1 /* 2 * (C) Copyright 2013 ADVANSEE 3 * Benoît Thébaudeau <benoit.thebaudeau@advansee.com> 4 * 5 * Based on Dirk Behme's 6 * https://github.com/dirkbehme/u-boot-imx6/blob/28b17e9/drivers/misc/imx_otp.c, 7 * which is based on Freescale's 8 * http://git.freescale.com/git/cgit.cgi/imx/uboot-imx.git/tree/drivers/misc/imx_otp.c?h=imx_v2009.08_1.1.0&id=9aa74e6, 9 * which is: 10 * Copyright (C) 2011 Freescale Semiconductor, Inc. 11 * 12 * See file CREDITS for list of people who contributed to this 13 * project. 14 * 15 * This program is free software; you can redistribute it and/or 16 * modify it under the terms of the GNU General Public License as 17 * published by the Free Software Foundation; either version 2 of 18 * the License, or (at your option) any later version. 19 * 20 * This program is distributed in the hope that it will be useful, 21 * but WITHOUT ANY WARRANTY; without even the implied warranty of 22 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 23 * GNU General Public License for more details. 24 * 25 * You should have received a copy of the GNU General Public License 26 * along with this program; if not, write to the Free Software 27 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 28 * MA 02111-1307 USA 29 */ 30 31 #include <common.h> 32 #include <fuse.h> 33 #include <asm/errno.h> 34 #include <asm/io.h> 35 #include <asm/arch/clock.h> 36 #include <asm/arch/imx-regs.h> 37 38 #define BO_CTRL_WR_UNLOCK 16 39 #define BM_CTRL_WR_UNLOCK 0xffff0000 40 #define BV_CTRL_WR_UNLOCK_KEY 0x3e77 41 #define BM_CTRL_ERROR 0x00000200 42 #define BM_CTRL_BUSY 0x00000100 43 #define BO_CTRL_ADDR 0 44 #define BM_CTRL_ADDR 0x0000007f 45 46 #define BO_TIMING_STROBE_READ 16 47 #define BM_TIMING_STROBE_READ 0x003f0000 48 #define BV_TIMING_STROBE_READ_NS 37 49 #define BO_TIMING_RELAX 12 50 #define BM_TIMING_RELAX 0x0000f000 51 #define BV_TIMING_RELAX_NS 17 52 #define BO_TIMING_STROBE_PROG 0 53 #define BM_TIMING_STROBE_PROG 0x00000fff 54 #define BV_TIMING_STROBE_PROG_US 10 55 56 #define BM_READ_CTRL_READ_FUSE 0x00000001 57 58 #define BF(value, field) (((value) << BO_##field) & BM_##field) 59 60 #define WRITE_POSTAMBLE_US 2 61 62 static void wait_busy(struct ocotp_regs *regs, unsigned int delay_us) 63 { 64 while (readl(®s->ctrl) & BM_CTRL_BUSY) 65 udelay(delay_us); 66 } 67 68 static void clear_error(struct ocotp_regs *regs) 69 { 70 writel(BM_CTRL_ERROR, ®s->ctrl_clr); 71 } 72 73 static int prepare_access(struct ocotp_regs **regs, u32 bank, u32 word, 74 int assert, const char *caller) 75 { 76 *regs = (struct ocotp_regs *)OCOTP_BASE_ADDR; 77 78 if (bank >= ARRAY_SIZE((*regs)->bank) || 79 word >= ARRAY_SIZE((*regs)->bank[0].fuse_regs) >> 2 || 80 !assert) { 81 printf("mxc_ocotp %s(): Invalid argument\n", caller); 82 return -EINVAL; 83 } 84 85 enable_ocotp_clk(1); 86 87 wait_busy(*regs, 1); 88 clear_error(*regs); 89 90 return 0; 91 } 92 93 static int finish_access(struct ocotp_regs *regs, const char *caller) 94 { 95 u32 err; 96 97 err = !!(readl(®s->ctrl) & BM_CTRL_ERROR); 98 clear_error(regs); 99 100 enable_ocotp_clk(0); 101 102 if (err) { 103 printf("mxc_ocotp %s(): Access protect error\n", caller); 104 return -EIO; 105 } 106 107 return 0; 108 } 109 110 static int prepare_read(struct ocotp_regs **regs, u32 bank, u32 word, u32 *val, 111 const char *caller) 112 { 113 return prepare_access(regs, bank, word, val != NULL, caller); 114 } 115 116 int fuse_read(u32 bank, u32 word, u32 *val) 117 { 118 struct ocotp_regs *regs; 119 int ret; 120 121 ret = prepare_read(®s, bank, word, val, __func__); 122 if (ret) 123 return ret; 124 125 *val = readl(®s->bank[bank].fuse_regs[word << 2]); 126 127 return finish_access(regs, __func__); 128 } 129 130 static void set_timing(struct ocotp_regs *regs) 131 { 132 u32 ipg_clk; 133 u32 relax, strobe_read, strobe_prog; 134 u32 timing; 135 136 ipg_clk = mxc_get_clock(MXC_IPG_CLK); 137 138 relax = DIV_ROUND_UP(ipg_clk * BV_TIMING_RELAX_NS, 1000000000) - 1; 139 strobe_read = DIV_ROUND_UP(ipg_clk * BV_TIMING_STROBE_READ_NS, 140 1000000000) + 2 * (relax + 1) - 1; 141 strobe_prog = DIV_ROUND(ipg_clk * BV_TIMING_STROBE_PROG_US, 1000000) + 142 2 * (relax + 1) - 1; 143 144 timing = BF(strobe_read, TIMING_STROBE_READ) | 145 BF(relax, TIMING_RELAX) | 146 BF(strobe_prog, TIMING_STROBE_PROG); 147 148 clrsetbits_le32(®s->timing, BM_TIMING_STROBE_READ | BM_TIMING_RELAX | 149 BM_TIMING_STROBE_PROG, timing); 150 } 151 152 static void setup_direct_access(struct ocotp_regs *regs, u32 bank, u32 word, 153 int write) 154 { 155 u32 wr_unlock = write ? BV_CTRL_WR_UNLOCK_KEY : 0; 156 u32 addr = bank << 3 | word; 157 158 set_timing(regs); 159 clrsetbits_le32(®s->ctrl, BM_CTRL_WR_UNLOCK | BM_CTRL_ADDR, 160 BF(wr_unlock, CTRL_WR_UNLOCK) | 161 BF(addr, CTRL_ADDR)); 162 } 163 164 int fuse_sense(u32 bank, u32 word, u32 *val) 165 { 166 struct ocotp_regs *regs; 167 int ret; 168 169 ret = prepare_read(®s, bank, word, val, __func__); 170 if (ret) 171 return ret; 172 173 setup_direct_access(regs, bank, word, false); 174 writel(BM_READ_CTRL_READ_FUSE, ®s->read_ctrl); 175 wait_busy(regs, 1); 176 *val = readl(®s->read_fuse_data); 177 178 return finish_access(regs, __func__); 179 } 180 181 static int prepare_write(struct ocotp_regs **regs, u32 bank, u32 word, 182 const char *caller) 183 { 184 return prepare_access(regs, bank, word, true, caller); 185 } 186 187 int fuse_prog(u32 bank, u32 word, u32 val) 188 { 189 struct ocotp_regs *regs; 190 int ret; 191 192 ret = prepare_write(®s, bank, word, __func__); 193 if (ret) 194 return ret; 195 196 setup_direct_access(regs, bank, word, true); 197 writel(val, ®s->data); 198 wait_busy(regs, BV_TIMING_STROBE_PROG_US); 199 udelay(WRITE_POSTAMBLE_US); 200 201 return finish_access(regs, __func__); 202 } 203 204 int fuse_override(u32 bank, u32 word, u32 val) 205 { 206 struct ocotp_regs *regs; 207 int ret; 208 209 ret = prepare_write(®s, bank, word, __func__); 210 if (ret) 211 return ret; 212 213 writel(val, ®s->bank[bank].fuse_regs[word << 2]); 214 215 return finish_access(regs, __func__); 216 } 217