1 /* SPDX-License-Identifier: GPL-2.0+ */ 2 /* 3 * (C) Copyright 2018 4 * Mario Six, Guntermann & Drunck GmbH, mario.six@gdsys.cc 5 */ 6 7 #ifndef __GDSYS_IOEP_H_ 8 #define __GDSYS_IOEP_H_ 9 10 /** 11 * struct io_generic_packet - header structure for GDSYS IOEP packets 12 * @target_address: Target protocol address of the packet. 13 * @source_address: Source protocol address of the packet. 14 * @packet_type: Packet type. 15 * @bc: Block counter (filled in by FPGA). 16 * @packet_length: Length of the packet's payload bytes. 17 */ 18 struct io_generic_packet { 19 u16 target_address; 20 u16 source_address; 21 u8 packet_type; 22 u8 bc; 23 u16 packet_length; 24 } __attribute__((__packed__)); 25 26 /** 27 * struct gdsys_ioep_regs - Registers of a IOEP device 28 * @transmit_data: Register that receives data to be sent 29 * @tx_control: TX control register 30 * @receive_data: Register filled with the received data 31 * @rx_tx_status: RX/TX status register 32 * @device_address: Register for setting/reading the device's address 33 * @target_address: Register for setting/reading the remote endpoint's address 34 * @int_enable: Interrupt/Interrupt enable register 35 */ 36 struct gdsys_ioep_regs { 37 u16 transmit_data; 38 u16 tx_control; 39 u16 receive_data; 40 u16 rx_tx_status; 41 u16 device_address; 42 u16 target_address; 43 u16 int_enable; 44 }; 45 46 /** 47 * gdsys_ioep_set() - Convenience macro to write registers of a IOEP device 48 * @map: Register map to write the value in 49 * @member: Name of the member in the gdsys_ioep_regs structure to write 50 * @val: Value to write to the register 51 */ 52 #define gdsys_ioep_set(map, member, val) \ 53 regmap_set(map, struct gdsys_ioep_regs, member, val) 54 55 /** 56 * gdsys_ioep_get() - Convenience macro to read registers of a IOEP device 57 * @map: Register map to read the value from 58 * @member: Name of the member in the gdsys_ioep_regs structure to read 59 * @valp: Pointer to buffer to read the register value into 60 */ 61 #define gdsys_ioep_get(map, member, valp) \ 62 regmap_get(map, struct gdsys_ioep_regs, member, valp) 63 64 /** 65 * enum rx_tx_status_values - Enum to describe the fields of the rx_tx_status 66 * register 67 * @STATE_TX_PACKET_BUILDING: The device is currently building a packet 68 * (and accepting data for it) 69 * @STATE_TX_TRANSMITTING: A packet is currenly being transmitted 70 * @STATE_TX_BUFFER_FULL: The TX buffer is full 71 * @STATE_TX_ERR: A TX error occurred 72 * @STATE_RECEIVE_TIMEOUT: A receive timeout occurred 73 * @STATE_PROC_RX_STORE_TIMEOUT: A RX store timeout for a processor packet 74 * occurred 75 * @STATE_PROC_RX_RECEIVE_TIMEOUT: A RX receive timeout for a processor packet 76 * occurred 77 * @STATE_RX_DIST_ERR: A error occurred in the distribution block 78 * @STATE_RX_LENGTH_ERR: A length invalid error occurred 79 * @STATE_RX_FRAME_CTR_ERR: A frame count error occurred (two 80 * non-increasing frame count numbers 81 * encountered) 82 * @STATE_RX_FCS_ERR: A CRC error occurred 83 * @STATE_RX_PACKET_DROPPED: A RX packet has been dropped 84 * @STATE_RX_DATA_LAST: The data to be read is the final data of the 85 * current packet 86 * @STATE_RX_DATA_FIRST: The data to be read is the first data of the 87 * current packet 88 * @STATE_RX_DATA_AVAILABLE: RX data is available to be read 89 */ 90 enum rx_tx_status_values { 91 STATE_TX_PACKET_BUILDING = BIT(0), 92 STATE_TX_TRANSMITTING = BIT(1), 93 STATE_TX_BUFFER_FULL = BIT(2), 94 STATE_TX_ERR = BIT(3), 95 STATE_RECEIVE_TIMEOUT = BIT(4), 96 STATE_PROC_RX_STORE_TIMEOUT = BIT(5), 97 STATE_PROC_RX_RECEIVE_TIMEOUT = BIT(6), 98 STATE_RX_DIST_ERR = BIT(7), 99 STATE_RX_LENGTH_ERR = BIT(8), 100 STATE_RX_FRAME_CTR_ERR = BIT(9), 101 STATE_RX_FCS_ERR = BIT(10), 102 STATE_RX_PACKET_DROPPED = BIT(11), 103 STATE_RX_DATA_LAST = BIT(12), 104 STATE_RX_DATA_FIRST = BIT(13), 105 STATE_RX_DATA_AVAILABLE = BIT(15), 106 }; 107 108 /** 109 * enum tx_control_values - Enum to describe the fields of the tx_control 110 * register 111 * @CTRL_PROC_RECEIVE_ENABLE: Enable packet reception for the processor 112 * @CTRL_FLUSH_TRANSMIT_BUFFER: Flush the transmit buffer (and send packet data) 113 */ 114 enum tx_control_values { 115 CTRL_PROC_RECEIVE_ENABLE = BIT(12), 116 CTRL_FLUSH_TRANSMIT_BUFFER = BIT(15), 117 }; 118 119 /** 120 * enum int_enable_values - Enum to describe the fields of the int_enable 121 * register 122 * @IRQ_CPU_TRANSMITBUFFER_FREE_STATUS: The transmit buffer is free (packet 123 * data can be transmitted to the 124 * device) 125 * @IRQ_CPU_PACKET_TRANSMITTED_EVENT: A packet has been transmitted 126 * @IRQ_NEW_CPU_PACKET_RECEIVED_EVENT: A new packet has been received 127 * @IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS: RX packet data are available to be 128 * read 129 */ 130 enum int_enable_values { 131 IRQ_CPU_TRANSMITBUFFER_FREE_STATUS = BIT(5), 132 IRQ_CPU_PACKET_TRANSMITTED_EVENT = BIT(6), 133 IRQ_NEW_CPU_PACKET_RECEIVED_EVENT = BIT(7), 134 IRQ_CPU_RECEIVE_DATA_AVAILABLE_STATUS = BIT(8), 135 }; 136 137 #endif /* __GDSYS_IOEP_H_ */ 138