1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2009-2013 ADVANSEE 4 * Benoît Thébaudeau <benoit.thebaudeau@advansee.com> 5 * 6 * Based on the mpc512x iim code: 7 * Copyright 2008 Silicon Turnkey Express, Inc. 8 * Martha Marx <mmarx@silicontkx.com> 9 */ 10 11 #include <common.h> 12 #include <fuse.h> 13 #include <linux/errno.h> 14 #include <asm/io.h> 15 #include <asm/arch/imx-regs.h> 16 #if defined(CONFIG_MX51) || defined(CONFIG_MX53) 17 #include <asm/arch/clock.h> 18 #endif 19 20 /* FSL IIM-specific constants */ 21 #define STAT_BUSY 0x80 22 #define STAT_PRGD 0x02 23 #define STAT_SNSD 0x01 24 25 #define STATM_PRGD_M 0x02 26 #define STATM_SNSD_M 0x01 27 28 #define ERR_PRGE 0x80 29 #define ERR_WPE 0x40 30 #define ERR_OPE 0x20 31 #define ERR_RPE 0x10 32 #define ERR_WLRE 0x08 33 #define ERR_SNSE 0x04 34 #define ERR_PARITYE 0x02 35 36 #define EMASK_PRGE_M 0x80 37 #define EMASK_WPE_M 0x40 38 #define EMASK_OPE_M 0x20 39 #define EMASK_RPE_M 0x10 40 #define EMASK_WLRE_M 0x08 41 #define EMASK_SNSE_M 0x04 42 #define EMASK_PARITYE_M 0x02 43 44 #define FCTL_DPC 0x80 45 #define FCTL_PRG_LENGTH_MASK 0x70 46 #define FCTL_ESNS_N 0x08 47 #define FCTL_ESNS_0 0x04 48 #define FCTL_ESNS_1 0x02 49 #define FCTL_PRG 0x01 50 51 #define UA_A_BANK_MASK 0x38 52 #define UA_A_ROWH_MASK 0x07 53 54 #define LA_A_ROWL_MASK 0xf8 55 #define LA_A_BIT_MASK 0x07 56 57 #define PREV_PROD_REV_MASK 0xf8 58 #define PREV_PROD_VT_MASK 0x07 59 60 /* Select the correct accessors depending on endianness */ 61 #if __BYTE_ORDER == __LITTLE_ENDIAN 62 #define iim_read32 in_le32 63 #define iim_write32 out_le32 64 #define iim_clrsetbits32 clrsetbits_le32 65 #define iim_clrbits32 clrbits_le32 66 #define iim_setbits32 setbits_le32 67 #elif __BYTE_ORDER == __BIG_ENDIAN 68 #define iim_read32 in_be32 69 #define iim_write32 out_be32 70 #define iim_clrsetbits32 clrsetbits_be32 71 #define iim_clrbits32 clrbits_be32 72 #define iim_setbits32 setbits_be32 73 #else 74 #error Endianess is not defined: please fix to continue 75 #endif 76 77 /* IIM control registers */ 78 struct fsl_iim { 79 u32 stat; 80 u32 statm; 81 u32 err; 82 u32 emask; 83 u32 fctl; 84 u32 ua; 85 u32 la; 86 u32 sdat; 87 u32 prev; 88 u32 srev; 89 u32 prg_p; 90 u32 scs[0x1f5]; 91 struct { 92 u32 word[0x100]; 93 } bank[8]; 94 }; 95 96 #if !defined(CONFIG_MX51) && !defined(CONFIG_MX53) 97 #define enable_efuse_prog_supply(enable) 98 #endif 99 100 static int prepare_access(struct fsl_iim **regs, u32 bank, u32 word, int assert, 101 const char *caller) 102 { 103 *regs = (struct fsl_iim *)IIM_BASE_ADDR; 104 105 if (bank >= ARRAY_SIZE((*regs)->bank) || 106 word >= ARRAY_SIZE((*regs)->bank[0].word) || 107 !assert) { 108 printf("fsl_iim %s(): Invalid argument\n", caller); 109 return -EINVAL; 110 } 111 112 return 0; 113 } 114 115 static void clear_status(struct fsl_iim *regs) 116 { 117 iim_setbits32(®s->stat, 0); 118 iim_setbits32(®s->err, 0); 119 } 120 121 static void finish_access(struct fsl_iim *regs, u32 *stat, u32 *err) 122 { 123 *stat = iim_read32(®s->stat); 124 *err = iim_read32(®s->err); 125 clear_status(regs); 126 } 127 128 static int prepare_read(struct fsl_iim **regs, u32 bank, u32 word, u32 *val, 129 const char *caller) 130 { 131 int ret; 132 133 ret = prepare_access(regs, bank, word, val != NULL, caller); 134 if (ret) 135 return ret; 136 137 clear_status(*regs); 138 139 return 0; 140 } 141 142 int fuse_read(u32 bank, u32 word, u32 *val) 143 { 144 struct fsl_iim *regs; 145 u32 stat, err; 146 int ret; 147 148 ret = prepare_read(®s, bank, word, val, __func__); 149 if (ret) 150 return ret; 151 152 *val = iim_read32(®s->bank[bank].word[word]); 153 finish_access(regs, &stat, &err); 154 155 if (err & ERR_RPE) { 156 puts("fsl_iim fuse_read(): Read protect error\n"); 157 return -EIO; 158 } 159 160 return 0; 161 } 162 163 static void direct_access(struct fsl_iim *regs, u32 bank, u32 word, u32 bit, 164 u32 fctl, u32 *stat, u32 *err) 165 { 166 iim_write32(®s->ua, bank << 3 | word >> 5); 167 iim_write32(®s->la, (word << 3 | bit) & 0xff); 168 if (fctl == FCTL_PRG) 169 iim_write32(®s->prg_p, 0xaa); 170 iim_setbits32(®s->fctl, fctl); 171 while (iim_read32(®s->stat) & STAT_BUSY) 172 udelay(20); 173 finish_access(regs, stat, err); 174 } 175 176 int fuse_sense(u32 bank, u32 word, u32 *val) 177 { 178 struct fsl_iim *regs; 179 u32 stat, err; 180 int ret; 181 182 ret = prepare_read(®s, bank, word, val, __func__); 183 if (ret) 184 return ret; 185 186 direct_access(regs, bank, word, 0, FCTL_ESNS_N, &stat, &err); 187 188 if (err & ERR_SNSE) { 189 puts("fsl_iim fuse_sense(): Explicit sense cycle error\n"); 190 return -EIO; 191 } 192 193 if (!(stat & STAT_SNSD)) { 194 puts("fsl_iim fuse_sense(): Explicit sense cycle did not complete\n"); 195 return -EIO; 196 } 197 198 *val = iim_read32(®s->sdat); 199 return 0; 200 } 201 202 static int prog_bit(struct fsl_iim *regs, u32 bank, u32 word, u32 bit) 203 { 204 u32 stat, err; 205 206 clear_status(regs); 207 direct_access(regs, bank, word, bit, FCTL_PRG, &stat, &err); 208 iim_write32(®s->prg_p, 0x00); 209 210 if (err & ERR_PRGE) { 211 puts("fsl_iim fuse_prog(): Program error\n"); 212 return -EIO; 213 } 214 215 if (err & ERR_WPE) { 216 puts("fsl_iim fuse_prog(): Write protect error\n"); 217 return -EIO; 218 } 219 220 if (!(stat & STAT_PRGD)) { 221 puts("fsl_iim fuse_prog(): Program did not complete\n"); 222 return -EIO; 223 } 224 225 return 0; 226 } 227 228 static int prepare_write(struct fsl_iim **regs, u32 bank, u32 word, u32 val, 229 const char *caller) 230 { 231 return prepare_access(regs, bank, word, !(val & ~0xff), caller); 232 } 233 234 int fuse_prog(u32 bank, u32 word, u32 val) 235 { 236 struct fsl_iim *regs; 237 u32 bit; 238 int ret; 239 240 ret = prepare_write(®s, bank, word, val, __func__); 241 if (ret) 242 return ret; 243 244 enable_efuse_prog_supply(1); 245 for (bit = 0; val; bit++, val >>= 1) 246 if (val & 0x01) { 247 ret = prog_bit(regs, bank, word, bit); 248 if (ret) { 249 enable_efuse_prog_supply(0); 250 return ret; 251 } 252 } 253 enable_efuse_prog_supply(0); 254 255 return 0; 256 } 257 258 int fuse_override(u32 bank, u32 word, u32 val) 259 { 260 struct fsl_iim *regs; 261 u32 stat, err; 262 int ret; 263 264 ret = prepare_write(®s, bank, word, val, __func__); 265 if (ret) 266 return ret; 267 268 clear_status(regs); 269 iim_write32(®s->bank[bank].word[word], val); 270 finish_access(regs, &stat, &err); 271 272 if (err & ERR_OPE) { 273 puts("fsl_iim fuse_override(): Override protect error\n"); 274 return -EIO; 275 } 276 277 return 0; 278 } 279