1# 2# Multifunction miscellaneous devices 3# 4 5menu "Multifunction device drivers" 6 7config MISC 8 bool "Enable Driver Model for Misc drivers" 9 depends on DM 10 help 11 Enable driver model for miscellaneous devices. This class is 12 used only for those do not fit other more general classes. A 13 set of generic read, write and ioctl methods may be used to 14 access the device. 15 16config ASPEED_AHBC 17 bool "Aspeed AHBC support" 18 depends on ARCH_ASPEED 19 help 20 Select this to enable ahbc driver for Aspeed SoC. 21 22config ASPEED_H2X 23 bool "Aspeed AHB to PCIe bus Bridge support" 24 depends on ARCH_ASPEED 25 help 26 Select this to enable AHB to PCIe bu Bridge driver for Aspeed SoC. 27 28config ASPEED_DP 29 bool "Aspeed Display Port firmware driver" 30 depends on ARCH_ASPEED 31 help 32 Select this to enable Diplay Port firmware driver 33 34config ASPEED_FSI 35 bool "Enable ASPEED FSI driver" 36 depends on ARCH_ASPEED 37 help 38 Support the FSI master present in the ASPEED system on chips. 39 40config ALTERA_SYSID 41 bool "Altera Sysid support" 42 depends on MISC 43 help 44 Select this to enable a sysid for Altera devices. Please find 45 details on the "Embedded Peripherals IP User Guide" of Altera. 46 47config ATSHA204A 48 bool "Support for Atmel ATSHA204A module" 49 depends on MISC 50 help 51 Enable support for I2C connected Atmel's ATSHA204A 52 CryptoAuthentication module found for example on the Turris Omnia 53 board. 54 55config ROCKCHIP_EFUSE 56 bool "Rockchip e-fuse support" 57 depends on MISC 58 help 59 Enable (read-only) access for the e-fuse block found in Rockchip 60 SoCs: accesses can either be made using byte addressing and a length 61 or through child-nodes that are generated based on the e-fuse map 62 retrieved from the DTS. 63 64 This driver currently supports the RK3399 only, but can easily be 65 extended (by porting the read function from the Linux kernel sources) 66 to support other recent Rockchip devices. 67 68config VEXPRESS_CONFIG 69 bool "Enable support for Arm Versatile Express config bus" 70 depends on MISC 71 help 72 If you say Y here, you will get support for accessing the 73 configuration bus on the Arm Versatile Express boards via 74 a sysreg driver. 75 76config CMD_CROS_EC 77 bool "Enable crosec command" 78 depends on CROS_EC 79 help 80 Enable command-line access to the Chrome OS EC (Embedded 81 Controller). This provides the 'crosec' command which has 82 a number of sub-commands for performing EC tasks such as 83 updating its flash, accessing a small saved context area 84 and talking to the I2C bus behind the EC (if there is one). 85 86config CROS_EC 87 bool "Enable Chrome OS EC" 88 help 89 Enable access to the Chrome OS EC. This is a separate 90 microcontroller typically available on a SPI bus on Chromebooks. It 91 provides access to the keyboard, some internal storage and may 92 control access to the battery and main PMIC depending on the 93 device. You can use the 'crosec' command to access it. 94 95config CROS_EC_I2C 96 bool "Enable Chrome OS EC I2C driver" 97 depends on CROS_EC 98 help 99 Enable I2C access to the Chrome OS EC. This is used on older 100 ARM Chromebooks such as snow and spring before the standard bus 101 changed to SPI. The EC will accept commands across the I2C using 102 a special message protocol, and provide responses. 103 104config CROS_EC_LPC 105 bool "Enable Chrome OS EC LPC driver" 106 depends on CROS_EC 107 help 108 Enable I2C access to the Chrome OS EC. This is used on x86 109 Chromebooks such as link and falco. The keyboard is provided 110 through a legacy port interface, so on x86 machines the main 111 function of the EC is power and thermal management. 112 113config CROS_EC_SANDBOX 114 bool "Enable Chrome OS EC sandbox driver" 115 depends on CROS_EC && SANDBOX 116 help 117 Enable a sandbox emulation of the Chrome OS EC. This supports 118 keyboard (use the -l flag to enable the LCD), verified boot context, 119 EC flash read/write/erase support and a few other things. It is 120 enough to perform a Chrome OS verified boot on sandbox. 121 122config CROS_EC_SPI 123 bool "Enable Chrome OS EC SPI driver" 124 depends on CROS_EC 125 help 126 Enable SPI access to the Chrome OS EC. This is used on newer 127 ARM Chromebooks such as pit, pi and nyan-big. The SPI interface 128 provides a faster and more robust interface than I2C but the bugs 129 are less interesting. 130 131config DS4510 132 bool "Enable support for DS4510 CPU supervisor" 133 help 134 Enable support for the Maxim DS4510 CPU supervisor. It has an 135 integrated 64-byte EEPROM, four programmable non-volatile I/O pins 136 and a configurable timer for the supervisor function. The device is 137 connected over I2C. 138 139config FSL_SEC_MON 140 bool "Enable FSL SEC_MON Driver" 141 help 142 Freescale Security Monitor block is responsible for monitoring 143 system states. 144 Security Monitor can be transitioned on any security failures, 145 like software violations or hardware security violations. 146 147config JZ4780_EFUSE 148 bool "Ingenic JZ4780 eFUSE support" 149 depends on ARCH_JZ47XX 150 help 151 This selects support for the eFUSE on Ingenic JZ4780 SoCs. 152 153config MXC_OCOTP 154 bool "Enable MXC OCOTP Driver" 155 help 156 If you say Y here, you will get support for the One Time 157 Programmable memory pages that are stored on the some 158 Freescale i.MX processors. 159 160config NUVOTON_NCT6102D 161 bool "Enable Nuvoton NCT6102D Super I/O driver" 162 help 163 If you say Y here, you will get support for the Nuvoton 164 NCT6102D Super I/O driver. This can be used to enable or 165 disable the legacy UART, the watchdog or other devices 166 in the Nuvoton Super IO chips on X86 platforms. 167 168config PWRSEQ 169 bool "Enable power-sequencing drivers" 170 depends on DM 171 help 172 Power-sequencing drivers provide support for controlling power for 173 devices. They are typically referenced by a phandle from another 174 device. When the device is started up, its power sequence can be 175 initiated. 176 177config SPL_PWRSEQ 178 bool "Enable power-sequencing drivers for SPL" 179 depends on PWRSEQ 180 help 181 Power-sequencing drivers provide support for controlling power for 182 devices. They are typically referenced by a phandle from another 183 device. When the device is started up, its power sequence can be 184 initiated. 185 186config PCA9551_LED 187 bool "Enable PCA9551 LED driver" 188 help 189 Enable driver for PCA9551 LED controller. This controller 190 is connected via I2C. So I2C needs to be enabled. 191 192config PCA9551_I2C_ADDR 193 hex "I2C address of PCA9551 LED controller" 194 depends on PCA9551_LED 195 default 0x60 196 help 197 The I2C address of the PCA9551 LED controller. 198 199config STM32MP_FUSE 200 bool "Enable STM32MP fuse wrapper providing the fuse API" 201 depends on ARCH_STM32MP && MISC 202 default y if CMD_FUSE 203 help 204 If you say Y here, you will get support for the fuse API (OTP) 205 for STM32MP architecture. 206 This API is needed for CMD_FUSE. 207 208config STM32_RCC 209 bool "Enable RCC driver for the STM32 SoC's family" 210 depends on (STM32 || ARCH_STM32MP) && MISC 211 help 212 Enable the STM32 RCC driver. The RCC block (Reset and Clock Control 213 block) is responsible of the management of the clock and reset 214 generation. 215 This driver is similar to an MFD driver in the Linux kernel. 216 217config TEGRA_CAR 218 bool "Enable support for the Tegra CAR driver" 219 depends on TEGRA_NO_BPMP 220 help 221 The Tegra CAR (Clock and Reset Controller) is a HW module that 222 controls almost all clocks and resets in a Tegra SoC. 223 224config TEGRA186_BPMP 225 bool "Enable support for the Tegra186 BPMP driver" 226 depends on TEGRA186 227 help 228 The Tegra BPMP (Boot and Power Management Processor) is a separate 229 auxiliary CPU embedded into Tegra to perform power management work, 230 and controls related features such as clocks, resets, power domains, 231 PMIC I2C bus, etc. This driver provides the core low-level 232 communication path by which feature-specific drivers (such as clock) 233 can make requests to the BPMP. This driver is similar to an MFD 234 driver in the Linux kernel. 235 236config TWL4030_LED 237 bool "Enable TWL4030 LED controller" 238 help 239 Enable this to add support for the TWL4030 LED controller. 240 241config WINBOND_W83627 242 bool "Enable Winbond Super I/O driver" 243 help 244 If you say Y here, you will get support for the Winbond 245 W83627 Super I/O driver. This can be used to enable the 246 legacy UART or other devices in the Winbond Super IO chips 247 on X86 platforms. 248 249config QFW 250 bool 251 help 252 Hidden option to enable QEMU fw_cfg interface. This will be selected by 253 either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE. 254 255config I2C_EEPROM 256 bool "Enable driver for generic I2C-attached EEPROMs" 257 depends on MISC 258 help 259 Enable a generic driver for EEPROMs attached via I2C. 260 261 262config SPL_I2C_EEPROM 263 bool "Enable driver for generic I2C-attached EEPROMs for SPL" 264 depends on MISC && SPL && SPL_DM 265 help 266 This option is an SPL-variant of the I2C_EEPROM option. 267 See the help of I2C_EEPROM for details. 268 269config ZYNQ_GEM_I2C_MAC_OFFSET 270 hex "Set the I2C MAC offset" 271 default 0x0 272 depends on DM_I2C 273 help 274 Set the MAC offset for i2C. 275 276if I2C_EEPROM 277 278config SYS_I2C_EEPROM_ADDR 279 hex "Chip address of the EEPROM device" 280 default 0 281 282config SYS_I2C_EEPROM_BUS 283 int "I2C bus of the EEPROM device." 284 default 0 285 286config SYS_EEPROM_SIZE 287 int "Size in bytes of the EEPROM device" 288 default 256 289 290config SYS_EEPROM_PAGE_WRITE_BITS 291 int "Number of bits used to address bytes in a single page" 292 default 0 293 help 294 The EEPROM page size is 2^SYS_EEPROM_PAGE_WRITE_BITS. 295 A 64 byte page, for example would require six bits. 296 297config SYS_EEPROM_PAGE_WRITE_DELAY_MS 298 int "Number of milliseconds to delay between page writes" 299 default 0 300 301config SYS_I2C_EEPROM_ADDR_LEN 302 int "Length in bytes of the EEPROM memory array address" 303 default 1 304 help 305 Note: This is NOT the chip address length! 306 307config SYS_I2C_EEPROM_ADDR_OVERFLOW 308 hex "EEPROM Address Overflow" 309 default 0 310 help 311 EEPROM chips that implement "address overflow" are ones 312 like Catalyst 24WC04/08/16 which has 9/10/11 bits of 313 address and the extra bits end up in the "chip address" bit 314 slots. This makes a 24WC08 (1Kbyte) chip look like four 256 315 byte chips. 316 317endif 318 319config GDSYS_RXAUI_CTRL 320 bool "Enable gdsys RXAUI control driver" 321 depends on MISC 322 help 323 Support gdsys FPGA's RXAUI control. 324 325config GDSYS_IOEP 326 bool "Enable gdsys IOEP driver" 327 depends on MISC 328 help 329 Support gdsys FPGA's IO endpoint driver. 330 331config MPC83XX_SERDES 332 bool "Enable MPC83xx serdes driver" 333 depends on MISC 334 help 335 Support for serdes found on MPC83xx SoCs. 336 337config FS_LOADER 338 bool "Enable loader driver for file system" 339 help 340 This is file system generic loader which can be used to load 341 the file image from the storage into target such as memory. 342 343 The consumer driver would then use this loader to program whatever, 344 ie. the FPGA device. 345 346config GDSYS_SOC 347 bool "Enable gdsys SOC driver" 348 depends on MISC 349 help 350 Support for gdsys IHS SOC, a simple bus associated with each gdsys 351 IHS (Integrated Hardware Systems) FPGA, which holds all devices whose 352 register maps are contained within the FPGA's register map. 353 354config IHS_FPGA 355 bool "Enable IHS FPGA driver" 356 depends on MISC 357 help 358 Support IHS (Integrated Hardware Systems) FPGA, the main FPGAs on 359 gdsys devices, which supply the majority of the functionality offered 360 by the devices. This driver supports both CON and CPU variants of the 361 devices, depending on the device tree entry. 362 363endmenu 364