1# 2# Multifunction miscellaneous devices 3# 4 5menu "Multifunction device drivers" 6 7config MISC 8 bool "Enable Driver Model for Misc drivers" 9 depends on DM 10 help 11 Enable driver model for miscellaneous devices. This class is 12 used only for those do not fit other more general classes. A 13 set of generic read, write and ioctl methods may be used to 14 access the device. 15 16config ALTERA_SYSID 17 bool "Altera Sysid support" 18 depends on MISC 19 help 20 Select this to enable a sysid for Altera devices. Please find 21 details on the "Embedded Peripherals IP User Guide" of Altera. 22 23config ATSHA204A 24 bool "Support for Atmel ATSHA204A module" 25 depends on MISC 26 help 27 Enable support for I2C connected Atmel's ATSHA204A 28 CryptoAuthentication module found for example on the Turris Omnia 29 board. 30 31config ROCKCHIP_EFUSE 32 bool "Rockchip e-fuse support" 33 depends on MISC 34 help 35 Enable (read-only) access for the e-fuse block found in Rockchip 36 SoCs: accesses can either be made using byte addressing and a length 37 or through child-nodes that are generated based on the e-fuse map 38 retrieved from the DTS. 39 40 This driver currently supports the RK3399 only, but can easily be 41 extended (by porting the read function from the Linux kernel sources) 42 to support other recent Rockchip devices. 43 44config VEXPRESS_CONFIG 45 bool "Enable support for Arm Versatile Express config bus" 46 depends on MISC 47 help 48 If you say Y here, you will get support for accessing the 49 configuration bus on the Arm Versatile Express boards via 50 a sysreg driver. 51 52config CMD_CROS_EC 53 bool "Enable crosec command" 54 depends on CROS_EC 55 help 56 Enable command-line access to the Chrome OS EC (Embedded 57 Controller). This provides the 'crosec' command which has 58 a number of sub-commands for performing EC tasks such as 59 updating its flash, accessing a small saved context area 60 and talking to the I2C bus behind the EC (if there is one). 61 62config CROS_EC 63 bool "Enable Chrome OS EC" 64 help 65 Enable access to the Chrome OS EC. This is a separate 66 microcontroller typically available on a SPI bus on Chromebooks. It 67 provides access to the keyboard, some internal storage and may 68 control access to the battery and main PMIC depending on the 69 device. You can use the 'crosec' command to access it. 70 71config CROS_EC_I2C 72 bool "Enable Chrome OS EC I2C driver" 73 depends on CROS_EC 74 help 75 Enable I2C access to the Chrome OS EC. This is used on older 76 ARM Chromebooks such as snow and spring before the standard bus 77 changed to SPI. The EC will accept commands across the I2C using 78 a special message protocol, and provide responses. 79 80config CROS_EC_LPC 81 bool "Enable Chrome OS EC LPC driver" 82 depends on CROS_EC 83 help 84 Enable I2C access to the Chrome OS EC. This is used on x86 85 Chromebooks such as link and falco. The keyboard is provided 86 through a legacy port interface, so on x86 machines the main 87 function of the EC is power and thermal management. 88 89config CROS_EC_SANDBOX 90 bool "Enable Chrome OS EC sandbox driver" 91 depends on CROS_EC && SANDBOX 92 help 93 Enable a sandbox emulation of the Chrome OS EC. This supports 94 keyboard (use the -l flag to enable the LCD), verified boot context, 95 EC flash read/write/erase support and a few other things. It is 96 enough to perform a Chrome OS verified boot on sandbox. 97 98config CROS_EC_SPI 99 bool "Enable Chrome OS EC SPI driver" 100 depends on CROS_EC 101 help 102 Enable SPI access to the Chrome OS EC. This is used on newer 103 ARM Chromebooks such as pit, pi and nyan-big. The SPI interface 104 provides a faster and more robust interface than I2C but the bugs 105 are less interesting. 106 107config DS4510 108 bool "Enable support for DS4510 CPU supervisor" 109 help 110 Enable support for the Maxim DS4510 CPU supervisor. It has an 111 integrated 64-byte EEPROM, four programmable non-volatile I/O pins 112 and a configurable timer for the supervisor function. The device is 113 connected over I2C. 114 115config FSL_SEC_MON 116 bool "Enable FSL SEC_MON Driver" 117 help 118 Freescale Security Monitor block is responsible for monitoring 119 system states. 120 Security Monitor can be transitioned on any security failures, 121 like software violations or hardware security violations. 122 123config MXC_OCOTP 124 bool "Enable MXC OCOTP Driver" 125 help 126 If you say Y here, you will get support for the One Time 127 Programmable memory pages that are stored on the some 128 Freescale i.MX processors. 129 130config NUVOTON_NCT6102D 131 bool "Enable Nuvoton NCT6102D Super I/O driver" 132 help 133 If you say Y here, you will get support for the Nuvoton 134 NCT6102D Super I/O driver. This can be used to enable or 135 disable the legacy UART, the watchdog or other devices 136 in the Nuvoton Super IO chips on X86 platforms. 137 138config PWRSEQ 139 bool "Enable power-sequencing drivers" 140 depends on DM 141 help 142 Power-sequencing drivers provide support for controlling power for 143 devices. They are typically referenced by a phandle from another 144 device. When the device is started up, its power sequence can be 145 initiated. 146 147config SPL_PWRSEQ 148 bool "Enable power-sequencing drivers for SPL" 149 depends on PWRSEQ 150 help 151 Power-sequencing drivers provide support for controlling power for 152 devices. They are typically referenced by a phandle from another 153 device. When the device is started up, its power sequence can be 154 initiated. 155 156config PCA9551_LED 157 bool "Enable PCA9551 LED driver" 158 help 159 Enable driver for PCA9551 LED controller. This controller 160 is connected via I2C. So I2C needs to be enabled. 161 162config PCA9551_I2C_ADDR 163 hex "I2C address of PCA9551 LED controller" 164 depends on PCA9551_LED 165 default 0x60 166 help 167 The I2C address of the PCA9551 LED controller. 168 169config STM32MP_FUSE 170 bool "Enable STM32MP fuse wrapper providing the fuse API" 171 depends on ARCH_STM32MP && MISC 172 default y if CMD_FUSE 173 help 174 If you say Y here, you will get support for the fuse API (OTP) 175 for STM32MP architecture. 176 This API is needed for CMD_FUSE. 177 178config STM32_RCC 179 bool "Enable RCC driver for the STM32 SoC's family" 180 depends on (STM32 || ARCH_STM32MP) && MISC 181 help 182 Enable the STM32 RCC driver. The RCC block (Reset and Clock Control 183 block) is responsible of the management of the clock and reset 184 generation. 185 This driver is similar to an MFD driver in the Linux kernel. 186 187config TEGRA_CAR 188 bool "Enable support for the Tegra CAR driver" 189 depends on TEGRA_NO_BPMP 190 help 191 The Tegra CAR (Clock and Reset Controller) is a HW module that 192 controls almost all clocks and resets in a Tegra SoC. 193 194config TEGRA186_BPMP 195 bool "Enable support for the Tegra186 BPMP driver" 196 depends on TEGRA186 197 help 198 The Tegra BPMP (Boot and Power Management Processor) is a separate 199 auxiliary CPU embedded into Tegra to perform power management work, 200 and controls related features such as clocks, resets, power domains, 201 PMIC I2C bus, etc. This driver provides the core low-level 202 communication path by which feature-specific drivers (such as clock) 203 can make requests to the BPMP. This driver is similar to an MFD 204 driver in the Linux kernel. 205 206config TWL4030_LED 207 bool "Enable TWL4030 LED controller" 208 help 209 Enable this to add support for the TWL4030 LED controller. 210 211config WINBOND_W83627 212 bool "Enable Winbond Super I/O driver" 213 help 214 If you say Y here, you will get support for the Winbond 215 W83627 Super I/O driver. This can be used to enable the 216 legacy UART or other devices in the Winbond Super IO chips 217 on X86 platforms. 218 219config QFW 220 bool 221 help 222 Hidden option to enable QEMU fw_cfg interface. This will be selected by 223 either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE. 224 225config I2C_EEPROM 226 bool "Enable driver for generic I2C-attached EEPROMs" 227 depends on MISC 228 help 229 Enable a generic driver for EEPROMs attached via I2C. 230 231 232config SPL_I2C_EEPROM 233 bool "Enable driver for generic I2C-attached EEPROMs for SPL" 234 depends on MISC && SPL && SPL_DM 235 help 236 This option is an SPL-variant of the I2C_EEPROM option. 237 See the help of I2C_EEPROM for details. 238 239config ZYNQ_GEM_I2C_MAC_OFFSET 240 hex "Set the I2C MAC offset" 241 default 0x0 242 help 243 Set the MAC offset for i2C. 244 245if I2C_EEPROM 246 247config SYS_I2C_EEPROM_ADDR 248 hex "Chip address of the EEPROM device" 249 default 0 250 251config SYS_I2C_EEPROM_BUS 252 int "I2C bus of the EEPROM device." 253 default 0 254 255config SYS_EEPROM_SIZE 256 int "Size in bytes of the EEPROM device" 257 default 256 258 259config SYS_EEPROM_PAGE_WRITE_BITS 260 int "Number of bits used to address bytes in a single page" 261 default 0 262 help 263 The EEPROM page size is 2^SYS_EEPROM_PAGE_WRITE_BITS. 264 A 64 byte page, for example would require six bits. 265 266config SYS_EEPROM_PAGE_WRITE_DELAY_MS 267 int "Number of milliseconds to delay between page writes" 268 default 0 269 270config SYS_I2C_EEPROM_ADDR_LEN 271 int "Length in bytes of the EEPROM memory array address" 272 default 1 273 help 274 Note: This is NOT the chip address length! 275 276config SYS_I2C_EEPROM_ADDR_OVERFLOW 277 hex "EEPROM Address Overflow" 278 default 0 279 help 280 EEPROM chips that implement "address overflow" are ones 281 like Catalyst 24WC04/08/16 which has 9/10/11 bits of 282 address and the extra bits end up in the "chip address" bit 283 slots. This makes a 24WC08 (1Kbyte) chip look like four 256 284 byte chips. 285 286endif 287 288config GDSYS_RXAUI_CTRL 289 bool "Enable gdsys RXAUI control driver" 290 depends on MISC 291 help 292 Support gdsys FPGA's RXAUI control. 293 294config GDSYS_IOEP 295 bool "Enable gdsys IOEP driver" 296 depends on MISC 297 help 298 Support gdsys FPGA's IO endpoint driver. 299 300config MPC83XX_SERDES 301 bool "Enable MPC83xx serdes driver" 302 depends on MISC 303 help 304 Support for serdes found on MPC83xx SoCs. 305 306config FS_LOADER 307 bool "Enable loader driver for file system" 308 help 309 This is file system generic loader which can be used to load 310 the file image from the storage into target such as memory. 311 312 The consumer driver would then use this loader to program whatever, 313 ie. the FPGA device. 314 315config GDSYS_SOC 316 bool "Enable gdsys SOC driver" 317 depends on MISC 318 help 319 Support for gdsys IHS SOC, a simple bus associated with each gdsys 320 IHS (Integrated Hardware Systems) FPGA, which holds all devices whose 321 register maps are contained within the FPGA's register map. 322 323config IHS_FPGA 324 bool "Enable IHS FPGA driver" 325 depends on MISC 326 help 327 Support IHS (Integrated Hardware Systems) FPGA, the main FPGAs on 328 gdsys devices, which supply the majority of the functionality offered 329 by the devices. This driver supports both CON and CPU variants of the 330 devices, depending on the device tree entry. 331 332endmenu 333