1# 2# Multifunction miscellaneous devices 3# 4 5menu "Multifunction device drivers" 6 7config MISC 8 bool "Enable Driver Model for Misc drivers" 9 depends on DM 10 help 11 Enable driver model for miscellaneous devices. This class is 12 used only for those do not fit other more general classes. A 13 set of generic read, write and ioctl methods may be used to 14 access the device. 15 16config ALTERA_SYSID 17 bool "Altera Sysid support" 18 depends on MISC 19 help 20 Select this to enable a sysid for Altera devices. Please find 21 details on the "Embedded Peripherals IP User Guide" of Altera. 22 23config ATSHA204A 24 bool "Support for Atmel ATSHA204A module" 25 depends on MISC 26 help 27 Enable support for I2C connected Atmel's ATSHA204A 28 CryptoAuthentication module found for example on the Turris Omnia 29 board. 30 31config ROCKCHIP_EFUSE 32 bool "Rockchip e-fuse support" 33 depends on MISC 34 help 35 Enable (read-only) access for the e-fuse block found in Rockchip 36 SoCs: accesses can either be made using byte addressing and a length 37 or through child-nodes that are generated based on the e-fuse map 38 retrieved from the DTS. 39 40 This driver currently supports the RK3399 only, but can easily be 41 extended (by porting the read function from the Linux kernel sources) 42 to support other recent Rockchip devices. 43 44config CMD_CROS_EC 45 bool "Enable crosec command" 46 depends on CROS_EC 47 help 48 Enable command-line access to the Chrome OS EC (Embedded 49 Controller). This provides the 'crosec' command which has 50 a number of sub-commands for performing EC tasks such as 51 updating its flash, accessing a small saved context area 52 and talking to the I2C bus behind the EC (if there is one). 53 54config CROS_EC 55 bool "Enable Chrome OS EC" 56 help 57 Enable access to the Chrome OS EC. This is a separate 58 microcontroller typically available on a SPI bus on Chromebooks. It 59 provides access to the keyboard, some internal storage and may 60 control access to the battery and main PMIC depending on the 61 device. You can use the 'crosec' command to access it. 62 63config CROS_EC_I2C 64 bool "Enable Chrome OS EC I2C driver" 65 depends on CROS_EC 66 help 67 Enable I2C access to the Chrome OS EC. This is used on older 68 ARM Chromebooks such as snow and spring before the standard bus 69 changed to SPI. The EC will accept commands across the I2C using 70 a special message protocol, and provide responses. 71 72config CROS_EC_LPC 73 bool "Enable Chrome OS EC LPC driver" 74 depends on CROS_EC 75 help 76 Enable I2C access to the Chrome OS EC. This is used on x86 77 Chromebooks such as link and falco. The keyboard is provided 78 through a legacy port interface, so on x86 machines the main 79 function of the EC is power and thermal management. 80 81config CROS_EC_SANDBOX 82 bool "Enable Chrome OS EC sandbox driver" 83 depends on CROS_EC && SANDBOX 84 help 85 Enable a sandbox emulation of the Chrome OS EC. This supports 86 keyboard (use the -l flag to enable the LCD), verified boot context, 87 EC flash read/write/erase support and a few other things. It is 88 enough to perform a Chrome OS verified boot on sandbox. 89 90config CROS_EC_SPI 91 bool "Enable Chrome OS EC SPI driver" 92 depends on CROS_EC 93 help 94 Enable SPI access to the Chrome OS EC. This is used on newer 95 ARM Chromebooks such as pit, pi and nyan-big. The SPI interface 96 provides a faster and more robust interface than I2C but the bugs 97 are less interesting. 98 99config DS4510 100 bool "Enable support for DS4510 CPU supervisor" 101 help 102 Enable support for the Maxim DS4510 CPU supervisor. It has an 103 integrated 64-byte EEPROM, four programmable non-volatile I/O pins 104 and a configurable timer for the supervisor function. The device is 105 connected over I2C. 106 107config FSL_SEC_MON 108 bool "Enable FSL SEC_MON Driver" 109 help 110 Freescale Security Monitor block is responsible for monitoring 111 system states. 112 Security Monitor can be transitioned on any security failures, 113 like software violations or hardware security violations. 114 115config MXC_OCOTP 116 bool "Enable MXC OCOTP Driver" 117 help 118 If you say Y here, you will get support for the One Time 119 Programmable memory pages that are stored on the some 120 Freescale i.MX processors. 121 122config NUVOTON_NCT6102D 123 bool "Enable Nuvoton NCT6102D Super I/O driver" 124 help 125 If you say Y here, you will get support for the Nuvoton 126 NCT6102D Super I/O driver. This can be used to enable or 127 disable the legacy UART, the watchdog or other devices 128 in the Nuvoton Super IO chips on X86 platforms. 129 130config PWRSEQ 131 bool "Enable power-sequencing drivers" 132 depends on DM 133 help 134 Power-sequencing drivers provide support for controlling power for 135 devices. They are typically referenced by a phandle from another 136 device. When the device is started up, its power sequence can be 137 initiated. 138 139config SPL_PWRSEQ 140 bool "Enable power-sequencing drivers for SPL" 141 depends on PWRSEQ 142 help 143 Power-sequencing drivers provide support for controlling power for 144 devices. They are typically referenced by a phandle from another 145 device. When the device is started up, its power sequence can be 146 initiated. 147 148config PCA9551_LED 149 bool "Enable PCA9551 LED driver" 150 help 151 Enable driver for PCA9551 LED controller. This controller 152 is connected via I2C. So I2C needs to be enabled. 153 154config PCA9551_I2C_ADDR 155 hex "I2C address of PCA9551 LED controller" 156 depends on PCA9551_LED 157 default 0x60 158 help 159 The I2C address of the PCA9551 LED controller. 160 161config STM32MP_FUSE 162 bool "Enable STM32MP fuse wrapper providing the fuse API" 163 depends on ARCH_STM32MP && MISC 164 default y if CMD_FUSE 165 help 166 If you say Y here, you will get support for the fuse API (OTP) 167 for STM32MP architecture. 168 This API is needed for CMD_FUSE. 169 170config STM32_RCC 171 bool "Enable RCC driver for the STM32 SoC's family" 172 depends on STM32 && MISC 173 help 174 Enable the STM32 RCC driver. The RCC block (Reset and Clock Control 175 block) is responsible of the management of the clock and reset 176 generation. 177 This driver is similar to an MFD driver in the Linux kernel. 178 179config TEGRA_CAR 180 bool "Enable support for the Tegra CAR driver" 181 depends on TEGRA_NO_BPMP 182 help 183 The Tegra CAR (Clock and Reset Controller) is a HW module that 184 controls almost all clocks and resets in a Tegra SoC. 185 186config TEGRA186_BPMP 187 bool "Enable support for the Tegra186 BPMP driver" 188 depends on TEGRA186 189 help 190 The Tegra BPMP (Boot and Power Management Processor) is a separate 191 auxiliary CPU embedded into Tegra to perform power management work, 192 and controls related features such as clocks, resets, power domains, 193 PMIC I2C bus, etc. This driver provides the core low-level 194 communication path by which feature-specific drivers (such as clock) 195 can make requests to the BPMP. This driver is similar to an MFD 196 driver in the Linux kernel. 197 198config WINBOND_W83627 199 bool "Enable Winbond Super I/O driver" 200 help 201 If you say Y here, you will get support for the Winbond 202 W83627 Super I/O driver. This can be used to enable the 203 legacy UART or other devices in the Winbond Super IO chips 204 on X86 platforms. 205 206config QFW 207 bool 208 help 209 Hidden option to enable QEMU fw_cfg interface. This will be selected by 210 either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE. 211 212config I2C_EEPROM 213 bool "Enable driver for generic I2C-attached EEPROMs" 214 depends on MISC 215 help 216 Enable a generic driver for EEPROMs attached via I2C. 217 218 219config SPL_I2C_EEPROM 220 bool "Enable driver for generic I2C-attached EEPROMs for SPL" 221 depends on MISC && SPL && SPL_DM 222 help 223 This option is an SPL-variant of the I2C_EEPROM option. 224 See the help of I2C_EEPROM for details. 225 226config ZYNQ_GEM_I2C_MAC_OFFSET 227 hex "Set the I2C MAC offset" 228 default 0x0 229 help 230 Set the MAC offset for i2C. 231 232if I2C_EEPROM 233 234config SYS_I2C_EEPROM_ADDR 235 hex "Chip address of the EEPROM device" 236 default 0 237 238config SYS_I2C_EEPROM_BUS 239 int "I2C bus of the EEPROM device." 240 default 0 241 242config SYS_EEPROM_SIZE 243 int "Size in bytes of the EEPROM device" 244 default 256 245 246config SYS_EEPROM_PAGE_WRITE_BITS 247 int "Number of bits used to address bytes in a single page" 248 default 0 249 help 250 The EEPROM page size is 2^SYS_EEPROM_PAGE_WRITE_BITS. 251 A 64 byte page, for example would require six bits. 252 253config SYS_EEPROM_PAGE_WRITE_DELAY_MS 254 int "Number of milliseconds to delay between page writes" 255 default 0 256 257config SYS_I2C_EEPROM_ADDR_LEN 258 int "Length in bytes of the EEPROM memory array address" 259 default 1 260 help 261 Note: This is NOT the chip address length! 262 263config SYS_I2C_EEPROM_ADDR_OVERFLOW 264 hex "EEPROM Address Overflow" 265 default 0 266 help 267 EEPROM chips that implement "address overflow" are ones 268 like Catalyst 24WC04/08/16 which has 9/10/11 bits of 269 address and the extra bits end up in the "chip address" bit 270 slots. This makes a 24WC08 (1Kbyte) chip look like four 256 271 byte chips. 272 273endif 274 275config GDSYS_RXAUI_CTRL 276 bool "Enable gdsys RXAUI control driver" 277 depends on MISC 278 help 279 Support gdsys FPGA's RXAUI control. 280endmenu 281