1# 2# Multifunction miscellaneous devices 3# 4 5menu "Multifunction device drivers" 6 7config MISC 8 bool "Enable Driver Model for Misc drivers" 9 depends on DM 10 help 11 Enable driver model for miscellaneous devices. This class is 12 used only for those do not fit other more general classes. A 13 set of generic read, write and ioctl methods may be used to 14 access the device. 15 16config ALTERA_SYSID 17 bool "Altera Sysid support" 18 depends on MISC 19 help 20 Select this to enable a sysid for Altera devices. Please find 21 details on the "Embedded Peripherals IP User Guide" of Altera. 22 23config ATSHA204A 24 bool "Support for Atmel ATSHA204A module" 25 depends on MISC 26 help 27 Enable support for I2C connected Atmel's ATSHA204A 28 CryptoAuthentication module found for example on the Turris Omnia 29 board. 30 31config ROCKCHIP_EFUSE 32 bool "Rockchip e-fuse support" 33 depends on MISC 34 help 35 Enable (read-only) access for the e-fuse block found in Rockchip 36 SoCs: accesses can either be made using byte addressing and a length 37 or through child-nodes that are generated based on the e-fuse map 38 retrieved from the DTS. 39 40 This driver currently supports the RK3399 only, but can easily be 41 extended (by porting the read function from the Linux kernel sources) 42 to support other recent Rockchip devices. 43 44config VEXPRESS_CONFIG 45 bool "Enable support for Arm Versatile Express config bus" 46 depends on MISC 47 help 48 If you say Y here, you will get support for accessing the 49 configuration bus on the Arm Versatile Express boards via 50 a sysreg driver. 51 52config CMD_CROS_EC 53 bool "Enable crosec command" 54 depends on CROS_EC 55 help 56 Enable command-line access to the Chrome OS EC (Embedded 57 Controller). This provides the 'crosec' command which has 58 a number of sub-commands for performing EC tasks such as 59 updating its flash, accessing a small saved context area 60 and talking to the I2C bus behind the EC (if there is one). 61 62config CROS_EC 63 bool "Enable Chrome OS EC" 64 help 65 Enable access to the Chrome OS EC. This is a separate 66 microcontroller typically available on a SPI bus on Chromebooks. It 67 provides access to the keyboard, some internal storage and may 68 control access to the battery and main PMIC depending on the 69 device. You can use the 'crosec' command to access it. 70 71config CROS_EC_I2C 72 bool "Enable Chrome OS EC I2C driver" 73 depends on CROS_EC 74 help 75 Enable I2C access to the Chrome OS EC. This is used on older 76 ARM Chromebooks such as snow and spring before the standard bus 77 changed to SPI. The EC will accept commands across the I2C using 78 a special message protocol, and provide responses. 79 80config CROS_EC_LPC 81 bool "Enable Chrome OS EC LPC driver" 82 depends on CROS_EC 83 help 84 Enable I2C access to the Chrome OS EC. This is used on x86 85 Chromebooks such as link and falco. The keyboard is provided 86 through a legacy port interface, so on x86 machines the main 87 function of the EC is power and thermal management. 88 89config CROS_EC_SANDBOX 90 bool "Enable Chrome OS EC sandbox driver" 91 depends on CROS_EC && SANDBOX 92 help 93 Enable a sandbox emulation of the Chrome OS EC. This supports 94 keyboard (use the -l flag to enable the LCD), verified boot context, 95 EC flash read/write/erase support and a few other things. It is 96 enough to perform a Chrome OS verified boot on sandbox. 97 98config CROS_EC_SPI 99 bool "Enable Chrome OS EC SPI driver" 100 depends on CROS_EC 101 help 102 Enable SPI access to the Chrome OS EC. This is used on newer 103 ARM Chromebooks such as pit, pi and nyan-big. The SPI interface 104 provides a faster and more robust interface than I2C but the bugs 105 are less interesting. 106 107config DS4510 108 bool "Enable support for DS4510 CPU supervisor" 109 help 110 Enable support for the Maxim DS4510 CPU supervisor. It has an 111 integrated 64-byte EEPROM, four programmable non-volatile I/O pins 112 and a configurable timer for the supervisor function. The device is 113 connected over I2C. 114 115config FSL_SEC_MON 116 bool "Enable FSL SEC_MON Driver" 117 help 118 Freescale Security Monitor block is responsible for monitoring 119 system states. 120 Security Monitor can be transitioned on any security failures, 121 like software violations or hardware security violations. 122 123config JZ4780_EFUSE 124 bool "Ingenic JZ4780 eFUSE support" 125 depends on ARCH_JZ47XX 126 help 127 This selects support for the eFUSE on Ingenic JZ4780 SoCs. 128 129config MXC_OCOTP 130 bool "Enable MXC OCOTP Driver" 131 help 132 If you say Y here, you will get support for the One Time 133 Programmable memory pages that are stored on the some 134 Freescale i.MX processors. 135 136config NUVOTON_NCT6102D 137 bool "Enable Nuvoton NCT6102D Super I/O driver" 138 help 139 If you say Y here, you will get support for the Nuvoton 140 NCT6102D Super I/O driver. This can be used to enable or 141 disable the legacy UART, the watchdog or other devices 142 in the Nuvoton Super IO chips on X86 platforms. 143 144config PWRSEQ 145 bool "Enable power-sequencing drivers" 146 depends on DM 147 help 148 Power-sequencing drivers provide support for controlling power for 149 devices. They are typically referenced by a phandle from another 150 device. When the device is started up, its power sequence can be 151 initiated. 152 153config SPL_PWRSEQ 154 bool "Enable power-sequencing drivers for SPL" 155 depends on PWRSEQ 156 help 157 Power-sequencing drivers provide support for controlling power for 158 devices. They are typically referenced by a phandle from another 159 device. When the device is started up, its power sequence can be 160 initiated. 161 162config PCA9551_LED 163 bool "Enable PCA9551 LED driver" 164 help 165 Enable driver for PCA9551 LED controller. This controller 166 is connected via I2C. So I2C needs to be enabled. 167 168config PCA9551_I2C_ADDR 169 hex "I2C address of PCA9551 LED controller" 170 depends on PCA9551_LED 171 default 0x60 172 help 173 The I2C address of the PCA9551 LED controller. 174 175config STM32MP_FUSE 176 bool "Enable STM32MP fuse wrapper providing the fuse API" 177 depends on ARCH_STM32MP && MISC 178 default y if CMD_FUSE 179 help 180 If you say Y here, you will get support for the fuse API (OTP) 181 for STM32MP architecture. 182 This API is needed for CMD_FUSE. 183 184config STM32_RCC 185 bool "Enable RCC driver for the STM32 SoC's family" 186 depends on (STM32 || ARCH_STM32MP) && MISC 187 help 188 Enable the STM32 RCC driver. The RCC block (Reset and Clock Control 189 block) is responsible of the management of the clock and reset 190 generation. 191 This driver is similar to an MFD driver in the Linux kernel. 192 193config TEGRA_CAR 194 bool "Enable support for the Tegra CAR driver" 195 depends on TEGRA_NO_BPMP 196 help 197 The Tegra CAR (Clock and Reset Controller) is a HW module that 198 controls almost all clocks and resets in a Tegra SoC. 199 200config TEGRA186_BPMP 201 bool "Enable support for the Tegra186 BPMP driver" 202 depends on TEGRA186 203 help 204 The Tegra BPMP (Boot and Power Management Processor) is a separate 205 auxiliary CPU embedded into Tegra to perform power management work, 206 and controls related features such as clocks, resets, power domains, 207 PMIC I2C bus, etc. This driver provides the core low-level 208 communication path by which feature-specific drivers (such as clock) 209 can make requests to the BPMP. This driver is similar to an MFD 210 driver in the Linux kernel. 211 212config TWL4030_LED 213 bool "Enable TWL4030 LED controller" 214 help 215 Enable this to add support for the TWL4030 LED controller. 216 217config WINBOND_W83627 218 bool "Enable Winbond Super I/O driver" 219 help 220 If you say Y here, you will get support for the Winbond 221 W83627 Super I/O driver. This can be used to enable the 222 legacy UART or other devices in the Winbond Super IO chips 223 on X86 platforms. 224 225config QFW 226 bool 227 help 228 Hidden option to enable QEMU fw_cfg interface. This will be selected by 229 either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE. 230 231config I2C_EEPROM 232 bool "Enable driver for generic I2C-attached EEPROMs" 233 depends on MISC 234 help 235 Enable a generic driver for EEPROMs attached via I2C. 236 237 238config SPL_I2C_EEPROM 239 bool "Enable driver for generic I2C-attached EEPROMs for SPL" 240 depends on MISC && SPL && SPL_DM 241 help 242 This option is an SPL-variant of the I2C_EEPROM option. 243 See the help of I2C_EEPROM for details. 244 245config ZYNQ_GEM_I2C_MAC_OFFSET 246 hex "Set the I2C MAC offset" 247 default 0x0 248 help 249 Set the MAC offset for i2C. 250 251if I2C_EEPROM 252 253config SYS_I2C_EEPROM_ADDR 254 hex "Chip address of the EEPROM device" 255 default 0 256 257config SYS_I2C_EEPROM_BUS 258 int "I2C bus of the EEPROM device." 259 default 0 260 261config SYS_EEPROM_SIZE 262 int "Size in bytes of the EEPROM device" 263 default 256 264 265config SYS_EEPROM_PAGE_WRITE_BITS 266 int "Number of bits used to address bytes in a single page" 267 default 0 268 help 269 The EEPROM page size is 2^SYS_EEPROM_PAGE_WRITE_BITS. 270 A 64 byte page, for example would require six bits. 271 272config SYS_EEPROM_PAGE_WRITE_DELAY_MS 273 int "Number of milliseconds to delay between page writes" 274 default 0 275 276config SYS_I2C_EEPROM_ADDR_LEN 277 int "Length in bytes of the EEPROM memory array address" 278 default 1 279 help 280 Note: This is NOT the chip address length! 281 282config SYS_I2C_EEPROM_ADDR_OVERFLOW 283 hex "EEPROM Address Overflow" 284 default 0 285 help 286 EEPROM chips that implement "address overflow" are ones 287 like Catalyst 24WC04/08/16 which has 9/10/11 bits of 288 address and the extra bits end up in the "chip address" bit 289 slots. This makes a 24WC08 (1Kbyte) chip look like four 256 290 byte chips. 291 292endif 293 294config GDSYS_RXAUI_CTRL 295 bool "Enable gdsys RXAUI control driver" 296 depends on MISC 297 help 298 Support gdsys FPGA's RXAUI control. 299 300config GDSYS_IOEP 301 bool "Enable gdsys IOEP driver" 302 depends on MISC 303 help 304 Support gdsys FPGA's IO endpoint driver. 305 306config MPC83XX_SERDES 307 bool "Enable MPC83xx serdes driver" 308 depends on MISC 309 help 310 Support for serdes found on MPC83xx SoCs. 311 312config FS_LOADER 313 bool "Enable loader driver for file system" 314 help 315 This is file system generic loader which can be used to load 316 the file image from the storage into target such as memory. 317 318 The consumer driver would then use this loader to program whatever, 319 ie. the FPGA device. 320 321config GDSYS_SOC 322 bool "Enable gdsys SOC driver" 323 depends on MISC 324 help 325 Support for gdsys IHS SOC, a simple bus associated with each gdsys 326 IHS (Integrated Hardware Systems) FPGA, which holds all devices whose 327 register maps are contained within the FPGA's register map. 328 329config IHS_FPGA 330 bool "Enable IHS FPGA driver" 331 depends on MISC 332 help 333 Support IHS (Integrated Hardware Systems) FPGA, the main FPGAs on 334 gdsys devices, which supply the majority of the functionality offered 335 by the devices. This driver supports both CON and CPU variants of the 336 devices, depending on the device tree entry. 337 338endmenu 339