1# 2# Multifunction miscellaneous devices 3# 4 5menu "Multifunction device drivers" 6 7config MISC 8 bool "Enable Driver Model for Misc drivers" 9 depends on DM 10 help 11 Enable driver model for miscellaneous devices. This class is 12 used only for those do not fit other more general classes. A 13 set of generic read, write and ioctl methods may be used to 14 access the device. 15 16config ASPEED_AHBC 17 bool "Aspeed AHBC support" 18 depends on ARCH_ASPEED 19 help 20 Select this to enable ahbc driver for Aspeed SoC. 21 22config ASPEED_H2X 23 bool "Aspeed AHB to PCIe bus Bridge support" 24 depends on ARCH_ASPEED 25 help 26 Select this to enable AHB to PCIe bu Bridge driver for Aspeed SoC. 27 28config ALTERA_SYSID 29 bool "Altera Sysid support" 30 depends on MISC 31 help 32 Select this to enable a sysid for Altera devices. Please find 33 details on the "Embedded Peripherals IP User Guide" of Altera. 34 35config ATSHA204A 36 bool "Support for Atmel ATSHA204A module" 37 depends on MISC 38 help 39 Enable support for I2C connected Atmel's ATSHA204A 40 CryptoAuthentication module found for example on the Turris Omnia 41 board. 42 43config ROCKCHIP_EFUSE 44 bool "Rockchip e-fuse support" 45 depends on MISC 46 help 47 Enable (read-only) access for the e-fuse block found in Rockchip 48 SoCs: accesses can either be made using byte addressing and a length 49 or through child-nodes that are generated based on the e-fuse map 50 retrieved from the DTS. 51 52 This driver currently supports the RK3399 only, but can easily be 53 extended (by porting the read function from the Linux kernel sources) 54 to support other recent Rockchip devices. 55 56config VEXPRESS_CONFIG 57 bool "Enable support for Arm Versatile Express config bus" 58 depends on MISC 59 help 60 If you say Y here, you will get support for accessing the 61 configuration bus on the Arm Versatile Express boards via 62 a sysreg driver. 63 64config CMD_CROS_EC 65 bool "Enable crosec command" 66 depends on CROS_EC 67 help 68 Enable command-line access to the Chrome OS EC (Embedded 69 Controller). This provides the 'crosec' command which has 70 a number of sub-commands for performing EC tasks such as 71 updating its flash, accessing a small saved context area 72 and talking to the I2C bus behind the EC (if there is one). 73 74config CROS_EC 75 bool "Enable Chrome OS EC" 76 help 77 Enable access to the Chrome OS EC. This is a separate 78 microcontroller typically available on a SPI bus on Chromebooks. It 79 provides access to the keyboard, some internal storage and may 80 control access to the battery and main PMIC depending on the 81 device. You can use the 'crosec' command to access it. 82 83config CROS_EC_I2C 84 bool "Enable Chrome OS EC I2C driver" 85 depends on CROS_EC 86 help 87 Enable I2C access to the Chrome OS EC. This is used on older 88 ARM Chromebooks such as snow and spring before the standard bus 89 changed to SPI. The EC will accept commands across the I2C using 90 a special message protocol, and provide responses. 91 92config CROS_EC_LPC 93 bool "Enable Chrome OS EC LPC driver" 94 depends on CROS_EC 95 help 96 Enable I2C access to the Chrome OS EC. This is used on x86 97 Chromebooks such as link and falco. The keyboard is provided 98 through a legacy port interface, so on x86 machines the main 99 function of the EC is power and thermal management. 100 101config CROS_EC_SANDBOX 102 bool "Enable Chrome OS EC sandbox driver" 103 depends on CROS_EC && SANDBOX 104 help 105 Enable a sandbox emulation of the Chrome OS EC. This supports 106 keyboard (use the -l flag to enable the LCD), verified boot context, 107 EC flash read/write/erase support and a few other things. It is 108 enough to perform a Chrome OS verified boot on sandbox. 109 110config CROS_EC_SPI 111 bool "Enable Chrome OS EC SPI driver" 112 depends on CROS_EC 113 help 114 Enable SPI access to the Chrome OS EC. This is used on newer 115 ARM Chromebooks such as pit, pi and nyan-big. The SPI interface 116 provides a faster and more robust interface than I2C but the bugs 117 are less interesting. 118 119config DS4510 120 bool "Enable support for DS4510 CPU supervisor" 121 help 122 Enable support for the Maxim DS4510 CPU supervisor. It has an 123 integrated 64-byte EEPROM, four programmable non-volatile I/O pins 124 and a configurable timer for the supervisor function. The device is 125 connected over I2C. 126 127config FSL_SEC_MON 128 bool "Enable FSL SEC_MON Driver" 129 help 130 Freescale Security Monitor block is responsible for monitoring 131 system states. 132 Security Monitor can be transitioned on any security failures, 133 like software violations or hardware security violations. 134 135config JZ4780_EFUSE 136 bool "Ingenic JZ4780 eFUSE support" 137 depends on ARCH_JZ47XX 138 help 139 This selects support for the eFUSE on Ingenic JZ4780 SoCs. 140 141config MXC_OCOTP 142 bool "Enable MXC OCOTP Driver" 143 help 144 If you say Y here, you will get support for the One Time 145 Programmable memory pages that are stored on the some 146 Freescale i.MX processors. 147 148config NUVOTON_NCT6102D 149 bool "Enable Nuvoton NCT6102D Super I/O driver" 150 help 151 If you say Y here, you will get support for the Nuvoton 152 NCT6102D Super I/O driver. This can be used to enable or 153 disable the legacy UART, the watchdog or other devices 154 in the Nuvoton Super IO chips on X86 platforms. 155 156config PWRSEQ 157 bool "Enable power-sequencing drivers" 158 depends on DM 159 help 160 Power-sequencing drivers provide support for controlling power for 161 devices. They are typically referenced by a phandle from another 162 device. When the device is started up, its power sequence can be 163 initiated. 164 165config SPL_PWRSEQ 166 bool "Enable power-sequencing drivers for SPL" 167 depends on PWRSEQ 168 help 169 Power-sequencing drivers provide support for controlling power for 170 devices. They are typically referenced by a phandle from another 171 device. When the device is started up, its power sequence can be 172 initiated. 173 174config PCA9551_LED 175 bool "Enable PCA9551 LED driver" 176 help 177 Enable driver for PCA9551 LED controller. This controller 178 is connected via I2C. So I2C needs to be enabled. 179 180config PCA9551_I2C_ADDR 181 hex "I2C address of PCA9551 LED controller" 182 depends on PCA9551_LED 183 default 0x60 184 help 185 The I2C address of the PCA9551 LED controller. 186 187config STM32MP_FUSE 188 bool "Enable STM32MP fuse wrapper providing the fuse API" 189 depends on ARCH_STM32MP && MISC 190 default y if CMD_FUSE 191 help 192 If you say Y here, you will get support for the fuse API (OTP) 193 for STM32MP architecture. 194 This API is needed for CMD_FUSE. 195 196config STM32_RCC 197 bool "Enable RCC driver for the STM32 SoC's family" 198 depends on (STM32 || ARCH_STM32MP) && MISC 199 help 200 Enable the STM32 RCC driver. The RCC block (Reset and Clock Control 201 block) is responsible of the management of the clock and reset 202 generation. 203 This driver is similar to an MFD driver in the Linux kernel. 204 205config TEGRA_CAR 206 bool "Enable support for the Tegra CAR driver" 207 depends on TEGRA_NO_BPMP 208 help 209 The Tegra CAR (Clock and Reset Controller) is a HW module that 210 controls almost all clocks and resets in a Tegra SoC. 211 212config TEGRA186_BPMP 213 bool "Enable support for the Tegra186 BPMP driver" 214 depends on TEGRA186 215 help 216 The Tegra BPMP (Boot and Power Management Processor) is a separate 217 auxiliary CPU embedded into Tegra to perform power management work, 218 and controls related features such as clocks, resets, power domains, 219 PMIC I2C bus, etc. This driver provides the core low-level 220 communication path by which feature-specific drivers (such as clock) 221 can make requests to the BPMP. This driver is similar to an MFD 222 driver in the Linux kernel. 223 224config TWL4030_LED 225 bool "Enable TWL4030 LED controller" 226 help 227 Enable this to add support for the TWL4030 LED controller. 228 229config WINBOND_W83627 230 bool "Enable Winbond Super I/O driver" 231 help 232 If you say Y here, you will get support for the Winbond 233 W83627 Super I/O driver. This can be used to enable the 234 legacy UART or other devices in the Winbond Super IO chips 235 on X86 platforms. 236 237config QFW 238 bool 239 help 240 Hidden option to enable QEMU fw_cfg interface. This will be selected by 241 either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE. 242 243config I2C_EEPROM 244 bool "Enable driver for generic I2C-attached EEPROMs" 245 depends on MISC 246 help 247 Enable a generic driver for EEPROMs attached via I2C. 248 249 250config SPL_I2C_EEPROM 251 bool "Enable driver for generic I2C-attached EEPROMs for SPL" 252 depends on MISC && SPL && SPL_DM 253 help 254 This option is an SPL-variant of the I2C_EEPROM option. 255 See the help of I2C_EEPROM for details. 256 257config ZYNQ_GEM_I2C_MAC_OFFSET 258 hex "Set the I2C MAC offset" 259 default 0x0 260 depends on DM_I2C 261 help 262 Set the MAC offset for i2C. 263 264if I2C_EEPROM 265 266config SYS_I2C_EEPROM_ADDR 267 hex "Chip address of the EEPROM device" 268 default 0 269 270config SYS_I2C_EEPROM_BUS 271 int "I2C bus of the EEPROM device." 272 default 0 273 274config SYS_EEPROM_SIZE 275 int "Size in bytes of the EEPROM device" 276 default 256 277 278config SYS_EEPROM_PAGE_WRITE_BITS 279 int "Number of bits used to address bytes in a single page" 280 default 0 281 help 282 The EEPROM page size is 2^SYS_EEPROM_PAGE_WRITE_BITS. 283 A 64 byte page, for example would require six bits. 284 285config SYS_EEPROM_PAGE_WRITE_DELAY_MS 286 int "Number of milliseconds to delay between page writes" 287 default 0 288 289config SYS_I2C_EEPROM_ADDR_LEN 290 int "Length in bytes of the EEPROM memory array address" 291 default 1 292 help 293 Note: This is NOT the chip address length! 294 295config SYS_I2C_EEPROM_ADDR_OVERFLOW 296 hex "EEPROM Address Overflow" 297 default 0 298 help 299 EEPROM chips that implement "address overflow" are ones 300 like Catalyst 24WC04/08/16 which has 9/10/11 bits of 301 address and the extra bits end up in the "chip address" bit 302 slots. This makes a 24WC08 (1Kbyte) chip look like four 256 303 byte chips. 304 305endif 306 307config GDSYS_RXAUI_CTRL 308 bool "Enable gdsys RXAUI control driver" 309 depends on MISC 310 help 311 Support gdsys FPGA's RXAUI control. 312 313config GDSYS_IOEP 314 bool "Enable gdsys IOEP driver" 315 depends on MISC 316 help 317 Support gdsys FPGA's IO endpoint driver. 318 319config MPC83XX_SERDES 320 bool "Enable MPC83xx serdes driver" 321 depends on MISC 322 help 323 Support for serdes found on MPC83xx SoCs. 324 325config FS_LOADER 326 bool "Enable loader driver for file system" 327 help 328 This is file system generic loader which can be used to load 329 the file image from the storage into target such as memory. 330 331 The consumer driver would then use this loader to program whatever, 332 ie. the FPGA device. 333 334config GDSYS_SOC 335 bool "Enable gdsys SOC driver" 336 depends on MISC 337 help 338 Support for gdsys IHS SOC, a simple bus associated with each gdsys 339 IHS (Integrated Hardware Systems) FPGA, which holds all devices whose 340 register maps are contained within the FPGA's register map. 341 342config IHS_FPGA 343 bool "Enable IHS FPGA driver" 344 depends on MISC 345 help 346 Support IHS (Integrated Hardware Systems) FPGA, the main FPGAs on 347 gdsys devices, which supply the majority of the functionality offered 348 by the devices. This driver supports both CON and CPU variants of the 349 devices, depending on the device tree entry. 350 351endmenu 352