10b11dbf7SMasahiro Yamada# 20b11dbf7SMasahiro Yamada# Multifunction miscellaneous devices 30b11dbf7SMasahiro Yamada# 40b11dbf7SMasahiro Yamada 50b11dbf7SMasahiro Yamadamenu "Multifunction device drivers" 60b11dbf7SMasahiro Yamada 74395e06eSThomas Chouconfig MISC 84395e06eSThomas Chou bool "Enable Driver Model for Misc drivers" 94395e06eSThomas Chou depends on DM 104395e06eSThomas Chou help 114395e06eSThomas Chou Enable driver model for miscellaneous devices. This class is 124395e06eSThomas Chou used only for those do not fit other more general classes. A 134395e06eSThomas Chou set of generic read, write and ioctl methods may be used to 144395e06eSThomas Chou access the device. 154395e06eSThomas Chou 16ca844dd8SThomas Chouconfig ALTERA_SYSID 17ca844dd8SThomas Chou bool "Altera Sysid support" 18ca844dd8SThomas Chou depends on MISC 19ca844dd8SThomas Chou help 20ca844dd8SThomas Chou Select this to enable a sysid for Altera devices. Please find 21ca844dd8SThomas Chou details on the "Embedded Peripherals IP User Guide" of Altera. 22ca844dd8SThomas Chou 23aa5eb9a3SMarek Behúnconfig ATSHA204A 24aa5eb9a3SMarek Behún bool "Support for Atmel ATSHA204A module" 25aa5eb9a3SMarek Behún depends on MISC 26aa5eb9a3SMarek Behún help 27aa5eb9a3SMarek Behún Enable support for I2C connected Atmel's ATSHA204A 28aa5eb9a3SMarek Behún CryptoAuthentication module found for example on the Turris Omnia 29aa5eb9a3SMarek Behún board. 30aa5eb9a3SMarek Behún 3149cd8e85SPhilipp Tomsichconfig ROCKCHIP_EFUSE 3249cd8e85SPhilipp Tomsich bool "Rockchip e-fuse support" 3349cd8e85SPhilipp Tomsich depends on MISC 3449cd8e85SPhilipp Tomsich help 3549cd8e85SPhilipp Tomsich Enable (read-only) access for the e-fuse block found in Rockchip 3649cd8e85SPhilipp Tomsich SoCs: accesses can either be made using byte addressing and a length 3749cd8e85SPhilipp Tomsich or through child-nodes that are generated based on the e-fuse map 3849cd8e85SPhilipp Tomsich retrieved from the DTS. 3949cd8e85SPhilipp Tomsich 4049cd8e85SPhilipp Tomsich This driver currently supports the RK3399 only, but can easily be 4149cd8e85SPhilipp Tomsich extended (by porting the read function from the Linux kernel sources) 4249cd8e85SPhilipp Tomsich to support other recent Rockchip devices. 4349cd8e85SPhilipp Tomsich 440fabfeb2SLiviu Dudauconfig VEXPRESS_CONFIG 450fabfeb2SLiviu Dudau bool "Enable support for Arm Versatile Express config bus" 460fabfeb2SLiviu Dudau depends on MISC 470fabfeb2SLiviu Dudau help 480fabfeb2SLiviu Dudau If you say Y here, you will get support for accessing the 490fabfeb2SLiviu Dudau configuration bus on the Arm Versatile Express boards via 500fabfeb2SLiviu Dudau a sysreg driver. 510fabfeb2SLiviu Dudau 526fb9ac15SSimon Glassconfig CMD_CROS_EC 536fb9ac15SSimon Glass bool "Enable crosec command" 546fb9ac15SSimon Glass depends on CROS_EC 556fb9ac15SSimon Glass help 566fb9ac15SSimon Glass Enable command-line access to the Chrome OS EC (Embedded 576fb9ac15SSimon Glass Controller). This provides the 'crosec' command which has 586fb9ac15SSimon Glass a number of sub-commands for performing EC tasks such as 596fb9ac15SSimon Glass updating its flash, accessing a small saved context area 606fb9ac15SSimon Glass and talking to the I2C bus behind the EC (if there is one). 616fb9ac15SSimon Glass 626fb9ac15SSimon Glassconfig CROS_EC 636fb9ac15SSimon Glass bool "Enable Chrome OS EC" 646fb9ac15SSimon Glass help 656fb9ac15SSimon Glass Enable access to the Chrome OS EC. This is a separate 666fb9ac15SSimon Glass microcontroller typically available on a SPI bus on Chromebooks. It 676fb9ac15SSimon Glass provides access to the keyboard, some internal storage and may 686fb9ac15SSimon Glass control access to the battery and main PMIC depending on the 696fb9ac15SSimon Glass device. You can use the 'crosec' command to access it. 706fb9ac15SSimon Glass 716fb9ac15SSimon Glassconfig CROS_EC_I2C 726fb9ac15SSimon Glass bool "Enable Chrome OS EC I2C driver" 736fb9ac15SSimon Glass depends on CROS_EC 746fb9ac15SSimon Glass help 756fb9ac15SSimon Glass Enable I2C access to the Chrome OS EC. This is used on older 766fb9ac15SSimon Glass ARM Chromebooks such as snow and spring before the standard bus 776fb9ac15SSimon Glass changed to SPI. The EC will accept commands across the I2C using 786fb9ac15SSimon Glass a special message protocol, and provide responses. 796fb9ac15SSimon Glass 806fb9ac15SSimon Glassconfig CROS_EC_LPC 816fb9ac15SSimon Glass bool "Enable Chrome OS EC LPC driver" 826fb9ac15SSimon Glass depends on CROS_EC 836fb9ac15SSimon Glass help 846fb9ac15SSimon Glass Enable I2C access to the Chrome OS EC. This is used on x86 856fb9ac15SSimon Glass Chromebooks such as link and falco. The keyboard is provided 866fb9ac15SSimon Glass through a legacy port interface, so on x86 machines the main 876fb9ac15SSimon Glass function of the EC is power and thermal management. 886fb9ac15SSimon Glass 8947cb8c65SSimon Glassconfig CROS_EC_SANDBOX 9047cb8c65SSimon Glass bool "Enable Chrome OS EC sandbox driver" 9147cb8c65SSimon Glass depends on CROS_EC && SANDBOX 9247cb8c65SSimon Glass help 9347cb8c65SSimon Glass Enable a sandbox emulation of the Chrome OS EC. This supports 9447cb8c65SSimon Glass keyboard (use the -l flag to enable the LCD), verified boot context, 9547cb8c65SSimon Glass EC flash read/write/erase support and a few other things. It is 9647cb8c65SSimon Glass enough to perform a Chrome OS verified boot on sandbox. 9747cb8c65SSimon Glass 986fb9ac15SSimon Glassconfig CROS_EC_SPI 996fb9ac15SSimon Glass bool "Enable Chrome OS EC SPI driver" 1006fb9ac15SSimon Glass depends on CROS_EC 1016fb9ac15SSimon Glass help 1026fb9ac15SSimon Glass Enable SPI access to the Chrome OS EC. This is used on newer 1036fb9ac15SSimon Glass ARM Chromebooks such as pit, pi and nyan-big. The SPI interface 1046fb9ac15SSimon Glass provides a faster and more robust interface than I2C but the bugs 1056fb9ac15SSimon Glass are less interesting. 1066fb9ac15SSimon Glass 107879704d8SSimon Glassconfig DS4510 108879704d8SSimon Glass bool "Enable support for DS4510 CPU supervisor" 109879704d8SSimon Glass help 110879704d8SSimon Glass Enable support for the Maxim DS4510 CPU supervisor. It has an 111879704d8SSimon Glass integrated 64-byte EEPROM, four programmable non-volatile I/O pins 112879704d8SSimon Glass and a configurable timer for the supervisor function. The device is 113879704d8SSimon Glass connected over I2C. 114879704d8SSimon Glass 115c12e0d93SPeng Fanconfig FSL_SEC_MON 116fe78378dSgaurav rana bool "Enable FSL SEC_MON Driver" 117fe78378dSgaurav rana help 118fe78378dSgaurav rana Freescale Security Monitor block is responsible for monitoring 119fe78378dSgaurav rana system states. 120fe78378dSgaurav rana Security Monitor can be transitioned on any security failures, 121fe78378dSgaurav rana like software violations or hardware security violations. 1221cdd9412SStefan Roese 1233e020f03SPeng Fanconfig MXC_OCOTP 1243e020f03SPeng Fan bool "Enable MXC OCOTP Driver" 1253e020f03SPeng Fan help 1263e020f03SPeng Fan If you say Y here, you will get support for the One Time 1273e020f03SPeng Fan Programmable memory pages that are stored on the some 1283e020f03SPeng Fan Freescale i.MX processors. 1293e020f03SPeng Fan 1304cf9e464SStefan Roeseconfig NUVOTON_NCT6102D 1314cf9e464SStefan Roese bool "Enable Nuvoton NCT6102D Super I/O driver" 1324cf9e464SStefan Roese help 1334cf9e464SStefan Roese If you say Y here, you will get support for the Nuvoton 1344cf9e464SStefan Roese NCT6102D Super I/O driver. This can be used to enable or 1354cf9e464SStefan Roese disable the legacy UART, the watchdog or other devices 1364cf9e464SStefan Roese in the Nuvoton Super IO chips on X86 platforms. 1374cf9e464SStefan Roese 1385fd6badbSSimon Glassconfig PWRSEQ 1395fd6badbSSimon Glass bool "Enable power-sequencing drivers" 1405fd6badbSSimon Glass depends on DM 1415fd6badbSSimon Glass help 1425fd6badbSSimon Glass Power-sequencing drivers provide support for controlling power for 1435fd6badbSSimon Glass devices. They are typically referenced by a phandle from another 1445fd6badbSSimon Glass device. When the device is started up, its power sequence can be 1455fd6badbSSimon Glass initiated. 1465fd6badbSSimon Glass 1475fd6badbSSimon Glassconfig SPL_PWRSEQ 1485fd6badbSSimon Glass bool "Enable power-sequencing drivers for SPL" 1495fd6badbSSimon Glass depends on PWRSEQ 1505fd6badbSSimon Glass help 1515fd6badbSSimon Glass Power-sequencing drivers provide support for controlling power for 1525fd6badbSSimon Glass devices. They are typically referenced by a phandle from another 1535fd6badbSSimon Glass device. When the device is started up, its power sequence can be 1545fd6badbSSimon Glass initiated. 1555fd6badbSSimon Glass 1561cdd9412SStefan Roeseconfig PCA9551_LED 1571cdd9412SStefan Roese bool "Enable PCA9551 LED driver" 1581cdd9412SStefan Roese help 1591cdd9412SStefan Roese Enable driver for PCA9551 LED controller. This controller 1601cdd9412SStefan Roese is connected via I2C. So I2C needs to be enabled. 1611cdd9412SStefan Roese 1621cdd9412SStefan Roeseconfig PCA9551_I2C_ADDR 1631cdd9412SStefan Roese hex "I2C address of PCA9551 LED controller" 1641cdd9412SStefan Roese depends on PCA9551_LED 1651cdd9412SStefan Roese default 0x60 1661cdd9412SStefan Roese help 1671cdd9412SStefan Roese The I2C address of the PCA9551 LED controller. 168f9917454SSimon Glass 169c3600e1fSPatrick Delaunayconfig STM32MP_FUSE 170c3600e1fSPatrick Delaunay bool "Enable STM32MP fuse wrapper providing the fuse API" 171c3600e1fSPatrick Delaunay depends on ARCH_STM32MP && MISC 172c3600e1fSPatrick Delaunay default y if CMD_FUSE 173c3600e1fSPatrick Delaunay help 174c3600e1fSPatrick Delaunay If you say Y here, you will get support for the fuse API (OTP) 175c3600e1fSPatrick Delaunay for STM32MP architecture. 176c3600e1fSPatrick Delaunay This API is needed for CMD_FUSE. 177c3600e1fSPatrick Delaunay 1784e280b91SChristophe Kerelloconfig STM32_RCC 1794e280b91SChristophe Kerello bool "Enable RCC driver for the STM32 SoC's family" 180d090cbabSPatrick Delaunay depends on (STM32 || ARCH_STM32MP) && MISC 1814e280b91SChristophe Kerello help 1824e280b91SChristophe Kerello Enable the STM32 RCC driver. The RCC block (Reset and Clock Control 1834e280b91SChristophe Kerello block) is responsible of the management of the clock and reset 1844e280b91SChristophe Kerello generation. 1854e280b91SChristophe Kerello This driver is similar to an MFD driver in the Linux kernel. 1864e280b91SChristophe Kerello 187bd3ee84aSStephen Warrenconfig TEGRA_CAR 188bd3ee84aSStephen Warren bool "Enable support for the Tegra CAR driver" 189bd3ee84aSStephen Warren depends on TEGRA_NO_BPMP 190bd3ee84aSStephen Warren help 191bd3ee84aSStephen Warren The Tegra CAR (Clock and Reset Controller) is a HW module that 192bd3ee84aSStephen Warren controls almost all clocks and resets in a Tegra SoC. 193bd3ee84aSStephen Warren 19473dd5c4cSStephen Warrenconfig TEGRA186_BPMP 19573dd5c4cSStephen Warren bool "Enable support for the Tegra186 BPMP driver" 19673dd5c4cSStephen Warren depends on TEGRA186 19773dd5c4cSStephen Warren help 19873dd5c4cSStephen Warren The Tegra BPMP (Boot and Power Management Processor) is a separate 19973dd5c4cSStephen Warren auxiliary CPU embedded into Tegra to perform power management work, 20073dd5c4cSStephen Warren and controls related features such as clocks, resets, power domains, 20173dd5c4cSStephen Warren PMIC I2C bus, etc. This driver provides the core low-level 20273dd5c4cSStephen Warren communication path by which feature-specific drivers (such as clock) 20373dd5c4cSStephen Warren can make requests to the BPMP. This driver is similar to an MFD 20473dd5c4cSStephen Warren driver in the Linux kernel. 20573dd5c4cSStephen Warren 206cc3fedb2SAdam Fordconfig TWL4030_LED 207cc3fedb2SAdam Ford bool "Enable TWL4030 LED controller" 208cc3fedb2SAdam Ford help 209cc3fedb2SAdam Ford Enable this to add support for the TWL4030 LED controller. 210cc3fedb2SAdam Ford 21185056932SStefan Roeseconfig WINBOND_W83627 21285056932SStefan Roese bool "Enable Winbond Super I/O driver" 21385056932SStefan Roese help 21485056932SStefan Roese If you say Y here, you will get support for the Winbond 21585056932SStefan Roese W83627 Super I/O driver. This can be used to enable the 21685056932SStefan Roese legacy UART or other devices in the Winbond Super IO chips 21785056932SStefan Roese on X86 platforms. 21885056932SStefan Roese 219fcf5c041SMiao Yanconfig QFW 220fcf5c041SMiao Yan bool 221fcf5c041SMiao Yan help 222fcf5c041SMiao Yan Hidden option to enable QEMU fw_cfg interface. This will be selected by 22318686590SMiao Yan either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE. 224fcf5c041SMiao Yan 225d7e28918Smario.six@gdsys.ccconfig I2C_EEPROM 226d7e28918Smario.six@gdsys.cc bool "Enable driver for generic I2C-attached EEPROMs" 227d7e28918Smario.six@gdsys.cc depends on MISC 228d7e28918Smario.six@gdsys.cc help 229d7e28918Smario.six@gdsys.cc Enable a generic driver for EEPROMs attached via I2C. 230e3f24d4fSAdam Ford 231d81a1de9SWenyou Yang 232d81a1de9SWenyou Yangconfig SPL_I2C_EEPROM 233d81a1de9SWenyou Yang bool "Enable driver for generic I2C-attached EEPROMs for SPL" 234d81a1de9SWenyou Yang depends on MISC && SPL && SPL_DM 235d81a1de9SWenyou Yang help 236d81a1de9SWenyou Yang This option is an SPL-variant of the I2C_EEPROM option. 237d81a1de9SWenyou Yang See the help of I2C_EEPROM for details. 238d81a1de9SWenyou Yang 2395c32de20SVipul Kumarconfig ZYNQ_GEM_I2C_MAC_OFFSET 2405c32de20SVipul Kumar hex "Set the I2C MAC offset" 2415c32de20SVipul Kumar default 0x0 2425c32de20SVipul Kumar help 2435c32de20SVipul Kumar Set the MAC offset for i2C. 2445c32de20SVipul Kumar 245e3f24d4fSAdam Fordif I2C_EEPROM 246e3f24d4fSAdam Ford 247e3f24d4fSAdam Fordconfig SYS_I2C_EEPROM_ADDR 248e3f24d4fSAdam Ford hex "Chip address of the EEPROM device" 249e3f24d4fSAdam Ford default 0 250e3f24d4fSAdam Ford 251e3f24d4fSAdam Fordconfig SYS_I2C_EEPROM_BUS 252e3f24d4fSAdam Ford int "I2C bus of the EEPROM device." 253e3f24d4fSAdam Ford default 0 254e3f24d4fSAdam Ford 255e3f24d4fSAdam Fordconfig SYS_EEPROM_SIZE 256e3f24d4fSAdam Ford int "Size in bytes of the EEPROM device" 257e3f24d4fSAdam Ford default 256 258e3f24d4fSAdam Ford 259e3f24d4fSAdam Fordconfig SYS_EEPROM_PAGE_WRITE_BITS 260e3f24d4fSAdam Ford int "Number of bits used to address bytes in a single page" 261e3f24d4fSAdam Ford default 0 262e3f24d4fSAdam Ford help 263e3f24d4fSAdam Ford The EEPROM page size is 2^SYS_EEPROM_PAGE_WRITE_BITS. 264e3f24d4fSAdam Ford A 64 byte page, for example would require six bits. 265e3f24d4fSAdam Ford 266e3f24d4fSAdam Fordconfig SYS_EEPROM_PAGE_WRITE_DELAY_MS 267e3f24d4fSAdam Ford int "Number of milliseconds to delay between page writes" 268e3f24d4fSAdam Ford default 0 269e3f24d4fSAdam Ford 270e3f24d4fSAdam Fordconfig SYS_I2C_EEPROM_ADDR_LEN 271e3f24d4fSAdam Ford int "Length in bytes of the EEPROM memory array address" 272e3f24d4fSAdam Ford default 1 273e3f24d4fSAdam Ford help 274e3f24d4fSAdam Ford Note: This is NOT the chip address length! 275e3f24d4fSAdam Ford 276e3f24d4fSAdam Fordconfig SYS_I2C_EEPROM_ADDR_OVERFLOW 277e3f24d4fSAdam Ford hex "EEPROM Address Overflow" 278e3f24d4fSAdam Ford default 0 279e3f24d4fSAdam Ford help 280e3f24d4fSAdam Ford EEPROM chips that implement "address overflow" are ones 281e3f24d4fSAdam Ford like Catalyst 24WC04/08/16 which has 9/10/11 bits of 282e3f24d4fSAdam Ford address and the extra bits end up in the "chip address" bit 283e3f24d4fSAdam Ford slots. This makes a 24WC08 (1Kbyte) chip look like four 256 284e3f24d4fSAdam Ford byte chips. 285e3f24d4fSAdam Ford 286e3f24d4fSAdam Fordendif 287e3f24d4fSAdam Ford 28886da8c12SMario Sixconfig GDSYS_RXAUI_CTRL 28986da8c12SMario Six bool "Enable gdsys RXAUI control driver" 29086da8c12SMario Six depends on MISC 29186da8c12SMario Six help 29286da8c12SMario Six Support gdsys FPGA's RXAUI control. 2937e86242bSMario Six 2947e86242bSMario Sixconfig GDSYS_IOEP 2957e86242bSMario Six bool "Enable gdsys IOEP driver" 2967e86242bSMario Six depends on MISC 2977e86242bSMario Six help 2987e86242bSMario Six Support gdsys FPGA's IO endpoint driver. 299d2166319SMario Six 300d2166319SMario Sixconfig MPC83XX_SERDES 301d2166319SMario Six bool "Enable MPC83xx serdes driver" 302d2166319SMario Six depends on MISC 303d2166319SMario Six help 304d2166319SMario Six Support for serdes found on MPC83xx SoCs. 305d2166319SMario Six 30662030004STien Fong Cheeconfig FS_LOADER 30762030004STien Fong Chee bool "Enable loader driver for file system" 30862030004STien Fong Chee help 30962030004STien Fong Chee This is file system generic loader which can be used to load 31062030004STien Fong Chee the file image from the storage into target such as memory. 31162030004STien Fong Chee 31262030004STien Fong Chee The consumer driver would then use this loader to program whatever, 31362030004STien Fong Chee ie. the FPGA device. 31462030004STien Fong Chee 315*c0a2b086SMario Sixconfig GDSYS_SOC 316*c0a2b086SMario Six bool "Enable gdsys SOC driver" 317*c0a2b086SMario Six depends on MISC 318*c0a2b086SMario Six help 319*c0a2b086SMario Six Support for gdsys IHS SOC, a simple bus associated with each gdsys 320*c0a2b086SMario Six IHS (Integrated Hardware Systems) FPGA, which holds all devices whose 321*c0a2b086SMario Six register maps are contained within the FPGA's register map. 322*c0a2b086SMario Six 3230b11dbf7SMasahiro Yamadaendmenu 324