10b11dbf7SMasahiro Yamada# 20b11dbf7SMasahiro Yamada# Multifunction miscellaneous devices 30b11dbf7SMasahiro Yamada# 40b11dbf7SMasahiro Yamada 50b11dbf7SMasahiro Yamadamenu "Multifunction device drivers" 60b11dbf7SMasahiro Yamada 74395e06eSThomas Chouconfig MISC 84395e06eSThomas Chou bool "Enable Driver Model for Misc drivers" 94395e06eSThomas Chou depends on DM 104395e06eSThomas Chou help 114395e06eSThomas Chou Enable driver model for miscellaneous devices. This class is 124395e06eSThomas Chou used only for those do not fit other more general classes. A 134395e06eSThomas Chou set of generic read, write and ioctl methods may be used to 144395e06eSThomas Chou access the device. 154395e06eSThomas Chou 16*979d74d9Sryan_chenconfig ASPEED_AHBC 17*979d74d9Sryan_chen bool "Aspeed AHBC support" 18*979d74d9Sryan_chen depends on ARCH_ASPEED 19*979d74d9Sryan_chen help 20*979d74d9Sryan_chen Select this to enable ahbc driver for Aspeed SoC. 21*979d74d9Sryan_chen 22*979d74d9Sryan_chenconfig ASPEED_H2X 23*979d74d9Sryan_chen bool "Aspeed AHB to PCIe bus Bridge support" 24*979d74d9Sryan_chen depends on ARCH_ASPEED 25*979d74d9Sryan_chen help 26*979d74d9Sryan_chen Select this to enable AHB to PCIe bu Bridge driver for Aspeed SoC. 27*979d74d9Sryan_chen 28ca844dd8SThomas Chouconfig ALTERA_SYSID 29ca844dd8SThomas Chou bool "Altera Sysid support" 30ca844dd8SThomas Chou depends on MISC 31ca844dd8SThomas Chou help 32ca844dd8SThomas Chou Select this to enable a sysid for Altera devices. Please find 33ca844dd8SThomas Chou details on the "Embedded Peripherals IP User Guide" of Altera. 34ca844dd8SThomas Chou 35aa5eb9a3SMarek Behúnconfig ATSHA204A 36aa5eb9a3SMarek Behún bool "Support for Atmel ATSHA204A module" 37aa5eb9a3SMarek Behún depends on MISC 38aa5eb9a3SMarek Behún help 39aa5eb9a3SMarek Behún Enable support for I2C connected Atmel's ATSHA204A 40aa5eb9a3SMarek Behún CryptoAuthentication module found for example on the Turris Omnia 41aa5eb9a3SMarek Behún board. 42aa5eb9a3SMarek Behún 4349cd8e85SPhilipp Tomsichconfig ROCKCHIP_EFUSE 4449cd8e85SPhilipp Tomsich bool "Rockchip e-fuse support" 4549cd8e85SPhilipp Tomsich depends on MISC 4649cd8e85SPhilipp Tomsich help 4749cd8e85SPhilipp Tomsich Enable (read-only) access for the e-fuse block found in Rockchip 4849cd8e85SPhilipp Tomsich SoCs: accesses can either be made using byte addressing and a length 4949cd8e85SPhilipp Tomsich or through child-nodes that are generated based on the e-fuse map 5049cd8e85SPhilipp Tomsich retrieved from the DTS. 5149cd8e85SPhilipp Tomsich 5249cd8e85SPhilipp Tomsich This driver currently supports the RK3399 only, but can easily be 5349cd8e85SPhilipp Tomsich extended (by porting the read function from the Linux kernel sources) 5449cd8e85SPhilipp Tomsich to support other recent Rockchip devices. 5549cd8e85SPhilipp Tomsich 560fabfeb2SLiviu Dudauconfig VEXPRESS_CONFIG 570fabfeb2SLiviu Dudau bool "Enable support for Arm Versatile Express config bus" 580fabfeb2SLiviu Dudau depends on MISC 590fabfeb2SLiviu Dudau help 600fabfeb2SLiviu Dudau If you say Y here, you will get support for accessing the 610fabfeb2SLiviu Dudau configuration bus on the Arm Versatile Express boards via 620fabfeb2SLiviu Dudau a sysreg driver. 630fabfeb2SLiviu Dudau 646fb9ac15SSimon Glassconfig CMD_CROS_EC 656fb9ac15SSimon Glass bool "Enable crosec command" 666fb9ac15SSimon Glass depends on CROS_EC 676fb9ac15SSimon Glass help 686fb9ac15SSimon Glass Enable command-line access to the Chrome OS EC (Embedded 696fb9ac15SSimon Glass Controller). This provides the 'crosec' command which has 706fb9ac15SSimon Glass a number of sub-commands for performing EC tasks such as 716fb9ac15SSimon Glass updating its flash, accessing a small saved context area 726fb9ac15SSimon Glass and talking to the I2C bus behind the EC (if there is one). 736fb9ac15SSimon Glass 746fb9ac15SSimon Glassconfig CROS_EC 756fb9ac15SSimon Glass bool "Enable Chrome OS EC" 766fb9ac15SSimon Glass help 776fb9ac15SSimon Glass Enable access to the Chrome OS EC. This is a separate 786fb9ac15SSimon Glass microcontroller typically available on a SPI bus on Chromebooks. It 796fb9ac15SSimon Glass provides access to the keyboard, some internal storage and may 806fb9ac15SSimon Glass control access to the battery and main PMIC depending on the 816fb9ac15SSimon Glass device. You can use the 'crosec' command to access it. 826fb9ac15SSimon Glass 836fb9ac15SSimon Glassconfig CROS_EC_I2C 846fb9ac15SSimon Glass bool "Enable Chrome OS EC I2C driver" 856fb9ac15SSimon Glass depends on CROS_EC 866fb9ac15SSimon Glass help 876fb9ac15SSimon Glass Enable I2C access to the Chrome OS EC. This is used on older 886fb9ac15SSimon Glass ARM Chromebooks such as snow and spring before the standard bus 896fb9ac15SSimon Glass changed to SPI. The EC will accept commands across the I2C using 906fb9ac15SSimon Glass a special message protocol, and provide responses. 916fb9ac15SSimon Glass 926fb9ac15SSimon Glassconfig CROS_EC_LPC 936fb9ac15SSimon Glass bool "Enable Chrome OS EC LPC driver" 946fb9ac15SSimon Glass depends on CROS_EC 956fb9ac15SSimon Glass help 966fb9ac15SSimon Glass Enable I2C access to the Chrome OS EC. This is used on x86 976fb9ac15SSimon Glass Chromebooks such as link and falco. The keyboard is provided 986fb9ac15SSimon Glass through a legacy port interface, so on x86 machines the main 996fb9ac15SSimon Glass function of the EC is power and thermal management. 1006fb9ac15SSimon Glass 10147cb8c65SSimon Glassconfig CROS_EC_SANDBOX 10247cb8c65SSimon Glass bool "Enable Chrome OS EC sandbox driver" 10347cb8c65SSimon Glass depends on CROS_EC && SANDBOX 10447cb8c65SSimon Glass help 10547cb8c65SSimon Glass Enable a sandbox emulation of the Chrome OS EC. This supports 10647cb8c65SSimon Glass keyboard (use the -l flag to enable the LCD), verified boot context, 10747cb8c65SSimon Glass EC flash read/write/erase support and a few other things. It is 10847cb8c65SSimon Glass enough to perform a Chrome OS verified boot on sandbox. 10947cb8c65SSimon Glass 1106fb9ac15SSimon Glassconfig CROS_EC_SPI 1116fb9ac15SSimon Glass bool "Enable Chrome OS EC SPI driver" 1126fb9ac15SSimon Glass depends on CROS_EC 1136fb9ac15SSimon Glass help 1146fb9ac15SSimon Glass Enable SPI access to the Chrome OS EC. This is used on newer 1156fb9ac15SSimon Glass ARM Chromebooks such as pit, pi and nyan-big. The SPI interface 1166fb9ac15SSimon Glass provides a faster and more robust interface than I2C but the bugs 1176fb9ac15SSimon Glass are less interesting. 1186fb9ac15SSimon Glass 119879704d8SSimon Glassconfig DS4510 120879704d8SSimon Glass bool "Enable support for DS4510 CPU supervisor" 121879704d8SSimon Glass help 122879704d8SSimon Glass Enable support for the Maxim DS4510 CPU supervisor. It has an 123879704d8SSimon Glass integrated 64-byte EEPROM, four programmable non-volatile I/O pins 124879704d8SSimon Glass and a configurable timer for the supervisor function. The device is 125879704d8SSimon Glass connected over I2C. 126879704d8SSimon Glass 127c12e0d93SPeng Fanconfig FSL_SEC_MON 128fe78378dSgaurav rana bool "Enable FSL SEC_MON Driver" 129fe78378dSgaurav rana help 130fe78378dSgaurav rana Freescale Security Monitor block is responsible for monitoring 131fe78378dSgaurav rana system states. 132fe78378dSgaurav rana Security Monitor can be transitioned on any security failures, 133fe78378dSgaurav rana like software violations or hardware security violations. 1341cdd9412SStefan Roese 135b5392c50SPaul Burtonconfig JZ4780_EFUSE 136b5392c50SPaul Burton bool "Ingenic JZ4780 eFUSE support" 137b5392c50SPaul Burton depends on ARCH_JZ47XX 138b5392c50SPaul Burton help 139b5392c50SPaul Burton This selects support for the eFUSE on Ingenic JZ4780 SoCs. 140b5392c50SPaul Burton 1413e020f03SPeng Fanconfig MXC_OCOTP 1423e020f03SPeng Fan bool "Enable MXC OCOTP Driver" 1433e020f03SPeng Fan help 1443e020f03SPeng Fan If you say Y here, you will get support for the One Time 1453e020f03SPeng Fan Programmable memory pages that are stored on the some 1463e020f03SPeng Fan Freescale i.MX processors. 1473e020f03SPeng Fan 1484cf9e464SStefan Roeseconfig NUVOTON_NCT6102D 1494cf9e464SStefan Roese bool "Enable Nuvoton NCT6102D Super I/O driver" 1504cf9e464SStefan Roese help 1514cf9e464SStefan Roese If you say Y here, you will get support for the Nuvoton 1524cf9e464SStefan Roese NCT6102D Super I/O driver. This can be used to enable or 1534cf9e464SStefan Roese disable the legacy UART, the watchdog or other devices 1544cf9e464SStefan Roese in the Nuvoton Super IO chips on X86 platforms. 1554cf9e464SStefan Roese 1565fd6badbSSimon Glassconfig PWRSEQ 1575fd6badbSSimon Glass bool "Enable power-sequencing drivers" 1585fd6badbSSimon Glass depends on DM 1595fd6badbSSimon Glass help 1605fd6badbSSimon Glass Power-sequencing drivers provide support for controlling power for 1615fd6badbSSimon Glass devices. They are typically referenced by a phandle from another 1625fd6badbSSimon Glass device. When the device is started up, its power sequence can be 1635fd6badbSSimon Glass initiated. 1645fd6badbSSimon Glass 1655fd6badbSSimon Glassconfig SPL_PWRSEQ 1665fd6badbSSimon Glass bool "Enable power-sequencing drivers for SPL" 1675fd6badbSSimon Glass depends on PWRSEQ 1685fd6badbSSimon Glass help 1695fd6badbSSimon Glass Power-sequencing drivers provide support for controlling power for 1705fd6badbSSimon Glass devices. They are typically referenced by a phandle from another 1715fd6badbSSimon Glass device. When the device is started up, its power sequence can be 1725fd6badbSSimon Glass initiated. 1735fd6badbSSimon Glass 1741cdd9412SStefan Roeseconfig PCA9551_LED 1751cdd9412SStefan Roese bool "Enable PCA9551 LED driver" 1761cdd9412SStefan Roese help 1771cdd9412SStefan Roese Enable driver for PCA9551 LED controller. This controller 1781cdd9412SStefan Roese is connected via I2C. So I2C needs to be enabled. 1791cdd9412SStefan Roese 1801cdd9412SStefan Roeseconfig PCA9551_I2C_ADDR 1811cdd9412SStefan Roese hex "I2C address of PCA9551 LED controller" 1821cdd9412SStefan Roese depends on PCA9551_LED 1831cdd9412SStefan Roese default 0x60 1841cdd9412SStefan Roese help 1851cdd9412SStefan Roese The I2C address of the PCA9551 LED controller. 186f9917454SSimon Glass 187c3600e1fSPatrick Delaunayconfig STM32MP_FUSE 188c3600e1fSPatrick Delaunay bool "Enable STM32MP fuse wrapper providing the fuse API" 189c3600e1fSPatrick Delaunay depends on ARCH_STM32MP && MISC 190c3600e1fSPatrick Delaunay default y if CMD_FUSE 191c3600e1fSPatrick Delaunay help 192c3600e1fSPatrick Delaunay If you say Y here, you will get support for the fuse API (OTP) 193c3600e1fSPatrick Delaunay for STM32MP architecture. 194c3600e1fSPatrick Delaunay This API is needed for CMD_FUSE. 195c3600e1fSPatrick Delaunay 1964e280b91SChristophe Kerelloconfig STM32_RCC 1974e280b91SChristophe Kerello bool "Enable RCC driver for the STM32 SoC's family" 198d090cbabSPatrick Delaunay depends on (STM32 || ARCH_STM32MP) && MISC 1994e280b91SChristophe Kerello help 2004e280b91SChristophe Kerello Enable the STM32 RCC driver. The RCC block (Reset and Clock Control 2014e280b91SChristophe Kerello block) is responsible of the management of the clock and reset 2024e280b91SChristophe Kerello generation. 2034e280b91SChristophe Kerello This driver is similar to an MFD driver in the Linux kernel. 2044e280b91SChristophe Kerello 205bd3ee84aSStephen Warrenconfig TEGRA_CAR 206bd3ee84aSStephen Warren bool "Enable support for the Tegra CAR driver" 207bd3ee84aSStephen Warren depends on TEGRA_NO_BPMP 208bd3ee84aSStephen Warren help 209bd3ee84aSStephen Warren The Tegra CAR (Clock and Reset Controller) is a HW module that 210bd3ee84aSStephen Warren controls almost all clocks and resets in a Tegra SoC. 211bd3ee84aSStephen Warren 21273dd5c4cSStephen Warrenconfig TEGRA186_BPMP 21373dd5c4cSStephen Warren bool "Enable support for the Tegra186 BPMP driver" 21473dd5c4cSStephen Warren depends on TEGRA186 21573dd5c4cSStephen Warren help 21673dd5c4cSStephen Warren The Tegra BPMP (Boot and Power Management Processor) is a separate 21773dd5c4cSStephen Warren auxiliary CPU embedded into Tegra to perform power management work, 21873dd5c4cSStephen Warren and controls related features such as clocks, resets, power domains, 21973dd5c4cSStephen Warren PMIC I2C bus, etc. This driver provides the core low-level 22073dd5c4cSStephen Warren communication path by which feature-specific drivers (such as clock) 22173dd5c4cSStephen Warren can make requests to the BPMP. This driver is similar to an MFD 22273dd5c4cSStephen Warren driver in the Linux kernel. 22373dd5c4cSStephen Warren 224cc3fedb2SAdam Fordconfig TWL4030_LED 225cc3fedb2SAdam Ford bool "Enable TWL4030 LED controller" 226cc3fedb2SAdam Ford help 227cc3fedb2SAdam Ford Enable this to add support for the TWL4030 LED controller. 228cc3fedb2SAdam Ford 22985056932SStefan Roeseconfig WINBOND_W83627 23085056932SStefan Roese bool "Enable Winbond Super I/O driver" 23185056932SStefan Roese help 23285056932SStefan Roese If you say Y here, you will get support for the Winbond 23385056932SStefan Roese W83627 Super I/O driver. This can be used to enable the 23485056932SStefan Roese legacy UART or other devices in the Winbond Super IO chips 23585056932SStefan Roese on X86 platforms. 23685056932SStefan Roese 237fcf5c041SMiao Yanconfig QFW 238fcf5c041SMiao Yan bool 239fcf5c041SMiao Yan help 240fcf5c041SMiao Yan Hidden option to enable QEMU fw_cfg interface. This will be selected by 24118686590SMiao Yan either CONFIG_CMD_QFW or CONFIG_GENERATE_ACPI_TABLE. 242fcf5c041SMiao Yan 243d7e28918Smario.six@gdsys.ccconfig I2C_EEPROM 244d7e28918Smario.six@gdsys.cc bool "Enable driver for generic I2C-attached EEPROMs" 245d7e28918Smario.six@gdsys.cc depends on MISC 246d7e28918Smario.six@gdsys.cc help 247d7e28918Smario.six@gdsys.cc Enable a generic driver for EEPROMs attached via I2C. 248e3f24d4fSAdam Ford 249d81a1de9SWenyou Yang 250d81a1de9SWenyou Yangconfig SPL_I2C_EEPROM 251d81a1de9SWenyou Yang bool "Enable driver for generic I2C-attached EEPROMs for SPL" 252d81a1de9SWenyou Yang depends on MISC && SPL && SPL_DM 253d81a1de9SWenyou Yang help 254d81a1de9SWenyou Yang This option is an SPL-variant of the I2C_EEPROM option. 255d81a1de9SWenyou Yang See the help of I2C_EEPROM for details. 256d81a1de9SWenyou Yang 2575c32de20SVipul Kumarconfig ZYNQ_GEM_I2C_MAC_OFFSET 2585c32de20SVipul Kumar hex "Set the I2C MAC offset" 2595c32de20SVipul Kumar default 0x0 260027b1134SMichal Simek depends on DM_I2C 2615c32de20SVipul Kumar help 2625c32de20SVipul Kumar Set the MAC offset for i2C. 2635c32de20SVipul Kumar 264e3f24d4fSAdam Fordif I2C_EEPROM 265e3f24d4fSAdam Ford 266e3f24d4fSAdam Fordconfig SYS_I2C_EEPROM_ADDR 267e3f24d4fSAdam Ford hex "Chip address of the EEPROM device" 268e3f24d4fSAdam Ford default 0 269e3f24d4fSAdam Ford 270e3f24d4fSAdam Fordconfig SYS_I2C_EEPROM_BUS 271e3f24d4fSAdam Ford int "I2C bus of the EEPROM device." 272e3f24d4fSAdam Ford default 0 273e3f24d4fSAdam Ford 274e3f24d4fSAdam Fordconfig SYS_EEPROM_SIZE 275e3f24d4fSAdam Ford int "Size in bytes of the EEPROM device" 276e3f24d4fSAdam Ford default 256 277e3f24d4fSAdam Ford 278e3f24d4fSAdam Fordconfig SYS_EEPROM_PAGE_WRITE_BITS 279e3f24d4fSAdam Ford int "Number of bits used to address bytes in a single page" 280e3f24d4fSAdam Ford default 0 281e3f24d4fSAdam Ford help 282e3f24d4fSAdam Ford The EEPROM page size is 2^SYS_EEPROM_PAGE_WRITE_BITS. 283e3f24d4fSAdam Ford A 64 byte page, for example would require six bits. 284e3f24d4fSAdam Ford 285e3f24d4fSAdam Fordconfig SYS_EEPROM_PAGE_WRITE_DELAY_MS 286e3f24d4fSAdam Ford int "Number of milliseconds to delay between page writes" 287e3f24d4fSAdam Ford default 0 288e3f24d4fSAdam Ford 289e3f24d4fSAdam Fordconfig SYS_I2C_EEPROM_ADDR_LEN 290e3f24d4fSAdam Ford int "Length in bytes of the EEPROM memory array address" 291e3f24d4fSAdam Ford default 1 292e3f24d4fSAdam Ford help 293e3f24d4fSAdam Ford Note: This is NOT the chip address length! 294e3f24d4fSAdam Ford 295e3f24d4fSAdam Fordconfig SYS_I2C_EEPROM_ADDR_OVERFLOW 296e3f24d4fSAdam Ford hex "EEPROM Address Overflow" 297e3f24d4fSAdam Ford default 0 298e3f24d4fSAdam Ford help 299e3f24d4fSAdam Ford EEPROM chips that implement "address overflow" are ones 300e3f24d4fSAdam Ford like Catalyst 24WC04/08/16 which has 9/10/11 bits of 301e3f24d4fSAdam Ford address and the extra bits end up in the "chip address" bit 302e3f24d4fSAdam Ford slots. This makes a 24WC08 (1Kbyte) chip look like four 256 303e3f24d4fSAdam Ford byte chips. 304e3f24d4fSAdam Ford 305e3f24d4fSAdam Fordendif 306e3f24d4fSAdam Ford 30786da8c12SMario Sixconfig GDSYS_RXAUI_CTRL 30886da8c12SMario Six bool "Enable gdsys RXAUI control driver" 30986da8c12SMario Six depends on MISC 31086da8c12SMario Six help 31186da8c12SMario Six Support gdsys FPGA's RXAUI control. 3127e86242bSMario Six 3137e86242bSMario Sixconfig GDSYS_IOEP 3147e86242bSMario Six bool "Enable gdsys IOEP driver" 3157e86242bSMario Six depends on MISC 3167e86242bSMario Six help 3177e86242bSMario Six Support gdsys FPGA's IO endpoint driver. 318d2166319SMario Six 319d2166319SMario Sixconfig MPC83XX_SERDES 320d2166319SMario Six bool "Enable MPC83xx serdes driver" 321d2166319SMario Six depends on MISC 322d2166319SMario Six help 323d2166319SMario Six Support for serdes found on MPC83xx SoCs. 324d2166319SMario Six 32562030004STien Fong Cheeconfig FS_LOADER 32662030004STien Fong Chee bool "Enable loader driver for file system" 32762030004STien Fong Chee help 32862030004STien Fong Chee This is file system generic loader which can be used to load 32962030004STien Fong Chee the file image from the storage into target such as memory. 33062030004STien Fong Chee 33162030004STien Fong Chee The consumer driver would then use this loader to program whatever, 33262030004STien Fong Chee ie. the FPGA device. 33362030004STien Fong Chee 334c0a2b086SMario Sixconfig GDSYS_SOC 335c0a2b086SMario Six bool "Enable gdsys SOC driver" 336c0a2b086SMario Six depends on MISC 337c0a2b086SMario Six help 338c0a2b086SMario Six Support for gdsys IHS SOC, a simple bus associated with each gdsys 339c0a2b086SMario Six IHS (Integrated Hardware Systems) FPGA, which holds all devices whose 340c0a2b086SMario Six register maps are contained within the FPGA's register map. 341c0a2b086SMario Six 342ab88bd2bSMario Sixconfig IHS_FPGA 343ab88bd2bSMario Six bool "Enable IHS FPGA driver" 344ab88bd2bSMario Six depends on MISC 345ab88bd2bSMario Six help 346ab88bd2bSMario Six Support IHS (Integrated Hardware Systems) FPGA, the main FPGAs on 347ab88bd2bSMario Six gdsys devices, which supply the majority of the functionality offered 348ab88bd2bSMario Six by the devices. This driver supports both CON and CPU variants of the 349ab88bd2bSMario Six devices, depending on the device tree entry. 350ab88bd2bSMario Six 3510b11dbf7SMasahiro Yamadaendmenu 352