1 /* 2 * Copyright (c) 2012 The Chromium OS Authors. All rights reserved. 3 * Copyright (c) 2010-2011 NVIDIA Corporation 4 * NVIDIA Corporation <www.nvidia.com> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <common.h> 26 #include <fdtdec.h> 27 #include <i2c.h> 28 #include <asm/io.h> 29 #include <asm/arch/clock.h> 30 #include <asm/arch/funcmux.h> 31 #include <asm/arch/gpio.h> 32 #include <asm/arch/pinmux.h> 33 #include <asm/arch-tegra/clk_rst.h> 34 #include <asm/arch-tegra/tegra_i2c.h> 35 36 DECLARE_GLOBAL_DATA_PTR; 37 38 static unsigned int i2c_bus_num; 39 40 /* Information about i2c controller */ 41 struct i2c_bus { 42 int id; 43 enum periph_id periph_id; 44 int speed; 45 int pinmux_config; 46 struct i2c_control *control; 47 struct i2c_ctlr *regs; 48 int is_dvc; /* DVC type, rather than I2C */ 49 int is_scs; /* single clock source (T114+) */ 50 int inited; /* bus is inited */ 51 }; 52 53 static struct i2c_bus i2c_controllers[TEGRA_I2C_NUM_CONTROLLERS]; 54 55 static void set_packet_mode(struct i2c_bus *i2c_bus) 56 { 57 u32 config; 58 59 config = I2C_CNFG_NEW_MASTER_FSM_MASK | I2C_CNFG_PACKET_MODE_MASK; 60 61 if (i2c_bus->is_dvc) { 62 struct dvc_ctlr *dvc = (struct dvc_ctlr *)i2c_bus->regs; 63 64 writel(config, &dvc->cnfg); 65 } else { 66 writel(config, &i2c_bus->regs->cnfg); 67 /* 68 * program I2C_SL_CNFG.NEWSL to ENABLE. This fixes probe 69 * issues, i.e., some slaves may be wrongly detected. 70 */ 71 setbits_le32(&i2c_bus->regs->sl_cnfg, I2C_SL_CNFG_NEWSL_MASK); 72 } 73 } 74 75 static void i2c_reset_controller(struct i2c_bus *i2c_bus) 76 { 77 /* Reset I2C controller. */ 78 reset_periph(i2c_bus->periph_id, 1); 79 80 /* re-program config register to packet mode */ 81 set_packet_mode(i2c_bus); 82 } 83 84 static void i2c_init_controller(struct i2c_bus *i2c_bus) 85 { 86 /* 87 * Use PLLP - DP-04508-001_v06 datasheet indicates a divisor of 8 88 * here, in section 23.3.1, but in fact we seem to need a factor of 89 * 16 to get the right frequency. 90 */ 91 clock_start_periph_pll(i2c_bus->periph_id, CLOCK_ID_PERIPH, 92 i2c_bus->speed * 2 * 8); 93 94 if (i2c_bus->is_scs) { 95 /* 96 * T114 I2C went to a single clock source for standard/fast and 97 * HS clock speeds. The new clock rate setting calculation is: 98 * SCL = CLK_SOURCE.I2C / 99 * (CLK_MULT_STD_FAST_MODE * (I2C_CLK_DIV_STD_FAST_MODE+1) * 100 * I2C FREQUENCY DIVISOR) as per the T114 TRM (sec 30.3.1). 101 * 102 * NOTE: We do this here, after the initial clock/pll start, 103 * because if we read the clk_div reg before the controller 104 * is running, we hang, and we need it for the new calc. 105 */ 106 int clk_div_stdfst_mode = readl(&i2c_bus->regs->clk_div) >> 16; 107 debug("%s: CLK_DIV_STD_FAST_MODE setting = %d\n", __func__, 108 clk_div_stdfst_mode); 109 110 clock_start_periph_pll(i2c_bus->periph_id, CLOCK_ID_PERIPH, 111 CLK_MULT_STD_FAST_MODE * (clk_div_stdfst_mode + 1) * 112 i2c_bus->speed * 2); 113 } 114 115 /* Reset I2C controller. */ 116 i2c_reset_controller(i2c_bus); 117 118 /* Configure I2C controller. */ 119 if (i2c_bus->is_dvc) { /* only for DVC I2C */ 120 struct dvc_ctlr *dvc = (struct dvc_ctlr *)i2c_bus->regs; 121 122 setbits_le32(&dvc->ctrl3, DVC_CTRL_REG3_I2C_HW_SW_PROG_MASK); 123 } 124 125 funcmux_select(i2c_bus->periph_id, i2c_bus->pinmux_config); 126 } 127 128 static void send_packet_headers( 129 struct i2c_bus *i2c_bus, 130 struct i2c_trans_info *trans, 131 u32 packet_id) 132 { 133 u32 data; 134 135 /* prepare header1: Header size = 0 Protocol = I2C, pktType = 0 */ 136 data = PROTOCOL_TYPE_I2C << PKT_HDR1_PROTOCOL_SHIFT; 137 data |= packet_id << PKT_HDR1_PKT_ID_SHIFT; 138 data |= i2c_bus->id << PKT_HDR1_CTLR_ID_SHIFT; 139 writel(data, &i2c_bus->control->tx_fifo); 140 debug("pkt header 1 sent (0x%x)\n", data); 141 142 /* prepare header2 */ 143 data = (trans->num_bytes - 1) << PKT_HDR2_PAYLOAD_SIZE_SHIFT; 144 writel(data, &i2c_bus->control->tx_fifo); 145 debug("pkt header 2 sent (0x%x)\n", data); 146 147 /* prepare IO specific header: configure the slave address */ 148 data = trans->address << PKT_HDR3_SLAVE_ADDR_SHIFT; 149 150 /* Enable Read if it is not a write transaction */ 151 if (!(trans->flags & I2C_IS_WRITE)) 152 data |= PKT_HDR3_READ_MODE_MASK; 153 154 /* Write I2C specific header */ 155 writel(data, &i2c_bus->control->tx_fifo); 156 debug("pkt header 3 sent (0x%x)\n", data); 157 } 158 159 static int wait_for_tx_fifo_empty(struct i2c_control *control) 160 { 161 u32 count; 162 int timeout_us = I2C_TIMEOUT_USEC; 163 164 while (timeout_us >= 0) { 165 count = (readl(&control->fifo_status) & TX_FIFO_EMPTY_CNT_MASK) 166 >> TX_FIFO_EMPTY_CNT_SHIFT; 167 if (count == I2C_FIFO_DEPTH) 168 return 1; 169 udelay(10); 170 timeout_us -= 10; 171 } 172 173 return 0; 174 } 175 176 static int wait_for_rx_fifo_notempty(struct i2c_control *control) 177 { 178 u32 count; 179 int timeout_us = I2C_TIMEOUT_USEC; 180 181 while (timeout_us >= 0) { 182 count = (readl(&control->fifo_status) & TX_FIFO_FULL_CNT_MASK) 183 >> TX_FIFO_FULL_CNT_SHIFT; 184 if (count) 185 return 1; 186 udelay(10); 187 timeout_us -= 10; 188 } 189 190 return 0; 191 } 192 193 static int wait_for_transfer_complete(struct i2c_control *control) 194 { 195 int int_status; 196 int timeout_us = I2C_TIMEOUT_USEC; 197 198 while (timeout_us >= 0) { 199 int_status = readl(&control->int_status); 200 if (int_status & I2C_INT_NO_ACK_MASK) 201 return -int_status; 202 if (int_status & I2C_INT_ARBITRATION_LOST_MASK) 203 return -int_status; 204 if (int_status & I2C_INT_XFER_COMPLETE_MASK) 205 return 0; 206 207 udelay(10); 208 timeout_us -= 10; 209 } 210 211 return -1; 212 } 213 214 static int send_recv_packets(struct i2c_bus *i2c_bus, 215 struct i2c_trans_info *trans) 216 { 217 struct i2c_control *control = i2c_bus->control; 218 u32 int_status; 219 u32 words; 220 u8 *dptr; 221 u32 local; 222 uchar last_bytes; 223 int error = 0; 224 int is_write = trans->flags & I2C_IS_WRITE; 225 226 /* clear status from previous transaction, XFER_COMPLETE, NOACK, etc. */ 227 int_status = readl(&control->int_status); 228 writel(int_status, &control->int_status); 229 230 send_packet_headers(i2c_bus, trans, 1); 231 232 words = DIV_ROUND_UP(trans->num_bytes, 4); 233 last_bytes = trans->num_bytes & 3; 234 dptr = trans->buf; 235 236 while (words) { 237 u32 *wptr = (u32 *)dptr; 238 239 if (is_write) { 240 /* deal with word alignment */ 241 if ((unsigned)dptr & 3) { 242 memcpy(&local, dptr, sizeof(u32)); 243 writel(local, &control->tx_fifo); 244 debug("pkt data sent (0x%x)\n", local); 245 } else { 246 writel(*wptr, &control->tx_fifo); 247 debug("pkt data sent (0x%x)\n", *wptr); 248 } 249 if (!wait_for_tx_fifo_empty(control)) { 250 error = -1; 251 goto exit; 252 } 253 } else { 254 if (!wait_for_rx_fifo_notempty(control)) { 255 error = -1; 256 goto exit; 257 } 258 /* 259 * for the last word, we read into our local buffer, 260 * in case that caller did not provide enough buffer. 261 */ 262 local = readl(&control->rx_fifo); 263 if ((words == 1) && last_bytes) 264 memcpy(dptr, (char *)&local, last_bytes); 265 else if ((unsigned)dptr & 3) 266 memcpy(dptr, &local, sizeof(u32)); 267 else 268 *wptr = local; 269 debug("pkt data received (0x%x)\n", local); 270 } 271 words--; 272 dptr += sizeof(u32); 273 } 274 275 if (wait_for_transfer_complete(control)) { 276 error = -1; 277 goto exit; 278 } 279 return 0; 280 exit: 281 /* error, reset the controller. */ 282 i2c_reset_controller(i2c_bus); 283 284 return error; 285 } 286 287 static int tegra_i2c_write_data(u32 addr, u8 *data, u32 len) 288 { 289 int error; 290 struct i2c_trans_info trans_info; 291 292 trans_info.address = addr; 293 trans_info.buf = data; 294 trans_info.flags = I2C_IS_WRITE; 295 trans_info.num_bytes = len; 296 trans_info.is_10bit_address = 0; 297 298 error = send_recv_packets(&i2c_controllers[i2c_bus_num], &trans_info); 299 if (error) 300 debug("tegra_i2c_write_data: Error (%d) !!!\n", error); 301 302 return error; 303 } 304 305 static int tegra_i2c_read_data(u32 addr, u8 *data, u32 len) 306 { 307 int error; 308 struct i2c_trans_info trans_info; 309 310 trans_info.address = addr | 1; 311 trans_info.buf = data; 312 trans_info.flags = 0; 313 trans_info.num_bytes = len; 314 trans_info.is_10bit_address = 0; 315 316 error = send_recv_packets(&i2c_controllers[i2c_bus_num], &trans_info); 317 if (error) 318 debug("tegra_i2c_read_data: Error (%d) !!!\n", error); 319 320 return error; 321 } 322 323 #ifndef CONFIG_OF_CONTROL 324 #error "Please enable device tree support to use this driver" 325 #endif 326 327 unsigned int i2c_get_bus_speed(void) 328 { 329 return i2c_controllers[i2c_bus_num].speed; 330 } 331 332 int i2c_set_bus_speed(unsigned int speed) 333 { 334 struct i2c_bus *i2c_bus; 335 336 i2c_bus = &i2c_controllers[i2c_bus_num]; 337 i2c_bus->speed = speed; 338 i2c_init_controller(i2c_bus); 339 340 return 0; 341 } 342 343 static int i2c_get_config(const void *blob, int node, struct i2c_bus *i2c_bus) 344 { 345 i2c_bus->regs = (struct i2c_ctlr *)fdtdec_get_addr(blob, node, "reg"); 346 347 /* 348 * We don't have a binding for pinmux yet. Leave it out for now. So 349 * far no one needs anything other than the default. 350 */ 351 i2c_bus->pinmux_config = FUNCMUX_DEFAULT; 352 i2c_bus->speed = fdtdec_get_int(blob, node, "clock-frequency", 0); 353 i2c_bus->periph_id = clock_decode_periph_id(blob, node); 354 355 /* 356 * We can't specify the pinmux config in the fdt, so I2C2 will not 357 * work on Seaboard. It normally has no devices on it anyway. 358 * You could add in this little hack if you need to use it. 359 * The correct solution is a pinmux binding in the fdt. 360 * 361 * if (i2c_bus->periph_id == PERIPH_ID_I2C2) 362 * i2c_bus->pinmux_config = FUNCMUX_I2C2_PTA; 363 */ 364 if (i2c_bus->periph_id == -1) 365 return -FDT_ERR_NOTFOUND; 366 367 return 0; 368 } 369 370 /* 371 * Process a list of nodes, adding them to our list of I2C ports. 372 * 373 * @param blob fdt blob 374 * @param node_list list of nodes to process (any <=0 are ignored) 375 * @param count number of nodes to process 376 * @param is_dvc 1 if these are DVC ports, 0 if standard I2C 377 * @param is_scs 1 if this HW uses a single clock source (T114+) 378 * @return 0 if ok, -1 on error 379 */ 380 static int process_nodes(const void *blob, int node_list[], int count, 381 int is_dvc, int is_scs) 382 { 383 struct i2c_bus *i2c_bus; 384 int i; 385 386 /* build the i2c_controllers[] for each controller */ 387 for (i = 0; i < count; i++) { 388 int node = node_list[i]; 389 390 if (node <= 0) 391 continue; 392 393 i2c_bus = &i2c_controllers[i]; 394 i2c_bus->id = i; 395 396 if (i2c_get_config(blob, node, i2c_bus)) { 397 printf("i2c_init_board: failed to decode bus %d\n", i); 398 return -1; 399 } 400 401 i2c_bus->is_scs = is_scs; 402 403 i2c_bus->is_dvc = is_dvc; 404 if (is_dvc) { 405 i2c_bus->control = 406 &((struct dvc_ctlr *)i2c_bus->regs)->control; 407 } else { 408 i2c_bus->control = &i2c_bus->regs->control; 409 } 410 debug("%s: controller bus %d at %p, periph_id %d, speed %d: ", 411 is_dvc ? "dvc" : "i2c", i, i2c_bus->regs, 412 i2c_bus->periph_id, i2c_bus->speed); 413 i2c_init_controller(i2c_bus); 414 debug("ok\n"); 415 i2c_bus->inited = 1; 416 417 /* Mark position as used */ 418 node_list[i] = -1; 419 } 420 421 return 0; 422 } 423 424 /* Sadly there is no error return from this function */ 425 void i2c_init_board(void) 426 { 427 int node_list[TEGRA_I2C_NUM_CONTROLLERS]; 428 const void *blob = gd->fdt_blob; 429 int count; 430 431 /* First check for newer (T114+) I2C ports */ 432 count = fdtdec_find_aliases_for_id(blob, "i2c", 433 COMPAT_NVIDIA_TEGRA114_I2C, node_list, 434 TEGRA_I2C_NUM_CONTROLLERS); 435 if (process_nodes(blob, node_list, count, 0, 1)) 436 return; 437 438 /* Now get the older (T20/T30) normal I2C ports */ 439 count = fdtdec_find_aliases_for_id(blob, "i2c", 440 COMPAT_NVIDIA_TEGRA20_I2C, node_list, 441 TEGRA_I2C_NUM_CONTROLLERS); 442 if (process_nodes(blob, node_list, count, 0, 0)) 443 return; 444 445 /* Now look for dvc ports */ 446 count = fdtdec_add_aliases_for_id(blob, "i2c", 447 COMPAT_NVIDIA_TEGRA20_DVC, node_list, 448 TEGRA_I2C_NUM_CONTROLLERS); 449 if (process_nodes(blob, node_list, count, 1, 0)) 450 return; 451 } 452 453 void i2c_init(int speed, int slaveaddr) 454 { 455 /* This will override the speed selected in the fdt for that port */ 456 debug("i2c_init(speed=%u, slaveaddr=0x%x)\n", speed, slaveaddr); 457 i2c_set_bus_speed(speed); 458 } 459 460 /* i2c write version without the register address */ 461 int i2c_write_data(uchar chip, uchar *buffer, int len) 462 { 463 int rc; 464 465 debug("i2c_write_data: chip=0x%x, len=0x%x\n", chip, len); 466 debug("write_data: "); 467 /* use rc for counter */ 468 for (rc = 0; rc < len; ++rc) 469 debug(" 0x%02x", buffer[rc]); 470 debug("\n"); 471 472 /* Shift 7-bit address over for lower-level i2c functions */ 473 rc = tegra_i2c_write_data(chip << 1, buffer, len); 474 if (rc) 475 debug("i2c_write_data(): rc=%d\n", rc); 476 477 return rc; 478 } 479 480 /* i2c read version without the register address */ 481 int i2c_read_data(uchar chip, uchar *buffer, int len) 482 { 483 int rc; 484 485 debug("inside i2c_read_data():\n"); 486 /* Shift 7-bit address over for lower-level i2c functions */ 487 rc = tegra_i2c_read_data(chip << 1, buffer, len); 488 if (rc) { 489 debug("i2c_read_data(): rc=%d\n", rc); 490 return rc; 491 } 492 493 debug("i2c_read_data: "); 494 /* reuse rc for counter*/ 495 for (rc = 0; rc < len; ++rc) 496 debug(" 0x%02x", buffer[rc]); 497 debug("\n"); 498 499 return 0; 500 } 501 502 /* Probe to see if a chip is present. */ 503 int i2c_probe(uchar chip) 504 { 505 int rc; 506 uchar reg; 507 508 debug("i2c_probe: addr=0x%x\n", chip); 509 reg = 0; 510 rc = i2c_write_data(chip, ®, 1); 511 if (rc) { 512 debug("Error probing 0x%x.\n", chip); 513 return 1; 514 } 515 return 0; 516 } 517 518 static int i2c_addr_ok(const uint addr, const int alen) 519 { 520 /* We support 7 or 10 bit addresses, so one or two bytes each */ 521 return alen == 1 || alen == 2; 522 } 523 524 /* Read bytes */ 525 int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) 526 { 527 uint offset; 528 int i; 529 530 debug("i2c_read: chip=0x%x, addr=0x%x, len=0x%x\n", 531 chip, addr, len); 532 if (!i2c_addr_ok(addr, alen)) { 533 debug("i2c_read: Bad address %x.%d.\n", addr, alen); 534 return 1; 535 } 536 for (offset = 0; offset < len; offset++) { 537 if (alen) { 538 uchar data[alen]; 539 for (i = 0; i < alen; i++) { 540 data[alen - i - 1] = 541 (addr + offset) >> (8 * i); 542 } 543 if (i2c_write_data(chip, data, alen)) { 544 debug("i2c_read: error sending (0x%x)\n", 545 addr); 546 return 1; 547 } 548 } 549 if (i2c_read_data(chip, buffer + offset, 1)) { 550 debug("i2c_read: error reading (0x%x)\n", addr); 551 return 1; 552 } 553 } 554 555 return 0; 556 } 557 558 /* Write bytes */ 559 int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) 560 { 561 uint offset; 562 int i; 563 564 debug("i2c_write: chip=0x%x, addr=0x%x, len=0x%x\n", 565 chip, addr, len); 566 if (!i2c_addr_ok(addr, alen)) { 567 debug("i2c_write: Bad address %x.%d.\n", addr, alen); 568 return 1; 569 } 570 for (offset = 0; offset < len; offset++) { 571 uchar data[alen + 1]; 572 for (i = 0; i < alen; i++) 573 data[alen - i - 1] = (addr + offset) >> (8 * i); 574 data[alen] = buffer[offset]; 575 if (i2c_write_data(chip, data, alen + 1)) { 576 debug("i2c_write: error sending (0x%x)\n", addr); 577 return 1; 578 } 579 } 580 581 return 0; 582 } 583 584 #if defined(CONFIG_I2C_MULTI_BUS) 585 /* 586 * Functions for multiple I2C bus handling 587 */ 588 unsigned int i2c_get_bus_num(void) 589 { 590 return i2c_bus_num; 591 } 592 593 int i2c_set_bus_num(unsigned int bus) 594 { 595 if (bus >= TEGRA_I2C_NUM_CONTROLLERS || !i2c_controllers[bus].inited) 596 return -1; 597 i2c_bus_num = bus; 598 599 return 0; 600 } 601 #endif 602 603 int tegra_i2c_get_dvc_bus_num(void) 604 { 605 int i; 606 607 for (i = 0; i < CONFIG_SYS_MAX_I2C_BUS; i++) { 608 struct i2c_bus *bus = &i2c_controllers[i]; 609 610 if (bus->inited && bus->is_dvc) 611 return i; 612 } 613 614 return -1; 615 } 616