1 /* 2 * Copyright (c) 2012 The Chromium OS Authors. All rights reserved. 3 * Copyright (c) 2010-2011 NVIDIA Corporation 4 * NVIDIA Corporation <www.nvidia.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <dm.h> 11 #include <errno.h> 12 #include <fdtdec.h> 13 #include <i2c.h> 14 #include <asm/io.h> 15 #ifdef CONFIG_TEGRA186 16 #include <clk.h> 17 #include <reset.h> 18 #else 19 #include <asm/arch/clock.h> 20 #include <asm/arch/funcmux.h> 21 #include <asm/arch/pinmux.h> 22 #include <asm/arch-tegra/clk_rst.h> 23 #endif 24 #include <asm/arch/gpio.h> 25 #include <asm/arch-tegra/tegra_i2c.h> 26 27 /* 28 * FIXME: TODO: This driver contains a number of ifdef CONFIG_TEGRA186 that 29 * should not be present. These are needed because newer Tegra SoCs support 30 * only the standard clock/reset APIs, whereas older Tegra SoCs support only 31 * a custom Tegra-specific API. ASAP the older Tegra SoCs' code should be 32 * fixed to implement the standard APIs, and all drivers converted to solely 33 * use the new standard APIs, with no ifdefs. 34 */ 35 36 DECLARE_GLOBAL_DATA_PTR; 37 38 enum i2c_type { 39 TYPE_114, 40 TYPE_STD, 41 TYPE_DVC, 42 }; 43 44 /* Information about i2c controller */ 45 struct i2c_bus { 46 int id; 47 #ifdef CONFIG_TEGRA186 48 struct reset_ctl reset_ctl; 49 struct clk clk; 50 #else 51 enum periph_id periph_id; 52 #endif 53 int speed; 54 int pinmux_config; 55 struct i2c_control *control; 56 struct i2c_ctlr *regs; 57 enum i2c_type type; 58 int inited; /* bus is inited */ 59 }; 60 61 static void set_packet_mode(struct i2c_bus *i2c_bus) 62 { 63 u32 config; 64 65 config = I2C_CNFG_NEW_MASTER_FSM_MASK | I2C_CNFG_PACKET_MODE_MASK; 66 67 if (i2c_bus->type == TYPE_DVC) { 68 struct dvc_ctlr *dvc = (struct dvc_ctlr *)i2c_bus->regs; 69 70 writel(config, &dvc->cnfg); 71 } else { 72 writel(config, &i2c_bus->regs->cnfg); 73 /* 74 * program I2C_SL_CNFG.NEWSL to ENABLE. This fixes probe 75 * issues, i.e., some slaves may be wrongly detected. 76 */ 77 setbits_le32(&i2c_bus->regs->sl_cnfg, I2C_SL_CNFG_NEWSL_MASK); 78 } 79 } 80 81 static void i2c_reset_controller(struct i2c_bus *i2c_bus) 82 { 83 /* Reset I2C controller. */ 84 #ifdef CONFIG_TEGRA186 85 reset_assert(&i2c_bus->reset_ctl); 86 udelay(1); 87 reset_deassert(&i2c_bus->reset_ctl); 88 udelay(1); 89 #else 90 reset_periph(i2c_bus->periph_id, 1); 91 #endif 92 93 /* re-program config register to packet mode */ 94 set_packet_mode(i2c_bus); 95 } 96 97 #ifdef CONFIG_TEGRA186 98 static int i2c_init_clock(struct i2c_bus *i2c_bus, unsigned rate) 99 { 100 int ret; 101 102 ret = reset_assert(&i2c_bus->reset_ctl); 103 if (ret) 104 return ret; 105 ret = clk_enable(&i2c_bus->clk); 106 if (ret) 107 return ret; 108 ret = clk_set_rate(&i2c_bus->clk, rate); 109 if (IS_ERR_VALUE(ret)) 110 return ret; 111 ret = reset_deassert(&i2c_bus->reset_ctl); 112 if (ret) 113 return ret; 114 115 return 0; 116 } 117 #endif 118 119 static void i2c_init_controller(struct i2c_bus *i2c_bus) 120 { 121 if (!i2c_bus->speed) 122 return; 123 debug("%s: speed=%d\n", __func__, i2c_bus->speed); 124 /* 125 * Use PLLP - DP-04508-001_v06 datasheet indicates a divisor of 8 126 * here, in section 23.3.1, but in fact we seem to need a factor of 127 * 16 to get the right frequency. 128 */ 129 #ifdef CONFIG_TEGRA186 130 i2c_init_clock(i2c_bus, i2c_bus->speed * 2 * 8); 131 #else 132 clock_start_periph_pll(i2c_bus->periph_id, CLOCK_ID_PERIPH, 133 i2c_bus->speed * 2 * 8); 134 #endif 135 136 if (i2c_bus->type == TYPE_114) { 137 /* 138 * T114 I2C went to a single clock source for standard/fast and 139 * HS clock speeds. The new clock rate setting calculation is: 140 * SCL = CLK_SOURCE.I2C / 141 * (CLK_MULT_STD_FAST_MODE * (I2C_CLK_DIV_STD_FAST_MODE+1) * 142 * I2C FREQUENCY DIVISOR) as per the T114 TRM (sec 30.3.1). 143 * 144 * NOTE: We do this here, after the initial clock/pll start, 145 * because if we read the clk_div reg before the controller 146 * is running, we hang, and we need it for the new calc. 147 */ 148 int clk_div_stdfst_mode = readl(&i2c_bus->regs->clk_div) >> 16; 149 unsigned rate = CLK_MULT_STD_FAST_MODE * 150 (clk_div_stdfst_mode + 1) * i2c_bus->speed * 2; 151 debug("%s: CLK_DIV_STD_FAST_MODE setting = %d\n", __func__, 152 clk_div_stdfst_mode); 153 154 #ifdef CONFIG_TEGRA186 155 i2c_init_clock(i2c_bus, rate); 156 #else 157 clock_start_periph_pll(i2c_bus->periph_id, CLOCK_ID_PERIPH, 158 rate); 159 #endif 160 } 161 162 /* Reset I2C controller. */ 163 i2c_reset_controller(i2c_bus); 164 165 /* Configure I2C controller. */ 166 if (i2c_bus->type == TYPE_DVC) { /* only for DVC I2C */ 167 struct dvc_ctlr *dvc = (struct dvc_ctlr *)i2c_bus->regs; 168 169 setbits_le32(&dvc->ctrl3, DVC_CTRL_REG3_I2C_HW_SW_PROG_MASK); 170 } 171 172 #ifndef CONFIG_TEGRA186 173 funcmux_select(i2c_bus->periph_id, i2c_bus->pinmux_config); 174 #endif 175 } 176 177 static void send_packet_headers( 178 struct i2c_bus *i2c_bus, 179 struct i2c_trans_info *trans, 180 u32 packet_id, 181 bool end_with_repeated_start) 182 { 183 u32 data; 184 185 /* prepare header1: Header size = 0 Protocol = I2C, pktType = 0 */ 186 data = PROTOCOL_TYPE_I2C << PKT_HDR1_PROTOCOL_SHIFT; 187 data |= packet_id << PKT_HDR1_PKT_ID_SHIFT; 188 data |= i2c_bus->id << PKT_HDR1_CTLR_ID_SHIFT; 189 writel(data, &i2c_bus->control->tx_fifo); 190 debug("pkt header 1 sent (0x%x)\n", data); 191 192 /* prepare header2 */ 193 data = (trans->num_bytes - 1) << PKT_HDR2_PAYLOAD_SIZE_SHIFT; 194 writel(data, &i2c_bus->control->tx_fifo); 195 debug("pkt header 2 sent (0x%x)\n", data); 196 197 /* prepare IO specific header: configure the slave address */ 198 data = trans->address << PKT_HDR3_SLAVE_ADDR_SHIFT; 199 200 /* Enable Read if it is not a write transaction */ 201 if (!(trans->flags & I2C_IS_WRITE)) 202 data |= PKT_HDR3_READ_MODE_MASK; 203 if (end_with_repeated_start) 204 data |= PKT_HDR3_REPEAT_START_MASK; 205 206 /* Write I2C specific header */ 207 writel(data, &i2c_bus->control->tx_fifo); 208 debug("pkt header 3 sent (0x%x)\n", data); 209 } 210 211 static int wait_for_tx_fifo_empty(struct i2c_control *control) 212 { 213 u32 count; 214 int timeout_us = I2C_TIMEOUT_USEC; 215 216 while (timeout_us >= 0) { 217 count = (readl(&control->fifo_status) & TX_FIFO_EMPTY_CNT_MASK) 218 >> TX_FIFO_EMPTY_CNT_SHIFT; 219 if (count == I2C_FIFO_DEPTH) 220 return 1; 221 udelay(10); 222 timeout_us -= 10; 223 } 224 225 return 0; 226 } 227 228 static int wait_for_rx_fifo_notempty(struct i2c_control *control) 229 { 230 u32 count; 231 int timeout_us = I2C_TIMEOUT_USEC; 232 233 while (timeout_us >= 0) { 234 count = (readl(&control->fifo_status) & TX_FIFO_FULL_CNT_MASK) 235 >> TX_FIFO_FULL_CNT_SHIFT; 236 if (count) 237 return 1; 238 udelay(10); 239 timeout_us -= 10; 240 } 241 242 return 0; 243 } 244 245 static int wait_for_transfer_complete(struct i2c_control *control) 246 { 247 int int_status; 248 int timeout_us = I2C_TIMEOUT_USEC; 249 250 while (timeout_us >= 0) { 251 int_status = readl(&control->int_status); 252 if (int_status & I2C_INT_NO_ACK_MASK) 253 return -int_status; 254 if (int_status & I2C_INT_ARBITRATION_LOST_MASK) 255 return -int_status; 256 if (int_status & I2C_INT_XFER_COMPLETE_MASK) 257 return 0; 258 259 udelay(10); 260 timeout_us -= 10; 261 } 262 263 return -1; 264 } 265 266 static int send_recv_packets(struct i2c_bus *i2c_bus, 267 struct i2c_trans_info *trans) 268 { 269 struct i2c_control *control = i2c_bus->control; 270 u32 int_status; 271 u32 words; 272 u8 *dptr; 273 u32 local; 274 uchar last_bytes; 275 int error = 0; 276 int is_write = trans->flags & I2C_IS_WRITE; 277 278 /* clear status from previous transaction, XFER_COMPLETE, NOACK, etc. */ 279 int_status = readl(&control->int_status); 280 writel(int_status, &control->int_status); 281 282 send_packet_headers(i2c_bus, trans, 1, 283 trans->flags & I2C_USE_REPEATED_START); 284 285 words = DIV_ROUND_UP(trans->num_bytes, 4); 286 last_bytes = trans->num_bytes & 3; 287 dptr = trans->buf; 288 289 while (words) { 290 u32 *wptr = (u32 *)dptr; 291 292 if (is_write) { 293 /* deal with word alignment */ 294 if ((words == 1) && last_bytes) { 295 local = 0; 296 memcpy(&local, dptr, last_bytes); 297 } else if ((unsigned long)dptr & 3) { 298 memcpy(&local, dptr, sizeof(u32)); 299 } else { 300 local = *wptr; 301 } 302 writel(local, &control->tx_fifo); 303 debug("pkt data sent (0x%x)\n", local); 304 if (!wait_for_tx_fifo_empty(control)) { 305 error = -1; 306 goto exit; 307 } 308 } else { 309 if (!wait_for_rx_fifo_notempty(control)) { 310 error = -1; 311 goto exit; 312 } 313 /* 314 * for the last word, we read into our local buffer, 315 * in case that caller did not provide enough buffer. 316 */ 317 local = readl(&control->rx_fifo); 318 if ((words == 1) && last_bytes) 319 memcpy(dptr, (char *)&local, last_bytes); 320 else if ((unsigned long)dptr & 3) 321 memcpy(dptr, &local, sizeof(u32)); 322 else 323 *wptr = local; 324 debug("pkt data received (0x%x)\n", local); 325 } 326 words--; 327 dptr += sizeof(u32); 328 } 329 330 if (wait_for_transfer_complete(control)) { 331 error = -1; 332 goto exit; 333 } 334 return 0; 335 exit: 336 /* error, reset the controller. */ 337 i2c_reset_controller(i2c_bus); 338 339 return error; 340 } 341 342 static int tegra_i2c_write_data(struct i2c_bus *i2c_bus, u32 addr, u8 *data, 343 u32 len, bool end_with_repeated_start) 344 { 345 int error; 346 struct i2c_trans_info trans_info; 347 348 trans_info.address = addr; 349 trans_info.buf = data; 350 trans_info.flags = I2C_IS_WRITE; 351 if (end_with_repeated_start) 352 trans_info.flags |= I2C_USE_REPEATED_START; 353 trans_info.num_bytes = len; 354 trans_info.is_10bit_address = 0; 355 356 error = send_recv_packets(i2c_bus, &trans_info); 357 if (error) 358 debug("tegra_i2c_write_data: Error (%d) !!!\n", error); 359 360 return error; 361 } 362 363 static int tegra_i2c_read_data(struct i2c_bus *i2c_bus, u32 addr, u8 *data, 364 u32 len) 365 { 366 int error; 367 struct i2c_trans_info trans_info; 368 369 trans_info.address = addr | 1; 370 trans_info.buf = data; 371 trans_info.flags = 0; 372 trans_info.num_bytes = len; 373 trans_info.is_10bit_address = 0; 374 375 error = send_recv_packets(i2c_bus, &trans_info); 376 if (error) 377 debug("tegra_i2c_read_data: Error (%d) !!!\n", error); 378 379 return error; 380 } 381 382 static int tegra_i2c_set_bus_speed(struct udevice *dev, unsigned int speed) 383 { 384 struct i2c_bus *i2c_bus = dev_get_priv(dev); 385 386 i2c_bus->speed = speed; 387 i2c_init_controller(i2c_bus); 388 389 return 0; 390 } 391 392 static int tegra_i2c_probe(struct udevice *dev) 393 { 394 struct i2c_bus *i2c_bus = dev_get_priv(dev); 395 #ifdef CONFIG_TEGRA186 396 int ret; 397 #else 398 const void *blob = gd->fdt_blob; 399 int node = dev->of_offset; 400 #endif 401 bool is_dvc; 402 403 i2c_bus->id = dev->seq; 404 i2c_bus->type = dev_get_driver_data(dev); 405 i2c_bus->regs = (struct i2c_ctlr *)dev_get_addr(dev); 406 407 /* 408 * We don't have a binding for pinmux yet. Leave it out for now. So 409 * far no one needs anything other than the default. 410 */ 411 #ifdef CONFIG_TEGRA186 412 ret = reset_get_by_name(dev, "i2c", &i2c_bus->reset_ctl); 413 if (ret) { 414 error("reset_get_by_name() failed: %d\n", ret); 415 return ret; 416 } 417 ret = clk_get_by_name(dev, "div-clk", &i2c_bus->clk); 418 if (ret) { 419 error("clk_get_by_name() failed: %d\n", ret); 420 return ret; 421 } 422 #else 423 i2c_bus->pinmux_config = FUNCMUX_DEFAULT; 424 i2c_bus->periph_id = clock_decode_periph_id(blob, node); 425 426 /* 427 * We can't specify the pinmux config in the fdt, so I2C2 will not 428 * work on Seaboard. It normally has no devices on it anyway. 429 * You could add in this little hack if you need to use it. 430 * The correct solution is a pinmux binding in the fdt. 431 * 432 * if (i2c_bus->periph_id == PERIPH_ID_I2C2) 433 * i2c_bus->pinmux_config = FUNCMUX_I2C2_PTA; 434 */ 435 if (i2c_bus->periph_id == -1) 436 return -EINVAL; 437 #endif 438 439 is_dvc = dev_get_driver_data(dev) == TYPE_DVC; 440 if (is_dvc) { 441 i2c_bus->control = 442 &((struct dvc_ctlr *)i2c_bus->regs)->control; 443 } else { 444 i2c_bus->control = &i2c_bus->regs->control; 445 } 446 i2c_init_controller(i2c_bus); 447 debug("%s: controller bus %d at %p, periph_id %d, speed %d: ", 448 is_dvc ? "dvc" : "i2c", dev->seq, i2c_bus->regs, 449 #ifndef CONFIG_TEGRA186 450 i2c_bus->periph_id, 451 #else 452 -1, 453 #endif 454 i2c_bus->speed); 455 456 return 0; 457 } 458 459 /* i2c write version without the register address */ 460 static int i2c_write_data(struct i2c_bus *i2c_bus, uchar chip, uchar *buffer, 461 int len, bool end_with_repeated_start) 462 { 463 int rc; 464 465 debug("i2c_write_data: chip=0x%x, len=0x%x\n", chip, len); 466 debug("write_data: "); 467 /* use rc for counter */ 468 for (rc = 0; rc < len; ++rc) 469 debug(" 0x%02x", buffer[rc]); 470 debug("\n"); 471 472 /* Shift 7-bit address over for lower-level i2c functions */ 473 rc = tegra_i2c_write_data(i2c_bus, chip << 1, buffer, len, 474 end_with_repeated_start); 475 if (rc) 476 debug("i2c_write_data(): rc=%d\n", rc); 477 478 return rc; 479 } 480 481 /* i2c read version without the register address */ 482 static int i2c_read_data(struct i2c_bus *i2c_bus, uchar chip, uchar *buffer, 483 int len) 484 { 485 int rc; 486 487 debug("inside i2c_read_data():\n"); 488 /* Shift 7-bit address over for lower-level i2c functions */ 489 rc = tegra_i2c_read_data(i2c_bus, chip << 1, buffer, len); 490 if (rc) { 491 debug("i2c_read_data(): rc=%d\n", rc); 492 return rc; 493 } 494 495 debug("i2c_read_data: "); 496 /* reuse rc for counter*/ 497 for (rc = 0; rc < len; ++rc) 498 debug(" 0x%02x", buffer[rc]); 499 debug("\n"); 500 501 return 0; 502 } 503 504 /* Probe to see if a chip is present. */ 505 static int tegra_i2c_probe_chip(struct udevice *bus, uint chip_addr, 506 uint chip_flags) 507 { 508 struct i2c_bus *i2c_bus = dev_get_priv(bus); 509 int rc; 510 u8 reg; 511 512 /* Shift 7-bit address over for lower-level i2c functions */ 513 rc = tegra_i2c_write_data(i2c_bus, chip_addr << 1, ®, sizeof(reg), 514 false); 515 516 return rc; 517 } 518 519 static int tegra_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, 520 int nmsgs) 521 { 522 struct i2c_bus *i2c_bus = dev_get_priv(bus); 523 int ret; 524 525 debug("i2c_xfer: %d messages\n", nmsgs); 526 for (; nmsgs > 0; nmsgs--, msg++) { 527 bool next_is_read = nmsgs > 1 && (msg[1].flags & I2C_M_RD); 528 529 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len); 530 if (msg->flags & I2C_M_RD) { 531 ret = i2c_read_data(i2c_bus, msg->addr, msg->buf, 532 msg->len); 533 } else { 534 ret = i2c_write_data(i2c_bus, msg->addr, msg->buf, 535 msg->len, next_is_read); 536 } 537 if (ret) { 538 debug("i2c_write: error sending\n"); 539 return -EREMOTEIO; 540 } 541 } 542 543 return 0; 544 } 545 546 int tegra_i2c_get_dvc_bus(struct udevice **busp) 547 { 548 struct udevice *bus; 549 550 for (uclass_first_device(UCLASS_I2C, &bus); 551 bus; 552 uclass_next_device(&bus)) { 553 if (dev_get_driver_data(bus) == TYPE_DVC) { 554 *busp = bus; 555 return 0; 556 } 557 } 558 559 return -ENODEV; 560 } 561 562 static const struct dm_i2c_ops tegra_i2c_ops = { 563 .xfer = tegra_i2c_xfer, 564 .probe_chip = tegra_i2c_probe_chip, 565 .set_bus_speed = tegra_i2c_set_bus_speed, 566 }; 567 568 static const struct udevice_id tegra_i2c_ids[] = { 569 { .compatible = "nvidia,tegra114-i2c", .data = TYPE_114 }, 570 { .compatible = "nvidia,tegra20-i2c", .data = TYPE_STD }, 571 { .compatible = "nvidia,tegra20-i2c-dvc", .data = TYPE_DVC }, 572 { } 573 }; 574 575 U_BOOT_DRIVER(i2c_tegra) = { 576 .name = "i2c_tegra", 577 .id = UCLASS_I2C, 578 .of_match = tegra_i2c_ids, 579 .probe = tegra_i2c_probe, 580 .priv_auto_alloc_size = sizeof(struct i2c_bus), 581 .ops = &tegra_i2c_ops, 582 }; 583