1 /* 2 * Copyright (c) 2012 The Chromium OS Authors. All rights reserved. 3 * Copyright (c) 2010-2011 NVIDIA Corporation 4 * NVIDIA Corporation <www.nvidia.com> 5 * 6 * SPDX-License-Identifier: GPL-2.0+ 7 */ 8 9 #include <common.h> 10 #include <dm.h> 11 #include <errno.h> 12 #include <fdtdec.h> 13 #include <i2c.h> 14 #include <asm/io.h> 15 #include <asm/arch/clock.h> 16 #include <asm/arch/funcmux.h> 17 #include <asm/arch/gpio.h> 18 #include <asm/arch/pinmux.h> 19 #include <asm/arch-tegra/clk_rst.h> 20 #include <asm/arch-tegra/tegra_i2c.h> 21 22 DECLARE_GLOBAL_DATA_PTR; 23 24 enum i2c_type { 25 TYPE_114, 26 TYPE_STD, 27 TYPE_DVC, 28 }; 29 30 /* Information about i2c controller */ 31 struct i2c_bus { 32 int id; 33 enum periph_id periph_id; 34 int speed; 35 int pinmux_config; 36 struct i2c_control *control; 37 struct i2c_ctlr *regs; 38 enum i2c_type type; 39 int inited; /* bus is inited */ 40 }; 41 42 static void set_packet_mode(struct i2c_bus *i2c_bus) 43 { 44 u32 config; 45 46 config = I2C_CNFG_NEW_MASTER_FSM_MASK | I2C_CNFG_PACKET_MODE_MASK; 47 48 if (i2c_bus->type == TYPE_DVC) { 49 struct dvc_ctlr *dvc = (struct dvc_ctlr *)i2c_bus->regs; 50 51 writel(config, &dvc->cnfg); 52 } else { 53 writel(config, &i2c_bus->regs->cnfg); 54 /* 55 * program I2C_SL_CNFG.NEWSL to ENABLE. This fixes probe 56 * issues, i.e., some slaves may be wrongly detected. 57 */ 58 setbits_le32(&i2c_bus->regs->sl_cnfg, I2C_SL_CNFG_NEWSL_MASK); 59 } 60 } 61 62 static void i2c_reset_controller(struct i2c_bus *i2c_bus) 63 { 64 /* Reset I2C controller. */ 65 reset_periph(i2c_bus->periph_id, 1); 66 67 /* re-program config register to packet mode */ 68 set_packet_mode(i2c_bus); 69 } 70 71 static void i2c_init_controller(struct i2c_bus *i2c_bus) 72 { 73 if (!i2c_bus->speed) 74 return; 75 debug("%s: speed=%d\n", __func__, i2c_bus->speed); 76 /* 77 * Use PLLP - DP-04508-001_v06 datasheet indicates a divisor of 8 78 * here, in section 23.3.1, but in fact we seem to need a factor of 79 * 16 to get the right frequency. 80 */ 81 clock_start_periph_pll(i2c_bus->periph_id, CLOCK_ID_PERIPH, 82 i2c_bus->speed * 2 * 8); 83 84 if (i2c_bus->type == TYPE_114) { 85 /* 86 * T114 I2C went to a single clock source for standard/fast and 87 * HS clock speeds. The new clock rate setting calculation is: 88 * SCL = CLK_SOURCE.I2C / 89 * (CLK_MULT_STD_FAST_MODE * (I2C_CLK_DIV_STD_FAST_MODE+1) * 90 * I2C FREQUENCY DIVISOR) as per the T114 TRM (sec 30.3.1). 91 * 92 * NOTE: We do this here, after the initial clock/pll start, 93 * because if we read the clk_div reg before the controller 94 * is running, we hang, and we need it for the new calc. 95 */ 96 int clk_div_stdfst_mode = readl(&i2c_bus->regs->clk_div) >> 16; 97 debug("%s: CLK_DIV_STD_FAST_MODE setting = %d\n", __func__, 98 clk_div_stdfst_mode); 99 100 clock_start_periph_pll(i2c_bus->periph_id, CLOCK_ID_PERIPH, 101 CLK_MULT_STD_FAST_MODE * (clk_div_stdfst_mode + 1) * 102 i2c_bus->speed * 2); 103 } 104 105 /* Reset I2C controller. */ 106 i2c_reset_controller(i2c_bus); 107 108 /* Configure I2C controller. */ 109 if (i2c_bus->type == TYPE_DVC) { /* only for DVC I2C */ 110 struct dvc_ctlr *dvc = (struct dvc_ctlr *)i2c_bus->regs; 111 112 setbits_le32(&dvc->ctrl3, DVC_CTRL_REG3_I2C_HW_SW_PROG_MASK); 113 } 114 115 funcmux_select(i2c_bus->periph_id, i2c_bus->pinmux_config); 116 } 117 118 static void send_packet_headers( 119 struct i2c_bus *i2c_bus, 120 struct i2c_trans_info *trans, 121 u32 packet_id, 122 bool end_with_repeated_start) 123 { 124 u32 data; 125 126 /* prepare header1: Header size = 0 Protocol = I2C, pktType = 0 */ 127 data = PROTOCOL_TYPE_I2C << PKT_HDR1_PROTOCOL_SHIFT; 128 data |= packet_id << PKT_HDR1_PKT_ID_SHIFT; 129 data |= i2c_bus->id << PKT_HDR1_CTLR_ID_SHIFT; 130 writel(data, &i2c_bus->control->tx_fifo); 131 debug("pkt header 1 sent (0x%x)\n", data); 132 133 /* prepare header2 */ 134 data = (trans->num_bytes - 1) << PKT_HDR2_PAYLOAD_SIZE_SHIFT; 135 writel(data, &i2c_bus->control->tx_fifo); 136 debug("pkt header 2 sent (0x%x)\n", data); 137 138 /* prepare IO specific header: configure the slave address */ 139 data = trans->address << PKT_HDR3_SLAVE_ADDR_SHIFT; 140 141 /* Enable Read if it is not a write transaction */ 142 if (!(trans->flags & I2C_IS_WRITE)) 143 data |= PKT_HDR3_READ_MODE_MASK; 144 if (end_with_repeated_start) 145 data |= PKT_HDR3_REPEAT_START_MASK; 146 147 /* Write I2C specific header */ 148 writel(data, &i2c_bus->control->tx_fifo); 149 debug("pkt header 3 sent (0x%x)\n", data); 150 } 151 152 static int wait_for_tx_fifo_empty(struct i2c_control *control) 153 { 154 u32 count; 155 int timeout_us = I2C_TIMEOUT_USEC; 156 157 while (timeout_us >= 0) { 158 count = (readl(&control->fifo_status) & TX_FIFO_EMPTY_CNT_MASK) 159 >> TX_FIFO_EMPTY_CNT_SHIFT; 160 if (count == I2C_FIFO_DEPTH) 161 return 1; 162 udelay(10); 163 timeout_us -= 10; 164 } 165 166 return 0; 167 } 168 169 static int wait_for_rx_fifo_notempty(struct i2c_control *control) 170 { 171 u32 count; 172 int timeout_us = I2C_TIMEOUT_USEC; 173 174 while (timeout_us >= 0) { 175 count = (readl(&control->fifo_status) & TX_FIFO_FULL_CNT_MASK) 176 >> TX_FIFO_FULL_CNT_SHIFT; 177 if (count) 178 return 1; 179 udelay(10); 180 timeout_us -= 10; 181 } 182 183 return 0; 184 } 185 186 static int wait_for_transfer_complete(struct i2c_control *control) 187 { 188 int int_status; 189 int timeout_us = I2C_TIMEOUT_USEC; 190 191 while (timeout_us >= 0) { 192 int_status = readl(&control->int_status); 193 if (int_status & I2C_INT_NO_ACK_MASK) 194 return -int_status; 195 if (int_status & I2C_INT_ARBITRATION_LOST_MASK) 196 return -int_status; 197 if (int_status & I2C_INT_XFER_COMPLETE_MASK) 198 return 0; 199 200 udelay(10); 201 timeout_us -= 10; 202 } 203 204 return -1; 205 } 206 207 static int send_recv_packets(struct i2c_bus *i2c_bus, 208 struct i2c_trans_info *trans) 209 { 210 struct i2c_control *control = i2c_bus->control; 211 u32 int_status; 212 u32 words; 213 u8 *dptr; 214 u32 local; 215 uchar last_bytes; 216 int error = 0; 217 int is_write = trans->flags & I2C_IS_WRITE; 218 219 /* clear status from previous transaction, XFER_COMPLETE, NOACK, etc. */ 220 int_status = readl(&control->int_status); 221 writel(int_status, &control->int_status); 222 223 send_packet_headers(i2c_bus, trans, 1, 224 trans->flags & I2C_USE_REPEATED_START); 225 226 words = DIV_ROUND_UP(trans->num_bytes, 4); 227 last_bytes = trans->num_bytes & 3; 228 dptr = trans->buf; 229 230 while (words) { 231 u32 *wptr = (u32 *)dptr; 232 233 if (is_write) { 234 /* deal with word alignment */ 235 if ((words == 1) && last_bytes) { 236 local = 0; 237 memcpy(&local, dptr, last_bytes); 238 } else if ((unsigned long)dptr & 3) { 239 memcpy(&local, dptr, sizeof(u32)); 240 } else { 241 local = *wptr; 242 } 243 writel(local, &control->tx_fifo); 244 debug("pkt data sent (0x%x)\n", local); 245 if (!wait_for_tx_fifo_empty(control)) { 246 error = -1; 247 goto exit; 248 } 249 } else { 250 if (!wait_for_rx_fifo_notempty(control)) { 251 error = -1; 252 goto exit; 253 } 254 /* 255 * for the last word, we read into our local buffer, 256 * in case that caller did not provide enough buffer. 257 */ 258 local = readl(&control->rx_fifo); 259 if ((words == 1) && last_bytes) 260 memcpy(dptr, (char *)&local, last_bytes); 261 else if ((unsigned long)dptr & 3) 262 memcpy(dptr, &local, sizeof(u32)); 263 else 264 *wptr = local; 265 debug("pkt data received (0x%x)\n", local); 266 } 267 words--; 268 dptr += sizeof(u32); 269 } 270 271 if (wait_for_transfer_complete(control)) { 272 error = -1; 273 goto exit; 274 } 275 return 0; 276 exit: 277 /* error, reset the controller. */ 278 i2c_reset_controller(i2c_bus); 279 280 return error; 281 } 282 283 static int tegra_i2c_write_data(struct i2c_bus *i2c_bus, u32 addr, u8 *data, 284 u32 len, bool end_with_repeated_start) 285 { 286 int error; 287 struct i2c_trans_info trans_info; 288 289 trans_info.address = addr; 290 trans_info.buf = data; 291 trans_info.flags = I2C_IS_WRITE; 292 if (end_with_repeated_start) 293 trans_info.flags |= I2C_USE_REPEATED_START; 294 trans_info.num_bytes = len; 295 trans_info.is_10bit_address = 0; 296 297 error = send_recv_packets(i2c_bus, &trans_info); 298 if (error) 299 debug("tegra_i2c_write_data: Error (%d) !!!\n", error); 300 301 return error; 302 } 303 304 static int tegra_i2c_read_data(struct i2c_bus *i2c_bus, u32 addr, u8 *data, 305 u32 len) 306 { 307 int error; 308 struct i2c_trans_info trans_info; 309 310 trans_info.address = addr | 1; 311 trans_info.buf = data; 312 trans_info.flags = 0; 313 trans_info.num_bytes = len; 314 trans_info.is_10bit_address = 0; 315 316 error = send_recv_packets(i2c_bus, &trans_info); 317 if (error) 318 debug("tegra_i2c_read_data: Error (%d) !!!\n", error); 319 320 return error; 321 } 322 323 static int tegra_i2c_set_bus_speed(struct udevice *dev, unsigned int speed) 324 { 325 struct i2c_bus *i2c_bus = dev_get_priv(dev); 326 327 i2c_bus->speed = speed; 328 i2c_init_controller(i2c_bus); 329 330 return 0; 331 } 332 333 static int tegra_i2c_probe(struct udevice *dev) 334 { 335 struct i2c_bus *i2c_bus = dev_get_priv(dev); 336 const void *blob = gd->fdt_blob; 337 int node = dev->of_offset; 338 bool is_dvc; 339 340 i2c_bus->id = dev->seq; 341 i2c_bus->type = dev_get_driver_data(dev); 342 i2c_bus->regs = (struct i2c_ctlr *)dev_get_addr(dev); 343 344 /* 345 * We don't have a binding for pinmux yet. Leave it out for now. So 346 * far no one needs anything other than the default. 347 */ 348 i2c_bus->pinmux_config = FUNCMUX_DEFAULT; 349 i2c_bus->periph_id = clock_decode_periph_id(blob, node); 350 351 /* 352 * We can't specify the pinmux config in the fdt, so I2C2 will not 353 * work on Seaboard. It normally has no devices on it anyway. 354 * You could add in this little hack if you need to use it. 355 * The correct solution is a pinmux binding in the fdt. 356 * 357 * if (i2c_bus->periph_id == PERIPH_ID_I2C2) 358 * i2c_bus->pinmux_config = FUNCMUX_I2C2_PTA; 359 */ 360 if (i2c_bus->periph_id == -1) 361 return -EINVAL; 362 363 is_dvc = dev_get_driver_data(dev) == TYPE_DVC; 364 if (is_dvc) { 365 i2c_bus->control = 366 &((struct dvc_ctlr *)i2c_bus->regs)->control; 367 } else { 368 i2c_bus->control = &i2c_bus->regs->control; 369 } 370 i2c_init_controller(i2c_bus); 371 debug("%s: controller bus %d at %p, periph_id %d, speed %d: ", 372 is_dvc ? "dvc" : "i2c", dev->seq, i2c_bus->regs, 373 i2c_bus->periph_id, i2c_bus->speed); 374 375 return 0; 376 } 377 378 /* i2c write version without the register address */ 379 static int i2c_write_data(struct i2c_bus *i2c_bus, uchar chip, uchar *buffer, 380 int len, bool end_with_repeated_start) 381 { 382 int rc; 383 384 debug("i2c_write_data: chip=0x%x, len=0x%x\n", chip, len); 385 debug("write_data: "); 386 /* use rc for counter */ 387 for (rc = 0; rc < len; ++rc) 388 debug(" 0x%02x", buffer[rc]); 389 debug("\n"); 390 391 /* Shift 7-bit address over for lower-level i2c functions */ 392 rc = tegra_i2c_write_data(i2c_bus, chip << 1, buffer, len, 393 end_with_repeated_start); 394 if (rc) 395 debug("i2c_write_data(): rc=%d\n", rc); 396 397 return rc; 398 } 399 400 /* i2c read version without the register address */ 401 static int i2c_read_data(struct i2c_bus *i2c_bus, uchar chip, uchar *buffer, 402 int len) 403 { 404 int rc; 405 406 debug("inside i2c_read_data():\n"); 407 /* Shift 7-bit address over for lower-level i2c functions */ 408 rc = tegra_i2c_read_data(i2c_bus, chip << 1, buffer, len); 409 if (rc) { 410 debug("i2c_read_data(): rc=%d\n", rc); 411 return rc; 412 } 413 414 debug("i2c_read_data: "); 415 /* reuse rc for counter*/ 416 for (rc = 0; rc < len; ++rc) 417 debug(" 0x%02x", buffer[rc]); 418 debug("\n"); 419 420 return 0; 421 } 422 423 /* Probe to see if a chip is present. */ 424 static int tegra_i2c_probe_chip(struct udevice *bus, uint chip_addr, 425 uint chip_flags) 426 { 427 struct i2c_bus *i2c_bus = dev_get_priv(bus); 428 int rc; 429 u8 reg; 430 431 /* Shift 7-bit address over for lower-level i2c functions */ 432 rc = tegra_i2c_write_data(i2c_bus, chip_addr << 1, ®, sizeof(reg), 433 false); 434 435 return rc; 436 } 437 438 static int tegra_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, 439 int nmsgs) 440 { 441 struct i2c_bus *i2c_bus = dev_get_priv(bus); 442 int ret; 443 444 debug("i2c_xfer: %d messages\n", nmsgs); 445 for (; nmsgs > 0; nmsgs--, msg++) { 446 bool next_is_read = nmsgs > 1 && (msg[1].flags & I2C_M_RD); 447 448 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len); 449 if (msg->flags & I2C_M_RD) { 450 ret = i2c_read_data(i2c_bus, msg->addr, msg->buf, 451 msg->len); 452 } else { 453 ret = i2c_write_data(i2c_bus, msg->addr, msg->buf, 454 msg->len, next_is_read); 455 } 456 if (ret) { 457 debug("i2c_write: error sending\n"); 458 return -EREMOTEIO; 459 } 460 } 461 462 return 0; 463 } 464 465 int tegra_i2c_get_dvc_bus(struct udevice **busp) 466 { 467 struct udevice *bus; 468 469 for (uclass_first_device(UCLASS_I2C, &bus); 470 bus; 471 uclass_next_device(&bus)) { 472 if (dev_get_driver_data(bus) == TYPE_DVC) { 473 *busp = bus; 474 return 0; 475 } 476 } 477 478 return -ENODEV; 479 } 480 481 static const struct dm_i2c_ops tegra_i2c_ops = { 482 .xfer = tegra_i2c_xfer, 483 .probe_chip = tegra_i2c_probe_chip, 484 .set_bus_speed = tegra_i2c_set_bus_speed, 485 }; 486 487 static const struct udevice_id tegra_i2c_ids[] = { 488 { .compatible = "nvidia,tegra114-i2c", .data = TYPE_114 }, 489 { .compatible = "nvidia,tegra20-i2c", .data = TYPE_STD }, 490 { .compatible = "nvidia,tegra20-i2c-dvc", .data = TYPE_DVC }, 491 { } 492 }; 493 494 U_BOOT_DRIVER(i2c_tegra) = { 495 .name = "i2c_tegra", 496 .id = UCLASS_I2C, 497 .of_match = tegra_i2c_ids, 498 .probe = tegra_i2c_probe, 499 .priv_auto_alloc_size = sizeof(struct i2c_bus), 500 .ops = &tegra_i2c_ops, 501 }; 502