1 /* 2 * (C) Copyright 2017 STMicroelectronics 3 * 4 * SPDX-License-Identifier: GPL-2.0+ 5 */ 6 7 #include <common.h> 8 #include <clk.h> 9 #include <dm.h> 10 #include <i2c.h> 11 #include <reset.h> 12 13 #include <dm/device.h> 14 #include <linux/io.h> 15 16 /* STM32 I2C registers */ 17 struct stm32_i2c_regs { 18 u32 cr1; /* I2C control register 1 */ 19 u32 cr2; /* I2C control register 2 */ 20 u32 oar1; /* I2C own address 1 register */ 21 u32 oar2; /* I2C own address 2 register */ 22 u32 timingr; /* I2C timing register */ 23 u32 timeoutr; /* I2C timeout register */ 24 u32 isr; /* I2C interrupt and status register */ 25 u32 icr; /* I2C interrupt clear register */ 26 u32 pecr; /* I2C packet error checking register */ 27 u32 rxdr; /* I2C receive data register */ 28 u32 txdr; /* I2C transmit data register */ 29 }; 30 31 #define STM32_I2C_CR1 0x00 32 #define STM32_I2C_CR2 0x04 33 #define STM32_I2C_TIMINGR 0x10 34 #define STM32_I2C_ISR 0x18 35 #define STM32_I2C_ICR 0x1C 36 #define STM32_I2C_RXDR 0x24 37 #define STM32_I2C_TXDR 0x28 38 39 /* STM32 I2C control 1 */ 40 #define STM32_I2C_CR1_ANFOFF BIT(12) 41 #define STM32_I2C_CR1_ERRIE BIT(7) 42 #define STM32_I2C_CR1_TCIE BIT(6) 43 #define STM32_I2C_CR1_STOPIE BIT(5) 44 #define STM32_I2C_CR1_NACKIE BIT(4) 45 #define STM32_I2C_CR1_ADDRIE BIT(3) 46 #define STM32_I2C_CR1_RXIE BIT(2) 47 #define STM32_I2C_CR1_TXIE BIT(1) 48 #define STM32_I2C_CR1_PE BIT(0) 49 50 /* STM32 I2C control 2 */ 51 #define STM32_I2C_CR2_AUTOEND BIT(25) 52 #define STM32_I2C_CR2_RELOAD BIT(24) 53 #define STM32_I2C_CR2_NBYTES_MASK GENMASK(23, 16) 54 #define STM32_I2C_CR2_NBYTES(n) ((n & 0xff) << 16) 55 #define STM32_I2C_CR2_NACK BIT(15) 56 #define STM32_I2C_CR2_STOP BIT(14) 57 #define STM32_I2C_CR2_START BIT(13) 58 #define STM32_I2C_CR2_HEAD10R BIT(12) 59 #define STM32_I2C_CR2_ADD10 BIT(11) 60 #define STM32_I2C_CR2_RD_WRN BIT(10) 61 #define STM32_I2C_CR2_SADD10_MASK GENMASK(9, 0) 62 #define STM32_I2C_CR2_SADD10(n) ((n & STM32_I2C_CR2_SADD10_MASK)) 63 #define STM32_I2C_CR2_SADD7_MASK GENMASK(7, 1) 64 #define STM32_I2C_CR2_SADD7(n) ((n & 0x7f) << 1) 65 #define STM32_I2C_CR2_RESET_MASK (STM32_I2C_CR2_HEAD10R \ 66 | STM32_I2C_CR2_NBYTES_MASK \ 67 | STM32_I2C_CR2_SADD7_MASK \ 68 | STM32_I2C_CR2_RELOAD \ 69 | STM32_I2C_CR2_RD_WRN) 70 71 /* STM32 I2C Interrupt Status */ 72 #define STM32_I2C_ISR_BUSY BIT(15) 73 #define STM32_I2C_ISR_ARLO BIT(9) 74 #define STM32_I2C_ISR_BERR BIT(8) 75 #define STM32_I2C_ISR_TCR BIT(7) 76 #define STM32_I2C_ISR_TC BIT(6) 77 #define STM32_I2C_ISR_STOPF BIT(5) 78 #define STM32_I2C_ISR_NACKF BIT(4) 79 #define STM32_I2C_ISR_ADDR BIT(3) 80 #define STM32_I2C_ISR_RXNE BIT(2) 81 #define STM32_I2C_ISR_TXIS BIT(1) 82 #define STM32_I2C_ISR_TXE BIT(0) 83 #define STM32_I2C_ISR_ERRORS (STM32_I2C_ISR_BERR \ 84 | STM32_I2C_ISR_ARLO) 85 86 /* STM32 I2C Interrupt Clear */ 87 #define STM32_I2C_ICR_ARLOCF BIT(9) 88 #define STM32_I2C_ICR_BERRCF BIT(8) 89 #define STM32_I2C_ICR_STOPCF BIT(5) 90 #define STM32_I2C_ICR_NACKCF BIT(4) 91 92 /* STM32 I2C Timing */ 93 #define STM32_I2C_TIMINGR_PRESC(n) ((n & 0xf) << 28) 94 #define STM32_I2C_TIMINGR_SCLDEL(n) ((n & 0xf) << 20) 95 #define STM32_I2C_TIMINGR_SDADEL(n) ((n & 0xf) << 16) 96 #define STM32_I2C_TIMINGR_SCLH(n) ((n & 0xff) << 8) 97 #define STM32_I2C_TIMINGR_SCLL(n) (n & 0xff) 98 99 #define STM32_I2C_MAX_LEN 0xff 100 101 #define STM32_I2C_DNF_DEFAULT 0 102 #define STM32_I2C_DNF_MAX 16 103 104 #define STM32_I2C_ANALOG_FILTER_ENABLE 1 105 #define STM32_I2C_ANALOG_FILTER_DELAY_MIN 50 /* ns */ 106 #define STM32_I2C_ANALOG_FILTER_DELAY_MAX 260 /* ns */ 107 108 #define STM32_I2C_RISE_TIME_DEFAULT 25 /* ns */ 109 #define STM32_I2C_FALL_TIME_DEFAULT 10 /* ns */ 110 111 #define STM32_PRESC_MAX BIT(4) 112 #define STM32_SCLDEL_MAX BIT(4) 113 #define STM32_SDADEL_MAX BIT(4) 114 #define STM32_SCLH_MAX BIT(8) 115 #define STM32_SCLL_MAX BIT(8) 116 117 #define STM32_NSEC_PER_SEC 1000000000L 118 119 #define STANDARD_RATE 100000 120 #define FAST_RATE 400000 121 #define FAST_PLUS_RATE 1000000 122 123 enum stm32_i2c_speed { 124 STM32_I2C_SPEED_STANDARD, /* 100 kHz */ 125 STM32_I2C_SPEED_FAST, /* 400 kHz */ 126 STM32_I2C_SPEED_FAST_PLUS, /* 1 MHz */ 127 STM32_I2C_SPEED_END, 128 }; 129 130 /** 131 * struct stm32_i2c_spec - private i2c specification timing 132 * @rate: I2C bus speed (Hz) 133 * @rate_min: 80% of I2C bus speed (Hz) 134 * @rate_max: 120% of I2C bus speed (Hz) 135 * @fall_max: Max fall time of both SDA and SCL signals (ns) 136 * @rise_max: Max rise time of both SDA and SCL signals (ns) 137 * @hddat_min: Min data hold time (ns) 138 * @vddat_max: Max data valid time (ns) 139 * @sudat_min: Min data setup time (ns) 140 * @l_min: Min low period of the SCL clock (ns) 141 * @h_min: Min high period of the SCL clock (ns) 142 */ 143 144 struct stm32_i2c_spec { 145 u32 rate; 146 u32 rate_min; 147 u32 rate_max; 148 u32 fall_max; 149 u32 rise_max; 150 u32 hddat_min; 151 u32 vddat_max; 152 u32 sudat_min; 153 u32 l_min; 154 u32 h_min; 155 }; 156 157 /** 158 * struct stm32_i2c_setup - private I2C timing setup parameters 159 * @speed: I2C speed mode (standard, Fast Plus) 160 * @speed_freq: I2C speed frequency (Hz) 161 * @clock_src: I2C clock source frequency (Hz) 162 * @rise_time: Rise time (ns) 163 * @fall_time: Fall time (ns) 164 * @dnf: Digital filter coefficient (0-16) 165 * @analog_filter: Analog filter delay (On/Off) 166 */ 167 struct stm32_i2c_setup { 168 enum stm32_i2c_speed speed; 169 u32 speed_freq; 170 u32 clock_src; 171 u32 rise_time; 172 u32 fall_time; 173 u8 dnf; 174 bool analog_filter; 175 }; 176 177 /** 178 * struct stm32_i2c_timings - private I2C output parameters 179 * @prec: Prescaler value 180 * @scldel: Data setup time 181 * @sdadel: Data hold time 182 * @sclh: SCL high period (master mode) 183 * @sclh: SCL low period (master mode) 184 */ 185 struct stm32_i2c_timings { 186 struct list_head node; 187 u8 presc; 188 u8 scldel; 189 u8 sdadel; 190 u8 sclh; 191 u8 scll; 192 }; 193 194 struct stm32_i2c_priv { 195 struct stm32_i2c_regs *regs; 196 struct clk clk; 197 struct stm32_i2c_setup *setup; 198 int speed; 199 }; 200 201 static struct stm32_i2c_spec i2c_specs[] = { 202 [STM32_I2C_SPEED_STANDARD] = { 203 .rate = STANDARD_RATE, 204 .rate_min = 8000, 205 .rate_max = 120000, 206 .fall_max = 300, 207 .rise_max = 1000, 208 .hddat_min = 0, 209 .vddat_max = 3450, 210 .sudat_min = 250, 211 .l_min = 4700, 212 .h_min = 4000, 213 }, 214 [STM32_I2C_SPEED_FAST] = { 215 .rate = FAST_RATE, 216 .rate_min = 320000, 217 .rate_max = 480000, 218 .fall_max = 300, 219 .rise_max = 300, 220 .hddat_min = 0, 221 .vddat_max = 900, 222 .sudat_min = 100, 223 .l_min = 1300, 224 .h_min = 600, 225 }, 226 [STM32_I2C_SPEED_FAST_PLUS] = { 227 .rate = FAST_PLUS_RATE, 228 .rate_min = 800000, 229 .rate_max = 1200000, 230 .fall_max = 100, 231 .rise_max = 120, 232 .hddat_min = 0, 233 .vddat_max = 450, 234 .sudat_min = 50, 235 .l_min = 500, 236 .h_min = 260, 237 }, 238 }; 239 240 static struct stm32_i2c_setup stm32f7_setup = { 241 .rise_time = STM32_I2C_RISE_TIME_DEFAULT, 242 .fall_time = STM32_I2C_FALL_TIME_DEFAULT, 243 .dnf = STM32_I2C_DNF_DEFAULT, 244 .analog_filter = STM32_I2C_ANALOG_FILTER_ENABLE, 245 }; 246 247 static int stm32_i2c_check_device_busy(struct stm32_i2c_priv *i2c_priv) 248 { 249 struct stm32_i2c_regs *regs = i2c_priv->regs; 250 u32 status = readl(®s->isr); 251 252 if (status & STM32_I2C_ISR_BUSY) 253 return -EBUSY; 254 255 return 0; 256 } 257 258 static void stm32_i2c_message_start(struct stm32_i2c_priv *i2c_priv, 259 struct i2c_msg *msg, bool stop) 260 { 261 struct stm32_i2c_regs *regs = i2c_priv->regs; 262 u32 cr2 = readl(®s->cr2); 263 264 /* Set transfer direction */ 265 cr2 &= ~STM32_I2C_CR2_RD_WRN; 266 if (msg->flags & I2C_M_RD) 267 cr2 |= STM32_I2C_CR2_RD_WRN; 268 269 /* Set slave address */ 270 cr2 &= ~(STM32_I2C_CR2_HEAD10R | STM32_I2C_CR2_ADD10); 271 if (msg->flags & I2C_M_TEN) { 272 cr2 &= ~STM32_I2C_CR2_SADD10_MASK; 273 cr2 |= STM32_I2C_CR2_SADD10(msg->addr); 274 cr2 |= STM32_I2C_CR2_ADD10; 275 } else { 276 cr2 &= ~STM32_I2C_CR2_SADD7_MASK; 277 cr2 |= STM32_I2C_CR2_SADD7(msg->addr); 278 } 279 280 /* Set nb bytes to transfer and reload or autoend bits */ 281 cr2 &= ~(STM32_I2C_CR2_NBYTES_MASK | STM32_I2C_CR2_RELOAD | 282 STM32_I2C_CR2_AUTOEND); 283 if (msg->len > STM32_I2C_MAX_LEN) { 284 cr2 |= STM32_I2C_CR2_NBYTES(STM32_I2C_MAX_LEN); 285 cr2 |= STM32_I2C_CR2_RELOAD; 286 } else { 287 cr2 |= STM32_I2C_CR2_NBYTES(msg->len); 288 } 289 290 /* Write configurations register */ 291 writel(cr2, ®s->cr2); 292 293 /* START/ReSTART generation */ 294 setbits_le32(®s->cr2, STM32_I2C_CR2_START); 295 } 296 297 /* 298 * RELOAD mode must be selected if total number of data bytes to be 299 * sent is greater than MAX_LEN 300 */ 301 302 static void stm32_i2c_handle_reload(struct stm32_i2c_priv *i2c_priv, 303 struct i2c_msg *msg, bool stop) 304 { 305 struct stm32_i2c_regs *regs = i2c_priv->regs; 306 u32 cr2 = readl(®s->cr2); 307 308 cr2 &= ~STM32_I2C_CR2_NBYTES_MASK; 309 310 if (msg->len > STM32_I2C_MAX_LEN) { 311 cr2 |= STM32_I2C_CR2_NBYTES(STM32_I2C_MAX_LEN); 312 } else { 313 cr2 &= ~STM32_I2C_CR2_RELOAD; 314 cr2 |= STM32_I2C_CR2_NBYTES(msg->len); 315 } 316 317 writel(cr2, ®s->cr2); 318 } 319 320 static int stm32_i2c_wait_flags(struct stm32_i2c_priv *i2c_priv, 321 u32 flags, u32 *status) 322 { 323 struct stm32_i2c_regs *regs = i2c_priv->regs; 324 u32 time_start = get_timer(0); 325 326 *status = readl(®s->isr); 327 while (!(*status & flags)) { 328 if (get_timer(time_start) > CONFIG_SYS_HZ) { 329 debug("%s: i2c timeout\n", __func__); 330 return -ETIMEDOUT; 331 } 332 333 *status = readl(®s->isr); 334 } 335 336 return 0; 337 } 338 339 static int stm32_i2c_check_end_of_message(struct stm32_i2c_priv *i2c_priv) 340 { 341 struct stm32_i2c_regs *regs = i2c_priv->regs; 342 u32 mask = STM32_I2C_ISR_ERRORS | STM32_I2C_ISR_NACKF | 343 STM32_I2C_ISR_STOPF; 344 u32 status; 345 int ret; 346 347 ret = stm32_i2c_wait_flags(i2c_priv, mask, &status); 348 if (ret) 349 return ret; 350 351 if (status & STM32_I2C_ISR_BERR) { 352 debug("%s: Bus error\n", __func__); 353 354 /* Clear BERR flag */ 355 setbits_le32(®s->icr, STM32_I2C_ICR_BERRCF); 356 357 return -EIO; 358 } 359 360 if (status & STM32_I2C_ISR_ARLO) { 361 debug("%s: Arbitration lost\n", __func__); 362 363 /* Clear ARLO flag */ 364 setbits_le32(®s->icr, STM32_I2C_ICR_ARLOCF); 365 366 return -EAGAIN; 367 } 368 369 if (status & STM32_I2C_ISR_NACKF) { 370 debug("%s: Receive NACK\n", __func__); 371 372 /* Clear NACK flag */ 373 setbits_le32(®s->icr, STM32_I2C_ICR_NACKCF); 374 375 /* Wait until STOPF flag is set */ 376 mask = STM32_I2C_ISR_STOPF; 377 ret = stm32_i2c_wait_flags(i2c_priv, mask, &status); 378 if (ret) 379 return ret; 380 381 ret = -EIO; 382 } 383 384 if (status & STM32_I2C_ISR_STOPF) { 385 /* Clear STOP flag */ 386 setbits_le32(®s->icr, STM32_I2C_ICR_STOPCF); 387 388 /* Clear control register 2 */ 389 setbits_le32(®s->cr2, STM32_I2C_CR2_RESET_MASK); 390 } 391 392 return ret; 393 } 394 395 static int stm32_i2c_message_xfer(struct stm32_i2c_priv *i2c_priv, 396 struct i2c_msg *msg, bool stop) 397 { 398 struct stm32_i2c_regs *regs = i2c_priv->regs; 399 u32 status; 400 u32 mask = msg->flags & I2C_M_RD ? STM32_I2C_ISR_RXNE : 401 STM32_I2C_ISR_TXIS | STM32_I2C_ISR_NACKF; 402 int bytes_to_rw = msg->len > STM32_I2C_MAX_LEN ? 403 STM32_I2C_MAX_LEN : msg->len; 404 int ret = 0; 405 406 /* Add errors */ 407 mask |= STM32_I2C_ISR_ERRORS; 408 409 stm32_i2c_message_start(i2c_priv, msg, stop); 410 411 while (msg->len) { 412 /* 413 * Wait until TXIS/NACKF/BERR/ARLO flags or 414 * RXNE/BERR/ARLO flags are set 415 */ 416 ret = stm32_i2c_wait_flags(i2c_priv, mask, &status); 417 if (ret) 418 break; 419 420 if (status & (STM32_I2C_ISR_NACKF | STM32_I2C_ISR_ERRORS)) 421 break; 422 423 if (status & STM32_I2C_ISR_RXNE) { 424 *msg->buf++ = readb(®s->rxdr); 425 msg->len--; 426 bytes_to_rw--; 427 } 428 429 if (status & STM32_I2C_ISR_TXIS) { 430 writeb(*msg->buf++, ®s->txdr); 431 msg->len--; 432 bytes_to_rw--; 433 } 434 435 if (!bytes_to_rw && msg->len) { 436 /* Wait until TCR flag is set */ 437 mask = STM32_I2C_ISR_TCR; 438 ret = stm32_i2c_wait_flags(i2c_priv, mask, &status); 439 if (ret) 440 break; 441 442 bytes_to_rw = msg->len > STM32_I2C_MAX_LEN ? 443 STM32_I2C_MAX_LEN : msg->len; 444 mask = msg->flags & I2C_M_RD ? STM32_I2C_ISR_RXNE : 445 STM32_I2C_ISR_TXIS | STM32_I2C_ISR_NACKF; 446 447 stm32_i2c_handle_reload(i2c_priv, msg, stop); 448 } else if (!bytes_to_rw) { 449 /* Wait until TC flag is set */ 450 mask = STM32_I2C_ISR_TC; 451 ret = stm32_i2c_wait_flags(i2c_priv, mask, &status); 452 if (ret) 453 break; 454 455 if (!stop) 456 /* Message sent, new message has to be sent */ 457 return 0; 458 } 459 } 460 461 /* End of transfer, send stop condition */ 462 mask = STM32_I2C_CR2_STOP; 463 setbits_le32(®s->cr2, mask); 464 465 return stm32_i2c_check_end_of_message(i2c_priv); 466 } 467 468 static int stm32_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, 469 int nmsgs) 470 { 471 struct stm32_i2c_priv *i2c_priv = dev_get_priv(bus); 472 int ret; 473 474 ret = stm32_i2c_check_device_busy(i2c_priv); 475 if (ret) 476 return ret; 477 478 for (; nmsgs > 0; nmsgs--, msg++) { 479 ret = stm32_i2c_message_xfer(i2c_priv, msg, nmsgs == 1); 480 if (ret) 481 return ret; 482 } 483 484 return 0; 485 } 486 487 static int stm32_i2c_compute_solutions(struct stm32_i2c_setup *setup, 488 struct list_head *solutions) 489 { 490 struct stm32_i2c_timings *v; 491 u32 p_prev = STM32_PRESC_MAX; 492 u32 i2cclk = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC, 493 setup->clock_src); 494 u32 af_delay_min, af_delay_max; 495 u16 p, l, a; 496 int sdadel_min, sdadel_max, scldel_min; 497 int ret = 0; 498 499 af_delay_min = setup->analog_filter ? 500 STM32_I2C_ANALOG_FILTER_DELAY_MIN : 0; 501 af_delay_max = setup->analog_filter ? 502 STM32_I2C_ANALOG_FILTER_DELAY_MAX : 0; 503 504 sdadel_min = setup->fall_time - i2c_specs[setup->speed].hddat_min - 505 af_delay_min - (setup->dnf + 3) * i2cclk; 506 507 sdadel_max = i2c_specs[setup->speed].vddat_max - setup->rise_time - 508 af_delay_max - (setup->dnf + 4) * i2cclk; 509 510 scldel_min = setup->rise_time + i2c_specs[setup->speed].sudat_min; 511 512 if (sdadel_min < 0) 513 sdadel_min = 0; 514 if (sdadel_max < 0) 515 sdadel_max = 0; 516 517 debug("%s: SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n", __func__, 518 sdadel_min, sdadel_max, scldel_min); 519 520 /* Compute possible values for PRESC, SCLDEL and SDADEL */ 521 for (p = 0; p < STM32_PRESC_MAX; p++) { 522 for (l = 0; l < STM32_SCLDEL_MAX; l++) { 523 u32 scldel = (l + 1) * (p + 1) * i2cclk; 524 525 if (scldel < scldel_min) 526 continue; 527 528 for (a = 0; a < STM32_SDADEL_MAX; a++) { 529 u32 sdadel = (a * (p + 1) + 1) * i2cclk; 530 531 if (((sdadel >= sdadel_min) && 532 (sdadel <= sdadel_max)) && 533 (p != p_prev)) { 534 v = calloc(1, sizeof(*v)); 535 if (!v) 536 return -ENOMEM; 537 538 v->presc = p; 539 v->scldel = l; 540 v->sdadel = a; 541 p_prev = p; 542 543 list_add_tail(&v->node, solutions); 544 } 545 } 546 } 547 } 548 549 if (list_empty(solutions)) { 550 pr_err("%s: no Prescaler solution\n", __func__); 551 ret = -EPERM; 552 } 553 554 return ret; 555 } 556 557 static int stm32_i2c_choose_solution(struct stm32_i2c_setup *setup, 558 struct list_head *solutions, 559 struct stm32_i2c_timings *s) 560 { 561 struct stm32_i2c_timings *v; 562 u32 i2cbus = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC, 563 setup->speed_freq); 564 u32 clk_error_prev = i2cbus; 565 u32 i2cclk = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC, 566 setup->clock_src); 567 u32 clk_min, clk_max; 568 u32 af_delay_min; 569 u32 dnf_delay; 570 u32 tsync; 571 u16 l, h; 572 bool sol_found = false; 573 int ret = 0; 574 575 af_delay_min = setup->analog_filter ? 576 STM32_I2C_ANALOG_FILTER_DELAY_MIN : 0; 577 dnf_delay = setup->dnf * i2cclk; 578 579 tsync = af_delay_min + dnf_delay + (2 * i2cclk); 580 clk_max = STM32_NSEC_PER_SEC / i2c_specs[setup->speed].rate_min; 581 clk_min = STM32_NSEC_PER_SEC / i2c_specs[setup->speed].rate_max; 582 583 /* 584 * Among Prescaler possibilities discovered above figures out SCL Low 585 * and High Period. Provided: 586 * - SCL Low Period has to be higher than Low Period of the SCL Clock 587 * defined by I2C Specification. I2C Clock has to be lower than 588 * (SCL Low Period - Analog/Digital filters) / 4. 589 * - SCL High Period has to be lower than High Period of the SCL Clock 590 * defined by I2C Specification 591 * - I2C Clock has to be lower than SCL High Period 592 */ 593 list_for_each_entry(v, solutions, node) { 594 u32 prescaler = (v->presc + 1) * i2cclk; 595 596 for (l = 0; l < STM32_SCLL_MAX; l++) { 597 u32 tscl_l = (l + 1) * prescaler + tsync; 598 if ((tscl_l < i2c_specs[setup->speed].l_min) || 599 (i2cclk >= 600 ((tscl_l - af_delay_min - dnf_delay) / 4))) { 601 continue; 602 } 603 604 for (h = 0; h < STM32_SCLH_MAX; h++) { 605 u32 tscl_h = (h + 1) * prescaler + tsync; 606 u32 tscl = tscl_l + tscl_h + 607 setup->rise_time + setup->fall_time; 608 609 if ((tscl >= clk_min) && (tscl <= clk_max) && 610 (tscl_h >= i2c_specs[setup->speed].h_min) && 611 (i2cclk < tscl_h)) { 612 int clk_error = tscl - i2cbus; 613 614 if (clk_error < 0) 615 clk_error = -clk_error; 616 617 if (clk_error < clk_error_prev) { 618 clk_error_prev = clk_error; 619 v->scll = l; 620 v->sclh = h; 621 sol_found = true; 622 memcpy(s, v, sizeof(*s)); 623 } 624 } 625 } 626 } 627 } 628 629 if (!sol_found) { 630 pr_err("%s: no solution at all\n", __func__); 631 ret = -EPERM; 632 } 633 634 return ret; 635 } 636 637 static int stm32_i2c_compute_timing(struct stm32_i2c_priv *i2c_priv, 638 struct stm32_i2c_setup *setup, 639 struct stm32_i2c_timings *output) 640 { 641 struct stm32_i2c_timings *v, *_v; 642 struct list_head solutions; 643 int ret; 644 645 if (setup->speed >= STM32_I2C_SPEED_END) { 646 pr_err("%s: speed out of bound {%d/%d}\n", __func__, 647 setup->speed, STM32_I2C_SPEED_END - 1); 648 return -EINVAL; 649 } 650 651 if ((setup->rise_time > i2c_specs[setup->speed].rise_max) || 652 (setup->fall_time > i2c_specs[setup->speed].fall_max)) { 653 pr_err("%s :timings out of bound Rise{%d>%d}/Fall{%d>%d}\n", 654 __func__, 655 setup->rise_time, i2c_specs[setup->speed].rise_max, 656 setup->fall_time, i2c_specs[setup->speed].fall_max); 657 return -EINVAL; 658 } 659 660 if (setup->dnf > STM32_I2C_DNF_MAX) { 661 pr_err("%s: DNF out of bound %d/%d\n", __func__, 662 setup->dnf, STM32_I2C_DNF_MAX); 663 return -EINVAL; 664 } 665 666 if (setup->speed_freq > i2c_specs[setup->speed].rate) { 667 pr_err("%s: Freq {%d/%d}\n", __func__, 668 setup->speed_freq, i2c_specs[setup->speed].rate); 669 return -EINVAL; 670 } 671 672 INIT_LIST_HEAD(&solutions); 673 ret = stm32_i2c_compute_solutions(setup, &solutions); 674 if (ret) 675 goto exit; 676 677 ret = stm32_i2c_choose_solution(setup, &solutions, output); 678 if (ret) 679 goto exit; 680 681 debug("%s: Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n", 682 __func__, output->presc, 683 output->scldel, output->sdadel, 684 output->scll, output->sclh); 685 686 exit: 687 /* Release list and memory */ 688 list_for_each_entry_safe(v, _v, &solutions, node) { 689 list_del(&v->node); 690 free(v); 691 } 692 693 return ret; 694 } 695 696 static int stm32_i2c_setup_timing(struct stm32_i2c_priv *i2c_priv, 697 struct stm32_i2c_timings *timing) 698 { 699 struct stm32_i2c_setup *setup = i2c_priv->setup; 700 int ret = 0; 701 702 setup->speed = i2c_priv->speed; 703 setup->speed_freq = i2c_specs[setup->speed].rate; 704 setup->clock_src = clk_get_rate(&i2c_priv->clk); 705 706 if (!setup->clock_src) { 707 pr_err("%s: clock rate is 0\n", __func__); 708 return -EINVAL; 709 } 710 711 do { 712 ret = stm32_i2c_compute_timing(i2c_priv, setup, timing); 713 if (ret) { 714 debug("%s: failed to compute I2C timings.\n", 715 __func__); 716 if (i2c_priv->speed > STM32_I2C_SPEED_STANDARD) { 717 i2c_priv->speed--; 718 setup->speed = i2c_priv->speed; 719 setup->speed_freq = 720 i2c_specs[setup->speed].rate; 721 debug("%s: downgrade I2C Speed Freq to (%i)\n", 722 __func__, i2c_specs[setup->speed].rate); 723 } else { 724 break; 725 } 726 } 727 } while (ret); 728 729 if (ret) { 730 pr_err("%s: impossible to compute I2C timings.\n", __func__); 731 return ret; 732 } 733 734 debug("%s: I2C Speed(%i), Freq(%i), Clk Source(%i)\n", __func__, 735 setup->speed, setup->speed_freq, setup->clock_src); 736 debug("%s: I2C Rise(%i) and Fall(%i) Time\n", __func__, 737 setup->rise_time, setup->fall_time); 738 debug("%s: I2C Analog Filter(%s), DNF(%i)\n", __func__, 739 setup->analog_filter ? "On" : "Off", setup->dnf); 740 741 return 0; 742 } 743 744 static int stm32_i2c_hw_config(struct stm32_i2c_priv *i2c_priv) 745 { 746 struct stm32_i2c_regs *regs = i2c_priv->regs; 747 struct stm32_i2c_timings t; 748 int ret; 749 u32 timing = 0; 750 751 ret = stm32_i2c_setup_timing(i2c_priv, &t); 752 if (ret) 753 return ret; 754 755 /* Disable I2C */ 756 clrbits_le32(®s->cr1, STM32_I2C_CR1_PE); 757 758 /* Timing settings */ 759 timing |= STM32_I2C_TIMINGR_PRESC(t.presc); 760 timing |= STM32_I2C_TIMINGR_SCLDEL(t.scldel); 761 timing |= STM32_I2C_TIMINGR_SDADEL(t.sdadel); 762 timing |= STM32_I2C_TIMINGR_SCLH(t.sclh); 763 timing |= STM32_I2C_TIMINGR_SCLL(t.scll); 764 writel(timing, ®s->timingr); 765 766 /* Enable I2C */ 767 if (i2c_priv->setup->analog_filter) 768 clrbits_le32(®s->cr1, STM32_I2C_CR1_ANFOFF); 769 else 770 setbits_le32(®s->cr1, STM32_I2C_CR1_ANFOFF); 771 setbits_le32(®s->cr1, STM32_I2C_CR1_PE); 772 773 return 0; 774 } 775 776 static int stm32_i2c_set_bus_speed(struct udevice *bus, unsigned int speed) 777 { 778 struct stm32_i2c_priv *i2c_priv = dev_get_priv(bus); 779 780 switch (speed) { 781 case STANDARD_RATE: 782 i2c_priv->speed = STM32_I2C_SPEED_STANDARD; 783 break; 784 case FAST_RATE: 785 i2c_priv->speed = STM32_I2C_SPEED_FAST; 786 break; 787 case FAST_PLUS_RATE: 788 i2c_priv->speed = STM32_I2C_SPEED_FAST_PLUS; 789 break; 790 default: 791 debug("%s: Speed %d not supported\n", __func__, speed); 792 return -EINVAL; 793 } 794 795 return stm32_i2c_hw_config(i2c_priv); 796 } 797 798 static int stm32_i2c_probe(struct udevice *dev) 799 { 800 struct stm32_i2c_priv *i2c_priv = dev_get_priv(dev); 801 struct reset_ctl reset_ctl; 802 fdt_addr_t addr; 803 int ret; 804 805 addr = dev_read_addr(dev); 806 if (addr == FDT_ADDR_T_NONE) 807 return -EINVAL; 808 809 i2c_priv->regs = (struct stm32_i2c_regs *)addr; 810 811 ret = clk_get_by_index(dev, 0, &i2c_priv->clk); 812 if (ret) 813 return ret; 814 815 ret = clk_enable(&i2c_priv->clk); 816 if (ret) 817 goto clk_free; 818 819 ret = reset_get_by_index(dev, 0, &reset_ctl); 820 if (ret) 821 goto clk_disable; 822 823 reset_assert(&reset_ctl); 824 udelay(2); 825 reset_deassert(&reset_ctl); 826 827 return 0; 828 829 clk_disable: 830 clk_disable(&i2c_priv->clk); 831 clk_free: 832 clk_free(&i2c_priv->clk); 833 834 return ret; 835 } 836 837 static int stm32_ofdata_to_platdata(struct udevice *dev) 838 { 839 struct stm32_i2c_priv *i2c_priv = dev_get_priv(dev); 840 u32 rise_time, fall_time; 841 842 i2c_priv->setup = (struct stm32_i2c_setup *)dev_get_driver_data(dev); 843 if (!i2c_priv->setup) 844 return -EINVAL; 845 846 rise_time = dev_read_u32_default(dev, "i2c-scl-rising-time-ns", 0); 847 if (rise_time) 848 i2c_priv->setup->rise_time = rise_time; 849 850 fall_time = dev_read_u32_default(dev, "i2c-scl-falling-time-ns", 0); 851 if (fall_time) 852 i2c_priv->setup->fall_time = fall_time; 853 854 return 0; 855 } 856 857 static const struct dm_i2c_ops stm32_i2c_ops = { 858 .xfer = stm32_i2c_xfer, 859 .set_bus_speed = stm32_i2c_set_bus_speed, 860 }; 861 862 static const struct udevice_id stm32_i2c_of_match[] = { 863 { .compatible = "st,stm32f7-i2c", .data = (ulong)&stm32f7_setup }, 864 {} 865 }; 866 867 U_BOOT_DRIVER(stm32f7_i2c) = { 868 .name = "stm32f7-i2c", 869 .id = UCLASS_I2C, 870 .of_match = stm32_i2c_of_match, 871 .ofdata_to_platdata = stm32_ofdata_to_platdata, 872 .probe = stm32_i2c_probe, 873 .priv_auto_alloc_size = sizeof(struct stm32_i2c_priv), 874 .ops = &stm32_i2c_ops, 875 }; 876