1*4fadcaf0SPatrice Chotard /* 2*4fadcaf0SPatrice Chotard * (C) Copyright 2017 STMicroelectronics 3*4fadcaf0SPatrice Chotard * 4*4fadcaf0SPatrice Chotard * SPDX-License-Identifier: GPL-2.0+ 5*4fadcaf0SPatrice Chotard */ 6*4fadcaf0SPatrice Chotard 7*4fadcaf0SPatrice Chotard #include <common.h> 8*4fadcaf0SPatrice Chotard #include <clk.h> 9*4fadcaf0SPatrice Chotard #include <dm.h> 10*4fadcaf0SPatrice Chotard #include <i2c.h> 11*4fadcaf0SPatrice Chotard #include <reset.h> 12*4fadcaf0SPatrice Chotard 13*4fadcaf0SPatrice Chotard #include <dm/device.h> 14*4fadcaf0SPatrice Chotard #include <linux/io.h> 15*4fadcaf0SPatrice Chotard 16*4fadcaf0SPatrice Chotard /* STM32 I2C registers */ 17*4fadcaf0SPatrice Chotard struct stm32_i2c_regs { 18*4fadcaf0SPatrice Chotard u32 cr1; /* I2C control register 1 */ 19*4fadcaf0SPatrice Chotard u32 cr2; /* I2C control register 2 */ 20*4fadcaf0SPatrice Chotard u32 oar1; /* I2C own address 1 register */ 21*4fadcaf0SPatrice Chotard u32 oar2; /* I2C own address 2 register */ 22*4fadcaf0SPatrice Chotard u32 timingr; /* I2C timing register */ 23*4fadcaf0SPatrice Chotard u32 timeoutr; /* I2C timeout register */ 24*4fadcaf0SPatrice Chotard u32 isr; /* I2C interrupt and status register */ 25*4fadcaf0SPatrice Chotard u32 icr; /* I2C interrupt clear register */ 26*4fadcaf0SPatrice Chotard u32 pecr; /* I2C packet error checking register */ 27*4fadcaf0SPatrice Chotard u32 rxdr; /* I2C receive data register */ 28*4fadcaf0SPatrice Chotard u32 txdr; /* I2C transmit data register */ 29*4fadcaf0SPatrice Chotard }; 30*4fadcaf0SPatrice Chotard 31*4fadcaf0SPatrice Chotard #define STM32_I2C_CR1 0x00 32*4fadcaf0SPatrice Chotard #define STM32_I2C_CR2 0x04 33*4fadcaf0SPatrice Chotard #define STM32_I2C_TIMINGR 0x10 34*4fadcaf0SPatrice Chotard #define STM32_I2C_ISR 0x18 35*4fadcaf0SPatrice Chotard #define STM32_I2C_ICR 0x1C 36*4fadcaf0SPatrice Chotard #define STM32_I2C_RXDR 0x24 37*4fadcaf0SPatrice Chotard #define STM32_I2C_TXDR 0x28 38*4fadcaf0SPatrice Chotard 39*4fadcaf0SPatrice Chotard /* STM32 I2C control 1 */ 40*4fadcaf0SPatrice Chotard #define STM32_I2C_CR1_ANFOFF BIT(12) 41*4fadcaf0SPatrice Chotard #define STM32_I2C_CR1_ERRIE BIT(7) 42*4fadcaf0SPatrice Chotard #define STM32_I2C_CR1_TCIE BIT(6) 43*4fadcaf0SPatrice Chotard #define STM32_I2C_CR1_STOPIE BIT(5) 44*4fadcaf0SPatrice Chotard #define STM32_I2C_CR1_NACKIE BIT(4) 45*4fadcaf0SPatrice Chotard #define STM32_I2C_CR1_ADDRIE BIT(3) 46*4fadcaf0SPatrice Chotard #define STM32_I2C_CR1_RXIE BIT(2) 47*4fadcaf0SPatrice Chotard #define STM32_I2C_CR1_TXIE BIT(1) 48*4fadcaf0SPatrice Chotard #define STM32_I2C_CR1_PE BIT(0) 49*4fadcaf0SPatrice Chotard 50*4fadcaf0SPatrice Chotard /* STM32 I2C control 2 */ 51*4fadcaf0SPatrice Chotard #define STM32_I2C_CR2_AUTOEND BIT(25) 52*4fadcaf0SPatrice Chotard #define STM32_I2C_CR2_RELOAD BIT(24) 53*4fadcaf0SPatrice Chotard #define STM32_I2C_CR2_NBYTES_MASK GENMASK(23, 16) 54*4fadcaf0SPatrice Chotard #define STM32_I2C_CR2_NBYTES(n) ((n & 0xff) << 16) 55*4fadcaf0SPatrice Chotard #define STM32_I2C_CR2_NACK BIT(15) 56*4fadcaf0SPatrice Chotard #define STM32_I2C_CR2_STOP BIT(14) 57*4fadcaf0SPatrice Chotard #define STM32_I2C_CR2_START BIT(13) 58*4fadcaf0SPatrice Chotard #define STM32_I2C_CR2_HEAD10R BIT(12) 59*4fadcaf0SPatrice Chotard #define STM32_I2C_CR2_ADD10 BIT(11) 60*4fadcaf0SPatrice Chotard #define STM32_I2C_CR2_RD_WRN BIT(10) 61*4fadcaf0SPatrice Chotard #define STM32_I2C_CR2_SADD10_MASK GENMASK(9, 0) 62*4fadcaf0SPatrice Chotard #define STM32_I2C_CR2_SADD10(n) ((n & STM32_I2C_CR2_SADD10_MASK)) 63*4fadcaf0SPatrice Chotard #define STM32_I2C_CR2_SADD7_MASK GENMASK(7, 1) 64*4fadcaf0SPatrice Chotard #define STM32_I2C_CR2_SADD7(n) ((n & 0x7f) << 1) 65*4fadcaf0SPatrice Chotard #define STM32_I2C_CR2_RESET_MASK (STM32_I2C_CR2_HEAD10R \ 66*4fadcaf0SPatrice Chotard | STM32_I2C_CR2_NBYTES_MASK \ 67*4fadcaf0SPatrice Chotard | STM32_I2C_CR2_SADD7_MASK \ 68*4fadcaf0SPatrice Chotard | STM32_I2C_CR2_RELOAD \ 69*4fadcaf0SPatrice Chotard | STM32_I2C_CR2_RD_WRN) 70*4fadcaf0SPatrice Chotard 71*4fadcaf0SPatrice Chotard /* STM32 I2C Interrupt Status */ 72*4fadcaf0SPatrice Chotard #define STM32_I2C_ISR_BUSY BIT(15) 73*4fadcaf0SPatrice Chotard #define STM32_I2C_ISR_ARLO BIT(9) 74*4fadcaf0SPatrice Chotard #define STM32_I2C_ISR_BERR BIT(8) 75*4fadcaf0SPatrice Chotard #define STM32_I2C_ISR_TCR BIT(7) 76*4fadcaf0SPatrice Chotard #define STM32_I2C_ISR_TC BIT(6) 77*4fadcaf0SPatrice Chotard #define STM32_I2C_ISR_STOPF BIT(5) 78*4fadcaf0SPatrice Chotard #define STM32_I2C_ISR_NACKF BIT(4) 79*4fadcaf0SPatrice Chotard #define STM32_I2C_ISR_ADDR BIT(3) 80*4fadcaf0SPatrice Chotard #define STM32_I2C_ISR_RXNE BIT(2) 81*4fadcaf0SPatrice Chotard #define STM32_I2C_ISR_TXIS BIT(1) 82*4fadcaf0SPatrice Chotard #define STM32_I2C_ISR_TXE BIT(0) 83*4fadcaf0SPatrice Chotard #define STM32_I2C_ISR_ERRORS (STM32_I2C_ISR_BERR \ 84*4fadcaf0SPatrice Chotard | STM32_I2C_ISR_ARLO) 85*4fadcaf0SPatrice Chotard 86*4fadcaf0SPatrice Chotard /* STM32 I2C Interrupt Clear */ 87*4fadcaf0SPatrice Chotard #define STM32_I2C_ICR_ARLOCF BIT(9) 88*4fadcaf0SPatrice Chotard #define STM32_I2C_ICR_BERRCF BIT(8) 89*4fadcaf0SPatrice Chotard #define STM32_I2C_ICR_STOPCF BIT(5) 90*4fadcaf0SPatrice Chotard #define STM32_I2C_ICR_NACKCF BIT(4) 91*4fadcaf0SPatrice Chotard 92*4fadcaf0SPatrice Chotard /* STM32 I2C Timing */ 93*4fadcaf0SPatrice Chotard #define STM32_I2C_TIMINGR_PRESC(n) ((n & 0xf) << 28) 94*4fadcaf0SPatrice Chotard #define STM32_I2C_TIMINGR_SCLDEL(n) ((n & 0xf) << 20) 95*4fadcaf0SPatrice Chotard #define STM32_I2C_TIMINGR_SDADEL(n) ((n & 0xf) << 16) 96*4fadcaf0SPatrice Chotard #define STM32_I2C_TIMINGR_SCLH(n) ((n & 0xff) << 8) 97*4fadcaf0SPatrice Chotard #define STM32_I2C_TIMINGR_SCLL(n) (n & 0xff) 98*4fadcaf0SPatrice Chotard 99*4fadcaf0SPatrice Chotard #define STM32_I2C_MAX_LEN 0xff 100*4fadcaf0SPatrice Chotard 101*4fadcaf0SPatrice Chotard #define STM32_I2C_DNF_DEFAULT 0 102*4fadcaf0SPatrice Chotard #define STM32_I2C_DNF_MAX 16 103*4fadcaf0SPatrice Chotard 104*4fadcaf0SPatrice Chotard #define STM32_I2C_ANALOG_FILTER_ENABLE 1 105*4fadcaf0SPatrice Chotard #define STM32_I2C_ANALOG_FILTER_DELAY_MIN 50 /* ns */ 106*4fadcaf0SPatrice Chotard #define STM32_I2C_ANALOG_FILTER_DELAY_MAX 260 /* ns */ 107*4fadcaf0SPatrice Chotard 108*4fadcaf0SPatrice Chotard #define STM32_I2C_RISE_TIME_DEFAULT 25 /* ns */ 109*4fadcaf0SPatrice Chotard #define STM32_I2C_FALL_TIME_DEFAULT 10 /* ns */ 110*4fadcaf0SPatrice Chotard 111*4fadcaf0SPatrice Chotard #define STM32_PRESC_MAX BIT(4) 112*4fadcaf0SPatrice Chotard #define STM32_SCLDEL_MAX BIT(4) 113*4fadcaf0SPatrice Chotard #define STM32_SDADEL_MAX BIT(4) 114*4fadcaf0SPatrice Chotard #define STM32_SCLH_MAX BIT(8) 115*4fadcaf0SPatrice Chotard #define STM32_SCLL_MAX BIT(8) 116*4fadcaf0SPatrice Chotard 117*4fadcaf0SPatrice Chotard #define STM32_NSEC_PER_SEC 1000000000L 118*4fadcaf0SPatrice Chotard 119*4fadcaf0SPatrice Chotard #define STANDARD_RATE 100000 120*4fadcaf0SPatrice Chotard #define FAST_RATE 400000 121*4fadcaf0SPatrice Chotard #define FAST_PLUS_RATE 1000000 122*4fadcaf0SPatrice Chotard 123*4fadcaf0SPatrice Chotard enum stm32_i2c_speed { 124*4fadcaf0SPatrice Chotard STM32_I2C_SPEED_STANDARD, /* 100 kHz */ 125*4fadcaf0SPatrice Chotard STM32_I2C_SPEED_FAST, /* 400 kHz */ 126*4fadcaf0SPatrice Chotard STM32_I2C_SPEED_FAST_PLUS, /* 1 MHz */ 127*4fadcaf0SPatrice Chotard STM32_I2C_SPEED_END, 128*4fadcaf0SPatrice Chotard }; 129*4fadcaf0SPatrice Chotard 130*4fadcaf0SPatrice Chotard /** 131*4fadcaf0SPatrice Chotard * struct stm32_i2c_spec - private i2c specification timing 132*4fadcaf0SPatrice Chotard * @rate: I2C bus speed (Hz) 133*4fadcaf0SPatrice Chotard * @rate_min: 80% of I2C bus speed (Hz) 134*4fadcaf0SPatrice Chotard * @rate_max: 120% of I2C bus speed (Hz) 135*4fadcaf0SPatrice Chotard * @fall_max: Max fall time of both SDA and SCL signals (ns) 136*4fadcaf0SPatrice Chotard * @rise_max: Max rise time of both SDA and SCL signals (ns) 137*4fadcaf0SPatrice Chotard * @hddat_min: Min data hold time (ns) 138*4fadcaf0SPatrice Chotard * @vddat_max: Max data valid time (ns) 139*4fadcaf0SPatrice Chotard * @sudat_min: Min data setup time (ns) 140*4fadcaf0SPatrice Chotard * @l_min: Min low period of the SCL clock (ns) 141*4fadcaf0SPatrice Chotard * @h_min: Min high period of the SCL clock (ns) 142*4fadcaf0SPatrice Chotard */ 143*4fadcaf0SPatrice Chotard 144*4fadcaf0SPatrice Chotard struct stm32_i2c_spec { 145*4fadcaf0SPatrice Chotard u32 rate; 146*4fadcaf0SPatrice Chotard u32 rate_min; 147*4fadcaf0SPatrice Chotard u32 rate_max; 148*4fadcaf0SPatrice Chotard u32 fall_max; 149*4fadcaf0SPatrice Chotard u32 rise_max; 150*4fadcaf0SPatrice Chotard u32 hddat_min; 151*4fadcaf0SPatrice Chotard u32 vddat_max; 152*4fadcaf0SPatrice Chotard u32 sudat_min; 153*4fadcaf0SPatrice Chotard u32 l_min; 154*4fadcaf0SPatrice Chotard u32 h_min; 155*4fadcaf0SPatrice Chotard }; 156*4fadcaf0SPatrice Chotard 157*4fadcaf0SPatrice Chotard /** 158*4fadcaf0SPatrice Chotard * struct stm32_i2c_setup - private I2C timing setup parameters 159*4fadcaf0SPatrice Chotard * @speed: I2C speed mode (standard, Fast Plus) 160*4fadcaf0SPatrice Chotard * @speed_freq: I2C speed frequency (Hz) 161*4fadcaf0SPatrice Chotard * @clock_src: I2C clock source frequency (Hz) 162*4fadcaf0SPatrice Chotard * @rise_time: Rise time (ns) 163*4fadcaf0SPatrice Chotard * @fall_time: Fall time (ns) 164*4fadcaf0SPatrice Chotard * @dnf: Digital filter coefficient (0-16) 165*4fadcaf0SPatrice Chotard * @analog_filter: Analog filter delay (On/Off) 166*4fadcaf0SPatrice Chotard */ 167*4fadcaf0SPatrice Chotard struct stm32_i2c_setup { 168*4fadcaf0SPatrice Chotard enum stm32_i2c_speed speed; 169*4fadcaf0SPatrice Chotard u32 speed_freq; 170*4fadcaf0SPatrice Chotard u32 clock_src; 171*4fadcaf0SPatrice Chotard u32 rise_time; 172*4fadcaf0SPatrice Chotard u32 fall_time; 173*4fadcaf0SPatrice Chotard u8 dnf; 174*4fadcaf0SPatrice Chotard bool analog_filter; 175*4fadcaf0SPatrice Chotard }; 176*4fadcaf0SPatrice Chotard 177*4fadcaf0SPatrice Chotard /** 178*4fadcaf0SPatrice Chotard * struct stm32_i2c_timings - private I2C output parameters 179*4fadcaf0SPatrice Chotard * @prec: Prescaler value 180*4fadcaf0SPatrice Chotard * @scldel: Data setup time 181*4fadcaf0SPatrice Chotard * @sdadel: Data hold time 182*4fadcaf0SPatrice Chotard * @sclh: SCL high period (master mode) 183*4fadcaf0SPatrice Chotard * @sclh: SCL low period (master mode) 184*4fadcaf0SPatrice Chotard */ 185*4fadcaf0SPatrice Chotard struct stm32_i2c_timings { 186*4fadcaf0SPatrice Chotard struct list_head node; 187*4fadcaf0SPatrice Chotard u8 presc; 188*4fadcaf0SPatrice Chotard u8 scldel; 189*4fadcaf0SPatrice Chotard u8 sdadel; 190*4fadcaf0SPatrice Chotard u8 sclh; 191*4fadcaf0SPatrice Chotard u8 scll; 192*4fadcaf0SPatrice Chotard }; 193*4fadcaf0SPatrice Chotard 194*4fadcaf0SPatrice Chotard struct stm32_i2c_priv { 195*4fadcaf0SPatrice Chotard struct stm32_i2c_regs *regs; 196*4fadcaf0SPatrice Chotard struct clk clk; 197*4fadcaf0SPatrice Chotard struct stm32_i2c_setup *setup; 198*4fadcaf0SPatrice Chotard int speed; 199*4fadcaf0SPatrice Chotard }; 200*4fadcaf0SPatrice Chotard 201*4fadcaf0SPatrice Chotard static struct stm32_i2c_spec i2c_specs[] = { 202*4fadcaf0SPatrice Chotard [STM32_I2C_SPEED_STANDARD] = { 203*4fadcaf0SPatrice Chotard .rate = STANDARD_RATE, 204*4fadcaf0SPatrice Chotard .rate_min = 8000, 205*4fadcaf0SPatrice Chotard .rate_max = 120000, 206*4fadcaf0SPatrice Chotard .fall_max = 300, 207*4fadcaf0SPatrice Chotard .rise_max = 1000, 208*4fadcaf0SPatrice Chotard .hddat_min = 0, 209*4fadcaf0SPatrice Chotard .vddat_max = 3450, 210*4fadcaf0SPatrice Chotard .sudat_min = 250, 211*4fadcaf0SPatrice Chotard .l_min = 4700, 212*4fadcaf0SPatrice Chotard .h_min = 4000, 213*4fadcaf0SPatrice Chotard }, 214*4fadcaf0SPatrice Chotard [STM32_I2C_SPEED_FAST] = { 215*4fadcaf0SPatrice Chotard .rate = FAST_RATE, 216*4fadcaf0SPatrice Chotard .rate_min = 320000, 217*4fadcaf0SPatrice Chotard .rate_max = 480000, 218*4fadcaf0SPatrice Chotard .fall_max = 300, 219*4fadcaf0SPatrice Chotard .rise_max = 300, 220*4fadcaf0SPatrice Chotard .hddat_min = 0, 221*4fadcaf0SPatrice Chotard .vddat_max = 900, 222*4fadcaf0SPatrice Chotard .sudat_min = 100, 223*4fadcaf0SPatrice Chotard .l_min = 1300, 224*4fadcaf0SPatrice Chotard .h_min = 600, 225*4fadcaf0SPatrice Chotard }, 226*4fadcaf0SPatrice Chotard [STM32_I2C_SPEED_FAST_PLUS] = { 227*4fadcaf0SPatrice Chotard .rate = FAST_PLUS_RATE, 228*4fadcaf0SPatrice Chotard .rate_min = 800000, 229*4fadcaf0SPatrice Chotard .rate_max = 1200000, 230*4fadcaf0SPatrice Chotard .fall_max = 100, 231*4fadcaf0SPatrice Chotard .rise_max = 120, 232*4fadcaf0SPatrice Chotard .hddat_min = 0, 233*4fadcaf0SPatrice Chotard .vddat_max = 450, 234*4fadcaf0SPatrice Chotard .sudat_min = 50, 235*4fadcaf0SPatrice Chotard .l_min = 500, 236*4fadcaf0SPatrice Chotard .h_min = 260, 237*4fadcaf0SPatrice Chotard }, 238*4fadcaf0SPatrice Chotard }; 239*4fadcaf0SPatrice Chotard 240*4fadcaf0SPatrice Chotard static struct stm32_i2c_setup stm32f7_setup = { 241*4fadcaf0SPatrice Chotard .rise_time = STM32_I2C_RISE_TIME_DEFAULT, 242*4fadcaf0SPatrice Chotard .fall_time = STM32_I2C_FALL_TIME_DEFAULT, 243*4fadcaf0SPatrice Chotard .dnf = STM32_I2C_DNF_DEFAULT, 244*4fadcaf0SPatrice Chotard .analog_filter = STM32_I2C_ANALOG_FILTER_ENABLE, 245*4fadcaf0SPatrice Chotard }; 246*4fadcaf0SPatrice Chotard 247*4fadcaf0SPatrice Chotard DECLARE_GLOBAL_DATA_PTR; 248*4fadcaf0SPatrice Chotard 249*4fadcaf0SPatrice Chotard static int stm32_i2c_check_device_busy(struct stm32_i2c_priv *i2c_priv) 250*4fadcaf0SPatrice Chotard { 251*4fadcaf0SPatrice Chotard struct stm32_i2c_regs *regs = i2c_priv->regs; 252*4fadcaf0SPatrice Chotard u32 status = readl(®s->isr); 253*4fadcaf0SPatrice Chotard 254*4fadcaf0SPatrice Chotard if (status & STM32_I2C_ISR_BUSY) 255*4fadcaf0SPatrice Chotard return -EBUSY; 256*4fadcaf0SPatrice Chotard 257*4fadcaf0SPatrice Chotard return 0; 258*4fadcaf0SPatrice Chotard } 259*4fadcaf0SPatrice Chotard 260*4fadcaf0SPatrice Chotard static void stm32_i2c_message_start(struct stm32_i2c_priv *i2c_priv, 261*4fadcaf0SPatrice Chotard struct i2c_msg *msg, bool stop) 262*4fadcaf0SPatrice Chotard { 263*4fadcaf0SPatrice Chotard struct stm32_i2c_regs *regs = i2c_priv->regs; 264*4fadcaf0SPatrice Chotard u32 cr2 = readl(®s->cr2); 265*4fadcaf0SPatrice Chotard 266*4fadcaf0SPatrice Chotard /* Set transfer direction */ 267*4fadcaf0SPatrice Chotard cr2 &= ~STM32_I2C_CR2_RD_WRN; 268*4fadcaf0SPatrice Chotard if (msg->flags & I2C_M_RD) 269*4fadcaf0SPatrice Chotard cr2 |= STM32_I2C_CR2_RD_WRN; 270*4fadcaf0SPatrice Chotard 271*4fadcaf0SPatrice Chotard /* Set slave address */ 272*4fadcaf0SPatrice Chotard cr2 &= ~(STM32_I2C_CR2_HEAD10R | STM32_I2C_CR2_ADD10); 273*4fadcaf0SPatrice Chotard if (msg->flags & I2C_M_TEN) { 274*4fadcaf0SPatrice Chotard cr2 &= ~STM32_I2C_CR2_SADD10_MASK; 275*4fadcaf0SPatrice Chotard cr2 |= STM32_I2C_CR2_SADD10(msg->addr); 276*4fadcaf0SPatrice Chotard cr2 |= STM32_I2C_CR2_ADD10; 277*4fadcaf0SPatrice Chotard } else { 278*4fadcaf0SPatrice Chotard cr2 &= ~STM32_I2C_CR2_SADD7_MASK; 279*4fadcaf0SPatrice Chotard cr2 |= STM32_I2C_CR2_SADD7(msg->addr); 280*4fadcaf0SPatrice Chotard } 281*4fadcaf0SPatrice Chotard 282*4fadcaf0SPatrice Chotard /* Set nb bytes to transfer and reload or autoend bits */ 283*4fadcaf0SPatrice Chotard cr2 &= ~(STM32_I2C_CR2_NBYTES_MASK | STM32_I2C_CR2_RELOAD | 284*4fadcaf0SPatrice Chotard STM32_I2C_CR2_AUTOEND); 285*4fadcaf0SPatrice Chotard if (msg->len > STM32_I2C_MAX_LEN) { 286*4fadcaf0SPatrice Chotard cr2 |= STM32_I2C_CR2_NBYTES(STM32_I2C_MAX_LEN); 287*4fadcaf0SPatrice Chotard cr2 |= STM32_I2C_CR2_RELOAD; 288*4fadcaf0SPatrice Chotard } else { 289*4fadcaf0SPatrice Chotard cr2 |= STM32_I2C_CR2_NBYTES(msg->len); 290*4fadcaf0SPatrice Chotard } 291*4fadcaf0SPatrice Chotard 292*4fadcaf0SPatrice Chotard /* Write configurations register */ 293*4fadcaf0SPatrice Chotard writel(cr2, ®s->cr2); 294*4fadcaf0SPatrice Chotard 295*4fadcaf0SPatrice Chotard /* START/ReSTART generation */ 296*4fadcaf0SPatrice Chotard setbits_le32(®s->cr2, STM32_I2C_CR2_START); 297*4fadcaf0SPatrice Chotard } 298*4fadcaf0SPatrice Chotard 299*4fadcaf0SPatrice Chotard /* 300*4fadcaf0SPatrice Chotard * RELOAD mode must be selected if total number of data bytes to be 301*4fadcaf0SPatrice Chotard * sent is greater than MAX_LEN 302*4fadcaf0SPatrice Chotard */ 303*4fadcaf0SPatrice Chotard 304*4fadcaf0SPatrice Chotard static void stm32_i2c_handle_reload(struct stm32_i2c_priv *i2c_priv, 305*4fadcaf0SPatrice Chotard struct i2c_msg *msg, bool stop) 306*4fadcaf0SPatrice Chotard { 307*4fadcaf0SPatrice Chotard struct stm32_i2c_regs *regs = i2c_priv->regs; 308*4fadcaf0SPatrice Chotard u32 cr2 = readl(®s->cr2); 309*4fadcaf0SPatrice Chotard 310*4fadcaf0SPatrice Chotard cr2 &= ~STM32_I2C_CR2_NBYTES_MASK; 311*4fadcaf0SPatrice Chotard 312*4fadcaf0SPatrice Chotard if (msg->len > STM32_I2C_MAX_LEN) { 313*4fadcaf0SPatrice Chotard cr2 |= STM32_I2C_CR2_NBYTES(STM32_I2C_MAX_LEN); 314*4fadcaf0SPatrice Chotard } else { 315*4fadcaf0SPatrice Chotard cr2 &= ~STM32_I2C_CR2_RELOAD; 316*4fadcaf0SPatrice Chotard cr2 |= STM32_I2C_CR2_NBYTES(msg->len); 317*4fadcaf0SPatrice Chotard } 318*4fadcaf0SPatrice Chotard 319*4fadcaf0SPatrice Chotard writel(cr2, ®s->cr2); 320*4fadcaf0SPatrice Chotard } 321*4fadcaf0SPatrice Chotard 322*4fadcaf0SPatrice Chotard static int stm32_i2c_wait_flags(struct stm32_i2c_priv *i2c_priv, 323*4fadcaf0SPatrice Chotard u32 flags, u32 *status) 324*4fadcaf0SPatrice Chotard { 325*4fadcaf0SPatrice Chotard struct stm32_i2c_regs *regs = i2c_priv->regs; 326*4fadcaf0SPatrice Chotard u32 time_start = get_timer(0); 327*4fadcaf0SPatrice Chotard 328*4fadcaf0SPatrice Chotard *status = readl(®s->isr); 329*4fadcaf0SPatrice Chotard while (!(*status & flags)) { 330*4fadcaf0SPatrice Chotard if (get_timer(time_start) > CONFIG_SYS_HZ) { 331*4fadcaf0SPatrice Chotard debug("%s: i2c timeout\n", __func__); 332*4fadcaf0SPatrice Chotard return -ETIMEDOUT; 333*4fadcaf0SPatrice Chotard } 334*4fadcaf0SPatrice Chotard 335*4fadcaf0SPatrice Chotard *status = readl(®s->isr); 336*4fadcaf0SPatrice Chotard } 337*4fadcaf0SPatrice Chotard 338*4fadcaf0SPatrice Chotard return 0; 339*4fadcaf0SPatrice Chotard } 340*4fadcaf0SPatrice Chotard 341*4fadcaf0SPatrice Chotard static int stm32_i2c_check_end_of_message(struct stm32_i2c_priv *i2c_priv) 342*4fadcaf0SPatrice Chotard { 343*4fadcaf0SPatrice Chotard struct stm32_i2c_regs *regs = i2c_priv->regs; 344*4fadcaf0SPatrice Chotard u32 mask = STM32_I2C_ISR_ERRORS | STM32_I2C_ISR_NACKF | 345*4fadcaf0SPatrice Chotard STM32_I2C_ISR_STOPF; 346*4fadcaf0SPatrice Chotard u32 status; 347*4fadcaf0SPatrice Chotard int ret; 348*4fadcaf0SPatrice Chotard 349*4fadcaf0SPatrice Chotard ret = stm32_i2c_wait_flags(i2c_priv, mask, &status); 350*4fadcaf0SPatrice Chotard if (ret) 351*4fadcaf0SPatrice Chotard return ret; 352*4fadcaf0SPatrice Chotard 353*4fadcaf0SPatrice Chotard if (status & STM32_I2C_ISR_BERR) { 354*4fadcaf0SPatrice Chotard debug("%s: Bus error\n", __func__); 355*4fadcaf0SPatrice Chotard 356*4fadcaf0SPatrice Chotard /* Clear BERR flag */ 357*4fadcaf0SPatrice Chotard setbits_le32(®s->icr, STM32_I2C_ICR_BERRCF); 358*4fadcaf0SPatrice Chotard 359*4fadcaf0SPatrice Chotard return -EIO; 360*4fadcaf0SPatrice Chotard } 361*4fadcaf0SPatrice Chotard 362*4fadcaf0SPatrice Chotard if (status & STM32_I2C_ISR_ARLO) { 363*4fadcaf0SPatrice Chotard debug("%s: Arbitration lost\n", __func__); 364*4fadcaf0SPatrice Chotard 365*4fadcaf0SPatrice Chotard /* Clear ARLO flag */ 366*4fadcaf0SPatrice Chotard setbits_le32(®s->icr, STM32_I2C_ICR_ARLOCF); 367*4fadcaf0SPatrice Chotard 368*4fadcaf0SPatrice Chotard return -EAGAIN; 369*4fadcaf0SPatrice Chotard } 370*4fadcaf0SPatrice Chotard 371*4fadcaf0SPatrice Chotard if (status & STM32_I2C_ISR_NACKF) { 372*4fadcaf0SPatrice Chotard debug("%s: Receive NACK\n", __func__); 373*4fadcaf0SPatrice Chotard 374*4fadcaf0SPatrice Chotard /* Clear NACK flag */ 375*4fadcaf0SPatrice Chotard setbits_le32(®s->icr, STM32_I2C_ICR_NACKCF); 376*4fadcaf0SPatrice Chotard 377*4fadcaf0SPatrice Chotard /* Wait until STOPF flag is set */ 378*4fadcaf0SPatrice Chotard mask = STM32_I2C_ISR_STOPF; 379*4fadcaf0SPatrice Chotard ret = stm32_i2c_wait_flags(i2c_priv, mask, &status); 380*4fadcaf0SPatrice Chotard if (ret) 381*4fadcaf0SPatrice Chotard return ret; 382*4fadcaf0SPatrice Chotard 383*4fadcaf0SPatrice Chotard ret = -EIO; 384*4fadcaf0SPatrice Chotard } 385*4fadcaf0SPatrice Chotard 386*4fadcaf0SPatrice Chotard if (status & STM32_I2C_ISR_STOPF) { 387*4fadcaf0SPatrice Chotard /* Clear STOP flag */ 388*4fadcaf0SPatrice Chotard setbits_le32(®s->icr, STM32_I2C_ICR_STOPCF); 389*4fadcaf0SPatrice Chotard 390*4fadcaf0SPatrice Chotard /* Clear control register 2 */ 391*4fadcaf0SPatrice Chotard setbits_le32(®s->cr2, STM32_I2C_CR2_RESET_MASK); 392*4fadcaf0SPatrice Chotard } 393*4fadcaf0SPatrice Chotard 394*4fadcaf0SPatrice Chotard return ret; 395*4fadcaf0SPatrice Chotard } 396*4fadcaf0SPatrice Chotard 397*4fadcaf0SPatrice Chotard static int stm32_i2c_message_xfer(struct stm32_i2c_priv *i2c_priv, 398*4fadcaf0SPatrice Chotard struct i2c_msg *msg, bool stop) 399*4fadcaf0SPatrice Chotard { 400*4fadcaf0SPatrice Chotard struct stm32_i2c_regs *regs = i2c_priv->regs; 401*4fadcaf0SPatrice Chotard u32 status; 402*4fadcaf0SPatrice Chotard u32 mask = msg->flags & I2C_M_RD ? STM32_I2C_ISR_RXNE : 403*4fadcaf0SPatrice Chotard STM32_I2C_ISR_TXIS | STM32_I2C_ISR_NACKF; 404*4fadcaf0SPatrice Chotard int bytes_to_rw = msg->len > STM32_I2C_MAX_LEN ? 405*4fadcaf0SPatrice Chotard STM32_I2C_MAX_LEN : msg->len; 406*4fadcaf0SPatrice Chotard int ret = 0; 407*4fadcaf0SPatrice Chotard 408*4fadcaf0SPatrice Chotard /* Add errors */ 409*4fadcaf0SPatrice Chotard mask |= STM32_I2C_ISR_ERRORS; 410*4fadcaf0SPatrice Chotard 411*4fadcaf0SPatrice Chotard stm32_i2c_message_start(i2c_priv, msg, stop); 412*4fadcaf0SPatrice Chotard 413*4fadcaf0SPatrice Chotard while (msg->len) { 414*4fadcaf0SPatrice Chotard /* 415*4fadcaf0SPatrice Chotard * Wait until TXIS/NACKF/BERR/ARLO flags or 416*4fadcaf0SPatrice Chotard * RXNE/BERR/ARLO flags are set 417*4fadcaf0SPatrice Chotard */ 418*4fadcaf0SPatrice Chotard ret = stm32_i2c_wait_flags(i2c_priv, mask, &status); 419*4fadcaf0SPatrice Chotard if (ret) 420*4fadcaf0SPatrice Chotard break; 421*4fadcaf0SPatrice Chotard 422*4fadcaf0SPatrice Chotard if (status & (STM32_I2C_ISR_NACKF | STM32_I2C_ISR_ERRORS)) 423*4fadcaf0SPatrice Chotard break; 424*4fadcaf0SPatrice Chotard 425*4fadcaf0SPatrice Chotard if (status & STM32_I2C_ISR_RXNE) { 426*4fadcaf0SPatrice Chotard *msg->buf++ = readb(®s->rxdr); 427*4fadcaf0SPatrice Chotard msg->len--; 428*4fadcaf0SPatrice Chotard bytes_to_rw--; 429*4fadcaf0SPatrice Chotard } 430*4fadcaf0SPatrice Chotard 431*4fadcaf0SPatrice Chotard if (status & STM32_I2C_ISR_TXIS) { 432*4fadcaf0SPatrice Chotard writeb(*msg->buf++, ®s->txdr); 433*4fadcaf0SPatrice Chotard msg->len--; 434*4fadcaf0SPatrice Chotard bytes_to_rw--; 435*4fadcaf0SPatrice Chotard } 436*4fadcaf0SPatrice Chotard 437*4fadcaf0SPatrice Chotard if (!bytes_to_rw && msg->len) { 438*4fadcaf0SPatrice Chotard /* Wait until TCR flag is set */ 439*4fadcaf0SPatrice Chotard mask = STM32_I2C_ISR_TCR; 440*4fadcaf0SPatrice Chotard ret = stm32_i2c_wait_flags(i2c_priv, mask, &status); 441*4fadcaf0SPatrice Chotard if (ret) 442*4fadcaf0SPatrice Chotard break; 443*4fadcaf0SPatrice Chotard 444*4fadcaf0SPatrice Chotard bytes_to_rw = msg->len > STM32_I2C_MAX_LEN ? 445*4fadcaf0SPatrice Chotard STM32_I2C_MAX_LEN : msg->len; 446*4fadcaf0SPatrice Chotard mask = msg->flags & I2C_M_RD ? STM32_I2C_ISR_RXNE : 447*4fadcaf0SPatrice Chotard STM32_I2C_ISR_TXIS | STM32_I2C_ISR_NACKF; 448*4fadcaf0SPatrice Chotard 449*4fadcaf0SPatrice Chotard stm32_i2c_handle_reload(i2c_priv, msg, stop); 450*4fadcaf0SPatrice Chotard } else if (!bytes_to_rw) { 451*4fadcaf0SPatrice Chotard /* Wait until TC flag is set */ 452*4fadcaf0SPatrice Chotard mask = STM32_I2C_ISR_TC; 453*4fadcaf0SPatrice Chotard ret = stm32_i2c_wait_flags(i2c_priv, mask, &status); 454*4fadcaf0SPatrice Chotard if (ret) 455*4fadcaf0SPatrice Chotard break; 456*4fadcaf0SPatrice Chotard 457*4fadcaf0SPatrice Chotard if (!stop) 458*4fadcaf0SPatrice Chotard /* Message sent, new message has to be sent */ 459*4fadcaf0SPatrice Chotard return 0; 460*4fadcaf0SPatrice Chotard } 461*4fadcaf0SPatrice Chotard } 462*4fadcaf0SPatrice Chotard 463*4fadcaf0SPatrice Chotard /* End of transfer, send stop condition */ 464*4fadcaf0SPatrice Chotard mask = STM32_I2C_CR2_STOP; 465*4fadcaf0SPatrice Chotard setbits_le32(®s->cr2, mask); 466*4fadcaf0SPatrice Chotard 467*4fadcaf0SPatrice Chotard return stm32_i2c_check_end_of_message(i2c_priv); 468*4fadcaf0SPatrice Chotard } 469*4fadcaf0SPatrice Chotard 470*4fadcaf0SPatrice Chotard static int stm32_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, 471*4fadcaf0SPatrice Chotard int nmsgs) 472*4fadcaf0SPatrice Chotard { 473*4fadcaf0SPatrice Chotard struct stm32_i2c_priv *i2c_priv = dev_get_priv(bus); 474*4fadcaf0SPatrice Chotard int ret; 475*4fadcaf0SPatrice Chotard 476*4fadcaf0SPatrice Chotard ret = stm32_i2c_check_device_busy(i2c_priv); 477*4fadcaf0SPatrice Chotard if (ret) 478*4fadcaf0SPatrice Chotard return ret; 479*4fadcaf0SPatrice Chotard 480*4fadcaf0SPatrice Chotard for (; nmsgs > 0; nmsgs--, msg++) { 481*4fadcaf0SPatrice Chotard ret = stm32_i2c_message_xfer(i2c_priv, msg, nmsgs == 1); 482*4fadcaf0SPatrice Chotard if (ret) 483*4fadcaf0SPatrice Chotard return ret; 484*4fadcaf0SPatrice Chotard } 485*4fadcaf0SPatrice Chotard 486*4fadcaf0SPatrice Chotard return 0; 487*4fadcaf0SPatrice Chotard } 488*4fadcaf0SPatrice Chotard 489*4fadcaf0SPatrice Chotard static int stm32_i2c_compute_solutions(struct stm32_i2c_setup *setup, 490*4fadcaf0SPatrice Chotard struct list_head *solutions) 491*4fadcaf0SPatrice Chotard { 492*4fadcaf0SPatrice Chotard struct stm32_i2c_timings *v; 493*4fadcaf0SPatrice Chotard u32 p_prev = STM32_PRESC_MAX; 494*4fadcaf0SPatrice Chotard u32 i2cclk = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC, 495*4fadcaf0SPatrice Chotard setup->clock_src); 496*4fadcaf0SPatrice Chotard u32 af_delay_min, af_delay_max; 497*4fadcaf0SPatrice Chotard u16 p, l, a; 498*4fadcaf0SPatrice Chotard int sdadel_min, sdadel_max, scldel_min; 499*4fadcaf0SPatrice Chotard int ret = 0; 500*4fadcaf0SPatrice Chotard 501*4fadcaf0SPatrice Chotard af_delay_min = setup->analog_filter ? 502*4fadcaf0SPatrice Chotard STM32_I2C_ANALOG_FILTER_DELAY_MIN : 0; 503*4fadcaf0SPatrice Chotard af_delay_max = setup->analog_filter ? 504*4fadcaf0SPatrice Chotard STM32_I2C_ANALOG_FILTER_DELAY_MAX : 0; 505*4fadcaf0SPatrice Chotard 506*4fadcaf0SPatrice Chotard sdadel_min = setup->fall_time - i2c_specs[setup->speed].hddat_min - 507*4fadcaf0SPatrice Chotard af_delay_min - (setup->dnf + 3) * i2cclk; 508*4fadcaf0SPatrice Chotard 509*4fadcaf0SPatrice Chotard sdadel_max = i2c_specs[setup->speed].vddat_max - setup->rise_time - 510*4fadcaf0SPatrice Chotard af_delay_max - (setup->dnf + 4) * i2cclk; 511*4fadcaf0SPatrice Chotard 512*4fadcaf0SPatrice Chotard scldel_min = setup->rise_time + i2c_specs[setup->speed].sudat_min; 513*4fadcaf0SPatrice Chotard 514*4fadcaf0SPatrice Chotard if (sdadel_min < 0) 515*4fadcaf0SPatrice Chotard sdadel_min = 0; 516*4fadcaf0SPatrice Chotard if (sdadel_max < 0) 517*4fadcaf0SPatrice Chotard sdadel_max = 0; 518*4fadcaf0SPatrice Chotard 519*4fadcaf0SPatrice Chotard debug("%s: SDADEL(min/max): %i/%i, SCLDEL(Min): %i\n", __func__, 520*4fadcaf0SPatrice Chotard sdadel_min, sdadel_max, scldel_min); 521*4fadcaf0SPatrice Chotard 522*4fadcaf0SPatrice Chotard /* Compute possible values for PRESC, SCLDEL and SDADEL */ 523*4fadcaf0SPatrice Chotard for (p = 0; p < STM32_PRESC_MAX; p++) { 524*4fadcaf0SPatrice Chotard for (l = 0; l < STM32_SCLDEL_MAX; l++) { 525*4fadcaf0SPatrice Chotard u32 scldel = (l + 1) * (p + 1) * i2cclk; 526*4fadcaf0SPatrice Chotard 527*4fadcaf0SPatrice Chotard if (scldel < scldel_min) 528*4fadcaf0SPatrice Chotard continue; 529*4fadcaf0SPatrice Chotard 530*4fadcaf0SPatrice Chotard for (a = 0; a < STM32_SDADEL_MAX; a++) { 531*4fadcaf0SPatrice Chotard u32 sdadel = (a * (p + 1) + 1) * i2cclk; 532*4fadcaf0SPatrice Chotard 533*4fadcaf0SPatrice Chotard if (((sdadel >= sdadel_min) && 534*4fadcaf0SPatrice Chotard (sdadel <= sdadel_max)) && 535*4fadcaf0SPatrice Chotard (p != p_prev)) { 536*4fadcaf0SPatrice Chotard v = kmalloc(sizeof(*v), GFP_KERNEL); 537*4fadcaf0SPatrice Chotard if (!v) 538*4fadcaf0SPatrice Chotard return -ENOMEM; 539*4fadcaf0SPatrice Chotard 540*4fadcaf0SPatrice Chotard v->presc = p; 541*4fadcaf0SPatrice Chotard v->scldel = l; 542*4fadcaf0SPatrice Chotard v->sdadel = a; 543*4fadcaf0SPatrice Chotard p_prev = p; 544*4fadcaf0SPatrice Chotard 545*4fadcaf0SPatrice Chotard list_add_tail(&v->node, solutions); 546*4fadcaf0SPatrice Chotard } 547*4fadcaf0SPatrice Chotard } 548*4fadcaf0SPatrice Chotard } 549*4fadcaf0SPatrice Chotard } 550*4fadcaf0SPatrice Chotard 551*4fadcaf0SPatrice Chotard if (list_empty(solutions)) { 552*4fadcaf0SPatrice Chotard error("%s: no Prescaler solution\n", __func__); 553*4fadcaf0SPatrice Chotard ret = -EPERM; 554*4fadcaf0SPatrice Chotard } 555*4fadcaf0SPatrice Chotard 556*4fadcaf0SPatrice Chotard return ret; 557*4fadcaf0SPatrice Chotard } 558*4fadcaf0SPatrice Chotard 559*4fadcaf0SPatrice Chotard static int stm32_i2c_choose_solution(struct stm32_i2c_setup *setup, 560*4fadcaf0SPatrice Chotard struct list_head *solutions, 561*4fadcaf0SPatrice Chotard struct stm32_i2c_timings *s) 562*4fadcaf0SPatrice Chotard { 563*4fadcaf0SPatrice Chotard struct stm32_i2c_timings *v; 564*4fadcaf0SPatrice Chotard u32 i2cbus = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC, 565*4fadcaf0SPatrice Chotard setup->speed_freq); 566*4fadcaf0SPatrice Chotard u32 clk_error_prev = i2cbus; 567*4fadcaf0SPatrice Chotard u32 i2cclk = DIV_ROUND_CLOSEST(STM32_NSEC_PER_SEC, 568*4fadcaf0SPatrice Chotard setup->clock_src); 569*4fadcaf0SPatrice Chotard u32 clk_min, clk_max; 570*4fadcaf0SPatrice Chotard u32 af_delay_min; 571*4fadcaf0SPatrice Chotard u32 dnf_delay; 572*4fadcaf0SPatrice Chotard u32 tsync; 573*4fadcaf0SPatrice Chotard u16 l, h; 574*4fadcaf0SPatrice Chotard int ret = 0; 575*4fadcaf0SPatrice Chotard 576*4fadcaf0SPatrice Chotard af_delay_min = setup->analog_filter ? 577*4fadcaf0SPatrice Chotard STM32_I2C_ANALOG_FILTER_DELAY_MIN : 0; 578*4fadcaf0SPatrice Chotard dnf_delay = setup->dnf * i2cclk; 579*4fadcaf0SPatrice Chotard 580*4fadcaf0SPatrice Chotard tsync = af_delay_min + dnf_delay + (2 * i2cclk); 581*4fadcaf0SPatrice Chotard clk_max = STM32_NSEC_PER_SEC / i2c_specs[setup->speed].rate_min; 582*4fadcaf0SPatrice Chotard clk_min = STM32_NSEC_PER_SEC / i2c_specs[setup->speed].rate_max; 583*4fadcaf0SPatrice Chotard 584*4fadcaf0SPatrice Chotard /* 585*4fadcaf0SPatrice Chotard * Among Prescaler possibilities discovered above figures out SCL Low 586*4fadcaf0SPatrice Chotard * and High Period. Provided: 587*4fadcaf0SPatrice Chotard * - SCL Low Period has to be higher than Low Period of the SCL Clock 588*4fadcaf0SPatrice Chotard * defined by I2C Specification. I2C Clock has to be lower than 589*4fadcaf0SPatrice Chotard * (SCL Low Period - Analog/Digital filters) / 4. 590*4fadcaf0SPatrice Chotard * - SCL High Period has to be lower than High Period of the SCL Clock 591*4fadcaf0SPatrice Chotard * defined by I2C Specification 592*4fadcaf0SPatrice Chotard * - I2C Clock has to be lower than SCL High Period 593*4fadcaf0SPatrice Chotard */ 594*4fadcaf0SPatrice Chotard list_for_each_entry(v, solutions, node) { 595*4fadcaf0SPatrice Chotard u32 prescaler = (v->presc + 1) * i2cclk; 596*4fadcaf0SPatrice Chotard 597*4fadcaf0SPatrice Chotard for (l = 0; l < STM32_SCLL_MAX; l++) { 598*4fadcaf0SPatrice Chotard u32 tscl_l = (l + 1) * prescaler + tsync; 599*4fadcaf0SPatrice Chotard if ((tscl_l < i2c_specs[setup->speed].l_min) || 600*4fadcaf0SPatrice Chotard (i2cclk >= 601*4fadcaf0SPatrice Chotard ((tscl_l - af_delay_min - dnf_delay) / 4))) { 602*4fadcaf0SPatrice Chotard continue; 603*4fadcaf0SPatrice Chotard } 604*4fadcaf0SPatrice Chotard 605*4fadcaf0SPatrice Chotard for (h = 0; h < STM32_SCLH_MAX; h++) { 606*4fadcaf0SPatrice Chotard u32 tscl_h = (h + 1) * prescaler + tsync; 607*4fadcaf0SPatrice Chotard u32 tscl = tscl_l + tscl_h + 608*4fadcaf0SPatrice Chotard setup->rise_time + setup->fall_time; 609*4fadcaf0SPatrice Chotard 610*4fadcaf0SPatrice Chotard if ((tscl >= clk_min) && (tscl <= clk_max) && 611*4fadcaf0SPatrice Chotard (tscl_h >= i2c_specs[setup->speed].h_min) && 612*4fadcaf0SPatrice Chotard (i2cclk < tscl_h)) { 613*4fadcaf0SPatrice Chotard int clk_error = tscl - i2cbus; 614*4fadcaf0SPatrice Chotard 615*4fadcaf0SPatrice Chotard if (clk_error < 0) 616*4fadcaf0SPatrice Chotard clk_error = -clk_error; 617*4fadcaf0SPatrice Chotard 618*4fadcaf0SPatrice Chotard if (clk_error < clk_error_prev) { 619*4fadcaf0SPatrice Chotard clk_error_prev = clk_error; 620*4fadcaf0SPatrice Chotard v->scll = l; 621*4fadcaf0SPatrice Chotard v->sclh = h; 622*4fadcaf0SPatrice Chotard s = v; 623*4fadcaf0SPatrice Chotard } 624*4fadcaf0SPatrice Chotard } 625*4fadcaf0SPatrice Chotard } 626*4fadcaf0SPatrice Chotard } 627*4fadcaf0SPatrice Chotard } 628*4fadcaf0SPatrice Chotard 629*4fadcaf0SPatrice Chotard if (!s) { 630*4fadcaf0SPatrice Chotard error("%s: no solution at all\n", __func__); 631*4fadcaf0SPatrice Chotard ret = -EPERM; 632*4fadcaf0SPatrice Chotard } 633*4fadcaf0SPatrice Chotard 634*4fadcaf0SPatrice Chotard return ret; 635*4fadcaf0SPatrice Chotard } 636*4fadcaf0SPatrice Chotard 637*4fadcaf0SPatrice Chotard static int stm32_i2c_compute_timing(struct stm32_i2c_priv *i2c_priv, 638*4fadcaf0SPatrice Chotard struct stm32_i2c_setup *setup, 639*4fadcaf0SPatrice Chotard struct stm32_i2c_timings *output) 640*4fadcaf0SPatrice Chotard { 641*4fadcaf0SPatrice Chotard struct stm32_i2c_timings *v, *_v, *s; 642*4fadcaf0SPatrice Chotard struct list_head solutions; 643*4fadcaf0SPatrice Chotard int ret; 644*4fadcaf0SPatrice Chotard 645*4fadcaf0SPatrice Chotard if (setup->speed >= STM32_I2C_SPEED_END) { 646*4fadcaf0SPatrice Chotard error("%s: speed out of bound {%d/%d}\n", __func__, 647*4fadcaf0SPatrice Chotard setup->speed, STM32_I2C_SPEED_END - 1); 648*4fadcaf0SPatrice Chotard return -EINVAL; 649*4fadcaf0SPatrice Chotard } 650*4fadcaf0SPatrice Chotard 651*4fadcaf0SPatrice Chotard if ((setup->rise_time > i2c_specs[setup->speed].rise_max) || 652*4fadcaf0SPatrice Chotard (setup->fall_time > i2c_specs[setup->speed].fall_max)) { 653*4fadcaf0SPatrice Chotard error("%s :timings out of bound Rise{%d>%d}/Fall{%d>%d}\n", 654*4fadcaf0SPatrice Chotard __func__, 655*4fadcaf0SPatrice Chotard setup->rise_time, i2c_specs[setup->speed].rise_max, 656*4fadcaf0SPatrice Chotard setup->fall_time, i2c_specs[setup->speed].fall_max); 657*4fadcaf0SPatrice Chotard return -EINVAL; 658*4fadcaf0SPatrice Chotard } 659*4fadcaf0SPatrice Chotard 660*4fadcaf0SPatrice Chotard if (setup->dnf > STM32_I2C_DNF_MAX) { 661*4fadcaf0SPatrice Chotard error("%s: DNF out of bound %d/%d\n", __func__, 662*4fadcaf0SPatrice Chotard setup->dnf, STM32_I2C_DNF_MAX); 663*4fadcaf0SPatrice Chotard return -EINVAL; 664*4fadcaf0SPatrice Chotard } 665*4fadcaf0SPatrice Chotard 666*4fadcaf0SPatrice Chotard if (setup->speed_freq > i2c_specs[setup->speed].rate) { 667*4fadcaf0SPatrice Chotard error("%s: Freq {%d/%d}\n", __func__, 668*4fadcaf0SPatrice Chotard setup->speed_freq, i2c_specs[setup->speed].rate); 669*4fadcaf0SPatrice Chotard return -EINVAL; 670*4fadcaf0SPatrice Chotard } 671*4fadcaf0SPatrice Chotard 672*4fadcaf0SPatrice Chotard s = NULL; 673*4fadcaf0SPatrice Chotard INIT_LIST_HEAD(&solutions); 674*4fadcaf0SPatrice Chotard ret = stm32_i2c_compute_solutions(setup, &solutions); 675*4fadcaf0SPatrice Chotard if (ret) 676*4fadcaf0SPatrice Chotard goto exit; 677*4fadcaf0SPatrice Chotard 678*4fadcaf0SPatrice Chotard ret = stm32_i2c_choose_solution(setup, &solutions, s); 679*4fadcaf0SPatrice Chotard if (ret) 680*4fadcaf0SPatrice Chotard goto exit; 681*4fadcaf0SPatrice Chotard 682*4fadcaf0SPatrice Chotard output->presc = s->presc; 683*4fadcaf0SPatrice Chotard output->scldel = s->scldel; 684*4fadcaf0SPatrice Chotard output->sdadel = s->sdadel; 685*4fadcaf0SPatrice Chotard output->scll = s->scll; 686*4fadcaf0SPatrice Chotard output->sclh = s->sclh; 687*4fadcaf0SPatrice Chotard 688*4fadcaf0SPatrice Chotard debug("%s: Presc: %i, scldel: %i, sdadel: %i, scll: %i, sclh: %i\n", 689*4fadcaf0SPatrice Chotard __func__, output->presc, 690*4fadcaf0SPatrice Chotard output->scldel, output->sdadel, 691*4fadcaf0SPatrice Chotard output->scll, output->sclh); 692*4fadcaf0SPatrice Chotard 693*4fadcaf0SPatrice Chotard exit: 694*4fadcaf0SPatrice Chotard /* Release list and memory */ 695*4fadcaf0SPatrice Chotard list_for_each_entry_safe(v, _v, &solutions, node) { 696*4fadcaf0SPatrice Chotard list_del(&v->node); 697*4fadcaf0SPatrice Chotard kfree(v); 698*4fadcaf0SPatrice Chotard } 699*4fadcaf0SPatrice Chotard 700*4fadcaf0SPatrice Chotard return ret; 701*4fadcaf0SPatrice Chotard } 702*4fadcaf0SPatrice Chotard 703*4fadcaf0SPatrice Chotard static int stm32_i2c_setup_timing(struct stm32_i2c_priv *i2c_priv, 704*4fadcaf0SPatrice Chotard struct stm32_i2c_timings *timing) 705*4fadcaf0SPatrice Chotard { 706*4fadcaf0SPatrice Chotard struct stm32_i2c_setup *setup = i2c_priv->setup; 707*4fadcaf0SPatrice Chotard int ret = 0; 708*4fadcaf0SPatrice Chotard 709*4fadcaf0SPatrice Chotard setup->speed = i2c_priv->speed; 710*4fadcaf0SPatrice Chotard setup->speed_freq = i2c_specs[setup->speed].rate; 711*4fadcaf0SPatrice Chotard setup->clock_src = clk_get_rate(&i2c_priv->clk); 712*4fadcaf0SPatrice Chotard 713*4fadcaf0SPatrice Chotard if (!setup->clock_src) { 714*4fadcaf0SPatrice Chotard error("%s: clock rate is 0\n", __func__); 715*4fadcaf0SPatrice Chotard return -EINVAL; 716*4fadcaf0SPatrice Chotard } 717*4fadcaf0SPatrice Chotard 718*4fadcaf0SPatrice Chotard do { 719*4fadcaf0SPatrice Chotard ret = stm32_i2c_compute_timing(i2c_priv, setup, timing); 720*4fadcaf0SPatrice Chotard if (ret) { 721*4fadcaf0SPatrice Chotard debug("%s: failed to compute I2C timings.\n", 722*4fadcaf0SPatrice Chotard __func__); 723*4fadcaf0SPatrice Chotard if (i2c_priv->speed > STM32_I2C_SPEED_STANDARD) { 724*4fadcaf0SPatrice Chotard i2c_priv->speed--; 725*4fadcaf0SPatrice Chotard setup->speed = i2c_priv->speed; 726*4fadcaf0SPatrice Chotard setup->speed_freq = 727*4fadcaf0SPatrice Chotard i2c_specs[setup->speed].rate; 728*4fadcaf0SPatrice Chotard debug("%s: downgrade I2C Speed Freq to (%i)\n", 729*4fadcaf0SPatrice Chotard __func__, i2c_specs[setup->speed].rate); 730*4fadcaf0SPatrice Chotard } else { 731*4fadcaf0SPatrice Chotard break; 732*4fadcaf0SPatrice Chotard } 733*4fadcaf0SPatrice Chotard } 734*4fadcaf0SPatrice Chotard } while (ret); 735*4fadcaf0SPatrice Chotard 736*4fadcaf0SPatrice Chotard if (ret) { 737*4fadcaf0SPatrice Chotard error("%s: impossible to compute I2C timings.\n", __func__); 738*4fadcaf0SPatrice Chotard return ret; 739*4fadcaf0SPatrice Chotard } 740*4fadcaf0SPatrice Chotard 741*4fadcaf0SPatrice Chotard debug("%s: I2C Speed(%i), Freq(%i), Clk Source(%i)\n", __func__, 742*4fadcaf0SPatrice Chotard setup->speed, setup->speed_freq, setup->clock_src); 743*4fadcaf0SPatrice Chotard debug("%s: I2C Rise(%i) and Fall(%i) Time\n", __func__, 744*4fadcaf0SPatrice Chotard setup->rise_time, setup->fall_time); 745*4fadcaf0SPatrice Chotard debug("%s: I2C Analog Filter(%s), DNF(%i)\n", __func__, 746*4fadcaf0SPatrice Chotard setup->analog_filter ? "On" : "Off", setup->dnf); 747*4fadcaf0SPatrice Chotard 748*4fadcaf0SPatrice Chotard return 0; 749*4fadcaf0SPatrice Chotard } 750*4fadcaf0SPatrice Chotard 751*4fadcaf0SPatrice Chotard static int stm32_i2c_hw_config(struct stm32_i2c_priv *i2c_priv) 752*4fadcaf0SPatrice Chotard { 753*4fadcaf0SPatrice Chotard struct stm32_i2c_regs *regs = i2c_priv->regs; 754*4fadcaf0SPatrice Chotard struct stm32_i2c_timings t; 755*4fadcaf0SPatrice Chotard int ret; 756*4fadcaf0SPatrice Chotard u32 timing = 0; 757*4fadcaf0SPatrice Chotard 758*4fadcaf0SPatrice Chotard ret = stm32_i2c_setup_timing(i2c_priv, &t); 759*4fadcaf0SPatrice Chotard if (ret) 760*4fadcaf0SPatrice Chotard return ret; 761*4fadcaf0SPatrice Chotard 762*4fadcaf0SPatrice Chotard /* Disable I2C */ 763*4fadcaf0SPatrice Chotard clrbits_le32(®s->cr1, STM32_I2C_CR1_PE); 764*4fadcaf0SPatrice Chotard 765*4fadcaf0SPatrice Chotard /* Timing settings */ 766*4fadcaf0SPatrice Chotard timing |= STM32_I2C_TIMINGR_PRESC(t.presc); 767*4fadcaf0SPatrice Chotard timing |= STM32_I2C_TIMINGR_SCLDEL(t.scldel); 768*4fadcaf0SPatrice Chotard timing |= STM32_I2C_TIMINGR_SDADEL(t.sdadel); 769*4fadcaf0SPatrice Chotard timing |= STM32_I2C_TIMINGR_SCLH(t.sclh); 770*4fadcaf0SPatrice Chotard timing |= STM32_I2C_TIMINGR_SCLL(t.scll); 771*4fadcaf0SPatrice Chotard writel(timing, ®s->timingr); 772*4fadcaf0SPatrice Chotard 773*4fadcaf0SPatrice Chotard /* Enable I2C */ 774*4fadcaf0SPatrice Chotard if (i2c_priv->setup->analog_filter) 775*4fadcaf0SPatrice Chotard clrbits_le32(®s->cr1, STM32_I2C_CR1_ANFOFF); 776*4fadcaf0SPatrice Chotard else 777*4fadcaf0SPatrice Chotard setbits_le32(®s->cr1, STM32_I2C_CR1_ANFOFF); 778*4fadcaf0SPatrice Chotard setbits_le32(®s->cr1, STM32_I2C_CR1_PE); 779*4fadcaf0SPatrice Chotard 780*4fadcaf0SPatrice Chotard return 0; 781*4fadcaf0SPatrice Chotard } 782*4fadcaf0SPatrice Chotard 783*4fadcaf0SPatrice Chotard static int stm32_i2c_set_bus_speed(struct udevice *bus, unsigned int speed) 784*4fadcaf0SPatrice Chotard { 785*4fadcaf0SPatrice Chotard struct stm32_i2c_priv *i2c_priv = dev_get_priv(bus); 786*4fadcaf0SPatrice Chotard 787*4fadcaf0SPatrice Chotard switch (speed) { 788*4fadcaf0SPatrice Chotard case STANDARD_RATE: 789*4fadcaf0SPatrice Chotard i2c_priv->speed = STM32_I2C_SPEED_STANDARD; 790*4fadcaf0SPatrice Chotard break; 791*4fadcaf0SPatrice Chotard case FAST_RATE: 792*4fadcaf0SPatrice Chotard i2c_priv->speed = STM32_I2C_SPEED_FAST; 793*4fadcaf0SPatrice Chotard break; 794*4fadcaf0SPatrice Chotard case FAST_PLUS_RATE: 795*4fadcaf0SPatrice Chotard i2c_priv->speed = STM32_I2C_SPEED_FAST_PLUS; 796*4fadcaf0SPatrice Chotard break; 797*4fadcaf0SPatrice Chotard default: 798*4fadcaf0SPatrice Chotard debug("%s: Speed %d not supported\n", __func__, speed); 799*4fadcaf0SPatrice Chotard return -EINVAL; 800*4fadcaf0SPatrice Chotard } 801*4fadcaf0SPatrice Chotard 802*4fadcaf0SPatrice Chotard return stm32_i2c_hw_config(i2c_priv); 803*4fadcaf0SPatrice Chotard } 804*4fadcaf0SPatrice Chotard 805*4fadcaf0SPatrice Chotard static int stm32_i2c_probe(struct udevice *dev) 806*4fadcaf0SPatrice Chotard { 807*4fadcaf0SPatrice Chotard struct stm32_i2c_priv *i2c_priv = dev_get_priv(dev); 808*4fadcaf0SPatrice Chotard struct reset_ctl reset_ctl; 809*4fadcaf0SPatrice Chotard fdt_addr_t addr; 810*4fadcaf0SPatrice Chotard int ret; 811*4fadcaf0SPatrice Chotard 812*4fadcaf0SPatrice Chotard addr = dev_read_addr(dev); 813*4fadcaf0SPatrice Chotard if (addr == FDT_ADDR_T_NONE) 814*4fadcaf0SPatrice Chotard return -EINVAL; 815*4fadcaf0SPatrice Chotard 816*4fadcaf0SPatrice Chotard i2c_priv->regs = (struct stm32_i2c_regs *)addr; 817*4fadcaf0SPatrice Chotard 818*4fadcaf0SPatrice Chotard ret = clk_get_by_index(dev, 0, &i2c_priv->clk); 819*4fadcaf0SPatrice Chotard if (ret) 820*4fadcaf0SPatrice Chotard return ret; 821*4fadcaf0SPatrice Chotard 822*4fadcaf0SPatrice Chotard ret = clk_enable(&i2c_priv->clk); 823*4fadcaf0SPatrice Chotard if (ret) 824*4fadcaf0SPatrice Chotard goto clk_free; 825*4fadcaf0SPatrice Chotard 826*4fadcaf0SPatrice Chotard ret = reset_get_by_index(dev, 0, &reset_ctl); 827*4fadcaf0SPatrice Chotard if (ret) 828*4fadcaf0SPatrice Chotard goto clk_disable; 829*4fadcaf0SPatrice Chotard 830*4fadcaf0SPatrice Chotard reset_assert(&reset_ctl); 831*4fadcaf0SPatrice Chotard udelay(2); 832*4fadcaf0SPatrice Chotard reset_deassert(&reset_ctl); 833*4fadcaf0SPatrice Chotard 834*4fadcaf0SPatrice Chotard return 0; 835*4fadcaf0SPatrice Chotard 836*4fadcaf0SPatrice Chotard clk_disable: 837*4fadcaf0SPatrice Chotard clk_disable(&i2c_priv->clk); 838*4fadcaf0SPatrice Chotard clk_free: 839*4fadcaf0SPatrice Chotard clk_free(&i2c_priv->clk); 840*4fadcaf0SPatrice Chotard 841*4fadcaf0SPatrice Chotard return ret; 842*4fadcaf0SPatrice Chotard } 843*4fadcaf0SPatrice Chotard 844*4fadcaf0SPatrice Chotard static int stm32_ofdata_to_platdata(struct udevice *dev) 845*4fadcaf0SPatrice Chotard { 846*4fadcaf0SPatrice Chotard struct stm32_i2c_priv *i2c_priv = dev_get_priv(dev); 847*4fadcaf0SPatrice Chotard u32 rise_time, fall_time; 848*4fadcaf0SPatrice Chotard 849*4fadcaf0SPatrice Chotard i2c_priv->setup = (struct stm32_i2c_setup *)dev_get_driver_data(dev); 850*4fadcaf0SPatrice Chotard if (!i2c_priv->setup) 851*4fadcaf0SPatrice Chotard return -EINVAL; 852*4fadcaf0SPatrice Chotard 853*4fadcaf0SPatrice Chotard rise_time = dev_read_u32_default(dev, "i2c-scl-rising-time-ns", 0); 854*4fadcaf0SPatrice Chotard if (rise_time) 855*4fadcaf0SPatrice Chotard i2c_priv->setup->rise_time = rise_time; 856*4fadcaf0SPatrice Chotard 857*4fadcaf0SPatrice Chotard fall_time = dev_read_u32_default(dev, "i2c-scl-falling-time-ns", 0); 858*4fadcaf0SPatrice Chotard if (fall_time) 859*4fadcaf0SPatrice Chotard i2c_priv->setup->fall_time = fall_time; 860*4fadcaf0SPatrice Chotard 861*4fadcaf0SPatrice Chotard return 0; 862*4fadcaf0SPatrice Chotard } 863*4fadcaf0SPatrice Chotard 864*4fadcaf0SPatrice Chotard static const struct dm_i2c_ops stm32_i2c_ops = { 865*4fadcaf0SPatrice Chotard .xfer = stm32_i2c_xfer, 866*4fadcaf0SPatrice Chotard .set_bus_speed = stm32_i2c_set_bus_speed, 867*4fadcaf0SPatrice Chotard }; 868*4fadcaf0SPatrice Chotard 869*4fadcaf0SPatrice Chotard static const struct udevice_id stm32_i2c_of_match[] = { 870*4fadcaf0SPatrice Chotard { .compatible = "st,stm32f7-i2c", .data = (ulong)&stm32f7_setup }, 871*4fadcaf0SPatrice Chotard {} 872*4fadcaf0SPatrice Chotard }; 873*4fadcaf0SPatrice Chotard 874*4fadcaf0SPatrice Chotard U_BOOT_DRIVER(stm32f7_i2c) = { 875*4fadcaf0SPatrice Chotard .name = "stm32f7-i2c", 876*4fadcaf0SPatrice Chotard .id = UCLASS_I2C, 877*4fadcaf0SPatrice Chotard .of_match = stm32_i2c_of_match, 878*4fadcaf0SPatrice Chotard .ofdata_to_platdata = stm32_ofdata_to_platdata, 879*4fadcaf0SPatrice Chotard .probe = stm32_i2c_probe, 880*4fadcaf0SPatrice Chotard .priv_auto_alloc_size = sizeof(struct stm32_i2c_priv), 881*4fadcaf0SPatrice Chotard .ops = &stm32_i2c_ops, 882*4fadcaf0SPatrice Chotard }; 883