1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * Copyright (C) 2011, 2013 Renesas Solutions Corp. 4 * Copyright (C) 2011, 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> 5 * 6 * NOTE: This driver should be converted to driver model before June 2017. 7 * Please see doc/driver-model/i2c-howto.txt for instructions. 8 */ 9 10 #include <common.h> 11 #include <i2c.h> 12 #include <asm/io.h> 13 14 DECLARE_GLOBAL_DATA_PTR; 15 16 /* Every register is 32bit aligned, but only 8bits in size */ 17 #define ureg(name) u8 name; u8 __pad_##name##0; u16 __pad_##name##1; 18 struct sh_i2c { 19 ureg(icdr); 20 ureg(iccr); 21 ureg(icsr); 22 ureg(icic); 23 ureg(iccl); 24 ureg(icch); 25 }; 26 #undef ureg 27 28 /* ICCR */ 29 #define SH_I2C_ICCR_ICE (1 << 7) 30 #define SH_I2C_ICCR_RACK (1 << 6) 31 #define SH_I2C_ICCR_RTS (1 << 4) 32 #define SH_I2C_ICCR_BUSY (1 << 2) 33 #define SH_I2C_ICCR_SCP (1 << 0) 34 35 /* ICSR / ICIC */ 36 #define SH_IC_BUSY (1 << 4) 37 #define SH_IC_TACK (1 << 2) 38 #define SH_IC_WAIT (1 << 1) 39 #define SH_IC_DTE (1 << 0) 40 41 #ifdef CONFIG_SH_I2C_8BIT 42 /* store 8th bit of iccl and icch in ICIC register */ 43 #define SH_I2C_ICIC_ICCLB8 (1 << 7) 44 #define SH_I2C_ICIC_ICCHB8 (1 << 6) 45 #endif 46 47 static const struct sh_i2c *i2c_dev[CONFIG_SYS_I2C_SH_NUM_CONTROLLERS] = { 48 (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE0, 49 #ifdef CONFIG_SYS_I2C_SH_BASE1 50 (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE1, 51 #endif 52 #ifdef CONFIG_SYS_I2C_SH_BASE2 53 (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE2, 54 #endif 55 #ifdef CONFIG_SYS_I2C_SH_BASE3 56 (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE3, 57 #endif 58 #ifdef CONFIG_SYS_I2C_SH_BASE4 59 (struct sh_i2c *)CONFIG_SYS_I2C_SH_BASE4, 60 #endif 61 }; 62 63 static u16 iccl, icch; 64 65 #define IRQ_WAIT 1000 66 67 static void sh_irq_dte(struct sh_i2c *dev) 68 { 69 int i; 70 71 for (i = 0; i < IRQ_WAIT; i++) { 72 if (SH_IC_DTE & readb(&dev->icsr)) 73 break; 74 udelay(10); 75 } 76 } 77 78 static int sh_irq_dte_with_tack(struct sh_i2c *dev) 79 { 80 int i; 81 82 for (i = 0; i < IRQ_WAIT; i++) { 83 if (SH_IC_DTE & readb(&dev->icsr)) 84 break; 85 if (SH_IC_TACK & readb(&dev->icsr)) 86 return -1; 87 udelay(10); 88 } 89 return 0; 90 } 91 92 static void sh_irq_busy(struct sh_i2c *dev) 93 { 94 int i; 95 96 for (i = 0; i < IRQ_WAIT; i++) { 97 if (!(SH_IC_BUSY & readb(&dev->icsr))) 98 break; 99 udelay(10); 100 } 101 } 102 103 static int sh_i2c_set_addr(struct sh_i2c *dev, u8 chip, u8 addr, int stop) 104 { 105 u8 icic = SH_IC_TACK; 106 107 debug("%s: chip: %x, addr: %x iccl: %x, icch %x\n", 108 __func__, chip, addr, iccl, icch); 109 clrbits_8(&dev->iccr, SH_I2C_ICCR_ICE); 110 setbits_8(&dev->iccr, SH_I2C_ICCR_ICE); 111 112 writeb(iccl & 0xff, &dev->iccl); 113 writeb(icch & 0xff, &dev->icch); 114 #ifdef CONFIG_SH_I2C_8BIT 115 if (iccl > 0xff) 116 icic |= SH_I2C_ICIC_ICCLB8; 117 if (icch > 0xff) 118 icic |= SH_I2C_ICIC_ICCHB8; 119 #endif 120 writeb(icic, &dev->icic); 121 122 writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &dev->iccr); 123 sh_irq_dte(dev); 124 125 clrbits_8(&dev->icsr, SH_IC_TACK); 126 writeb(chip << 1, &dev->icdr); 127 if (sh_irq_dte_with_tack(dev) != 0) 128 return -1; 129 130 writeb(addr, &dev->icdr); 131 if (stop) 132 writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS), &dev->iccr); 133 134 if (sh_irq_dte_with_tack(dev) != 0) 135 return -1; 136 return 0; 137 } 138 139 static void sh_i2c_finish(struct sh_i2c *dev) 140 { 141 writeb(0, &dev->icsr); 142 clrbits_8(&dev->iccr, SH_I2C_ICCR_ICE); 143 } 144 145 static int 146 sh_i2c_raw_write(struct sh_i2c *dev, u8 chip, uint addr, u8 val) 147 { 148 int ret = -1; 149 if (sh_i2c_set_addr(dev, chip, addr, 0) != 0) 150 goto exit0; 151 udelay(10); 152 153 writeb(val, &dev->icdr); 154 if (sh_irq_dte_with_tack(dev) != 0) 155 goto exit0; 156 157 writeb((SH_I2C_ICCR_ICE | SH_I2C_ICCR_RTS), &dev->iccr); 158 if (sh_irq_dte_with_tack(dev) != 0) 159 goto exit0; 160 sh_irq_busy(dev); 161 ret = 0; 162 163 exit0: 164 sh_i2c_finish(dev); 165 return ret; 166 } 167 168 static int sh_i2c_raw_read(struct sh_i2c *dev, u8 chip, u8 addr) 169 { 170 int ret = -1; 171 172 #if defined(CONFIG_SH73A0) 173 if (sh_i2c_set_addr(dev, chip, addr, 0) != 0) 174 goto exit0; 175 #else 176 if (sh_i2c_set_addr(dev, chip, addr, 1) != 0) 177 goto exit0; 178 udelay(100); 179 #endif 180 181 writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &dev->iccr); 182 sh_irq_dte(dev); 183 184 writeb(chip << 1 | 0x01, &dev->icdr); 185 if (sh_irq_dte_with_tack(dev) != 0) 186 goto exit0; 187 188 writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_SCP), &dev->iccr); 189 if (sh_irq_dte_with_tack(dev) != 0) 190 goto exit0; 191 192 ret = readb(&dev->icdr) & 0xff; 193 194 writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RACK), &dev->iccr); 195 readb(&dev->icdr); /* Dummy read */ 196 sh_irq_busy(dev); 197 198 exit0: 199 sh_i2c_finish(dev); 200 201 return ret; 202 } 203 204 static void 205 sh_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd) 206 { 207 int num, denom, tmp; 208 209 /* No i2c support prior to relocation */ 210 if (!(gd->flags & GD_FLG_RELOC)) 211 return; 212 213 /* 214 * Calculate the value for iccl. From the data sheet: 215 * iccl = (p-clock / transfer-rate) * (L / (L + H)) 216 * where L and H are the SCL low and high ratio. 217 */ 218 num = CONFIG_SH_I2C_CLOCK * CONFIG_SH_I2C_DATA_LOW; 219 denom = speed * (CONFIG_SH_I2C_DATA_HIGH + CONFIG_SH_I2C_DATA_LOW); 220 tmp = num * 10 / denom; 221 if (tmp % 10 >= 5) 222 iccl = (u16)((num/denom) + 1); 223 else 224 iccl = (u16)(num/denom); 225 226 /* Calculate the value for icch. From the data sheet: 227 icch = (p clock / transfer rate) * (H / (L + H)) */ 228 num = CONFIG_SH_I2C_CLOCK * CONFIG_SH_I2C_DATA_HIGH; 229 tmp = num * 10 / denom; 230 if (tmp % 10 >= 5) 231 icch = (u16)((num/denom) + 1); 232 else 233 icch = (u16)(num/denom); 234 235 debug("clock: %d, speed %d, iccl: %x, icch: %x\n", 236 CONFIG_SH_I2C_CLOCK, speed, iccl, icch); 237 } 238 239 static int sh_i2c_read(struct i2c_adapter *adap, uint8_t chip, 240 uint addr, int alen, u8 *data, int len) 241 { 242 int ret, i; 243 struct sh_i2c *dev = (struct sh_i2c *)i2c_dev[adap->hwadapnr]; 244 245 for (i = 0; i < len; i++) { 246 ret = sh_i2c_raw_read(dev, chip, addr + i); 247 if (ret < 0) 248 return -1; 249 250 data[i] = ret & 0xff; 251 debug("%s: data[%d]: %02x\n", __func__, i, data[i]); 252 } 253 254 return 0; 255 } 256 257 static int sh_i2c_write(struct i2c_adapter *adap, uint8_t chip, uint addr, 258 int alen, u8 *data, int len) 259 { 260 struct sh_i2c *dev = (struct sh_i2c *)i2c_dev[adap->hwadapnr]; 261 int i; 262 263 for (i = 0; i < len; i++) { 264 debug("%s: data[%d]: %02x\n", __func__, i, data[i]); 265 if (sh_i2c_raw_write(dev, chip, addr + i, data[i]) != 0) 266 return -1; 267 } 268 return 0; 269 } 270 271 static int 272 sh_i2c_probe(struct i2c_adapter *adap, u8 dev) 273 { 274 u8 dummy[1]; 275 276 return sh_i2c_read(adap, dev, 0, 0, dummy, sizeof dummy); 277 } 278 279 static unsigned int sh_i2c_set_bus_speed(struct i2c_adapter *adap, 280 unsigned int speed) 281 { 282 struct sh_i2c *dev = (struct sh_i2c *)i2c_dev[adap->hwadapnr]; 283 284 sh_i2c_finish(dev); 285 sh_i2c_init(adap, speed, 0); 286 287 return 0; 288 } 289 290 /* 291 * Register RCAR i2c adapters 292 */ 293 U_BOOT_I2C_ADAP_COMPLETE(sh_0, sh_i2c_init, sh_i2c_probe, sh_i2c_read, 294 sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED0, 0, 0) 295 #ifdef CONFIG_SYS_I2C_SH_BASE1 296 U_BOOT_I2C_ADAP_COMPLETE(sh_1, sh_i2c_init, sh_i2c_probe, sh_i2c_read, 297 sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED1, 0, 1) 298 #endif 299 #ifdef CONFIG_SYS_I2C_SH_BASE2 300 U_BOOT_I2C_ADAP_COMPLETE(sh_2, sh_i2c_init, sh_i2c_probe, sh_i2c_read, 301 sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED2, 0, 2) 302 #endif 303 #ifdef CONFIG_SYS_I2C_SH_BASE3 304 U_BOOT_I2C_ADAP_COMPLETE(sh_3, sh_i2c_init, sh_i2c_probe, sh_i2c_read, 305 sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED3, 0, 3) 306 #endif 307 #ifdef CONFIG_SYS_I2C_SH_BASE4 308 U_BOOT_I2C_ADAP_COMPLETE(sh_4, sh_i2c_init, sh_i2c_probe, sh_i2c_read, 309 sh_i2c_write, sh_i2c_set_bus_speed, CONFIG_SYS_I2C_SH_SPEED4, 0, 4) 310 #endif 311