1 /* 2 * Copyright (C) 2011, 2013 Renesas Solutions Corp. 3 * Copyright (C) 2011, 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 #include <common.h> 9 #include <asm/io.h> 10 11 DECLARE_GLOBAL_DATA_PTR; 12 13 /* Every register is 32bit aligned, but only 8bits in size */ 14 #define ureg(name) u8 name; u8 __pad_##name##0; u16 __pad_##name##1; 15 struct sh_i2c { 16 ureg(icdr); 17 ureg(iccr); 18 ureg(icsr); 19 ureg(icic); 20 ureg(iccl); 21 ureg(icch); 22 }; 23 #undef ureg 24 25 static struct sh_i2c *base; 26 27 /* ICCR */ 28 #define SH_I2C_ICCR_ICE (1 << 7) 29 #define SH_I2C_ICCR_RACK (1 << 6) 30 #define SH_I2C_ICCR_RTS (1 << 4) 31 #define SH_I2C_ICCR_BUSY (1 << 2) 32 #define SH_I2C_ICCR_SCP (1 << 0) 33 34 /* ICSR / ICIC */ 35 #define SH_IC_BUSY (1 << 4) 36 #define SH_IC_TACK (1 << 2) 37 #define SH_IC_WAIT (1 << 1) 38 #define SH_IC_DTE (1 << 0) 39 40 #ifdef CONFIG_SH_I2C_8BIT 41 /* store 8th bit of iccl and icch in ICIC register */ 42 #define SH_I2C_ICIC_ICCLB8 (1 << 7) 43 #define SH_I2C_ICIC_ICCHB8 (1 << 6) 44 #endif 45 46 static u16 iccl, icch; 47 48 #define IRQ_WAIT 1000 49 50 static void irq_dte(struct sh_i2c *base) 51 { 52 int i; 53 54 for (i = 0 ; i < IRQ_WAIT ; i++) { 55 if (SH_IC_DTE & readb(&base->icsr)) 56 break; 57 udelay(10); 58 } 59 } 60 61 static int irq_dte_with_tack(struct sh_i2c *base) 62 { 63 int i; 64 65 for (i = 0 ; i < IRQ_WAIT ; i++) { 66 if (SH_IC_DTE & readb(&base->icsr)) 67 break; 68 if (SH_IC_TACK & readb(&base->icsr)) 69 return -1; 70 udelay(10); 71 } 72 return 0; 73 } 74 75 static void irq_busy(struct sh_i2c *base) 76 { 77 int i; 78 79 for (i = 0 ; i < IRQ_WAIT ; i++) { 80 if (!(SH_IC_BUSY & readb(&base->icsr))) 81 break; 82 udelay(10); 83 } 84 } 85 86 static int i2c_set_addr(struct sh_i2c *base, u8 id, u8 reg, int stop) 87 { 88 u8 icic = SH_IC_TACK; 89 90 clrbits_8(&base->iccr, SH_I2C_ICCR_ICE); 91 setbits_8(&base->iccr, SH_I2C_ICCR_ICE); 92 93 writeb(iccl & 0xff, &base->iccl); 94 writeb(icch & 0xff, &base->icch); 95 #ifdef CONFIG_SH_I2C_8BIT 96 if (iccl > 0xff) 97 icic |= SH_I2C_ICIC_ICCLB8; 98 if (icch > 0xff) 99 icic |= SH_I2C_ICIC_ICCHB8; 100 #endif 101 writeb(icic, &base->icic); 102 103 writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &base->iccr); 104 irq_dte(base); 105 106 clrbits_8(&base->icsr, SH_IC_TACK); 107 writeb(id << 1, &base->icdr); 108 if (irq_dte_with_tack(base) != 0) 109 return -1; 110 111 writeb(reg, &base->icdr); 112 if (stop) 113 writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS), &base->iccr); 114 115 if (irq_dte_with_tack(base) != 0) 116 return -1; 117 return 0; 118 } 119 120 static void i2c_finish(struct sh_i2c *base) 121 { 122 writeb(0, &base->icsr); 123 clrbits_8(&base->iccr, SH_I2C_ICCR_ICE); 124 } 125 126 static int i2c_raw_write(struct sh_i2c *base, u8 id, u8 reg, u8 val) 127 { 128 int ret = -1; 129 if (i2c_set_addr(base, id, reg, 0) != 0) 130 goto exit0; 131 udelay(10); 132 133 writeb(val, &base->icdr); 134 if (irq_dte_with_tack(base) != 0) 135 goto exit0; 136 137 writeb((SH_I2C_ICCR_ICE | SH_I2C_ICCR_RTS), &base->iccr); 138 if (irq_dte_with_tack(base) != 0) 139 goto exit0; 140 irq_busy(base); 141 ret = 0; 142 exit0: 143 i2c_finish(base); 144 return ret; 145 } 146 147 static int i2c_raw_read(struct sh_i2c *base, u8 id, u8 reg) 148 { 149 int ret = -1; 150 151 #if defined(CONFIG_SH73A0) 152 if (i2c_set_addr(base, id, reg, 0) != 0) 153 goto exit0; 154 #else 155 if (i2c_set_addr(base, id, reg, 1) != 0) 156 goto exit0; 157 udelay(100); 158 #endif 159 160 writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &base->iccr); 161 irq_dte(base); 162 163 writeb(id << 1 | 0x01, &base->icdr); 164 if (irq_dte_with_tack(base) != 0) 165 goto exit0; 166 167 writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_SCP), &base->iccr); 168 if (irq_dte_with_tack(base) != 0) 169 goto exit0; 170 171 ret = readb(&base->icdr) & 0xff; 172 173 writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RACK), &base->iccr); 174 readb(&base->icdr); /* Dummy read */ 175 irq_busy(base); 176 exit0: 177 i2c_finish(base); 178 179 return ret; 180 } 181 182 #ifdef CONFIG_I2C_MULTI_BUS 183 static unsigned int current_bus; 184 185 /** 186 * i2c_set_bus_num - change active I2C bus 187 * @bus: bus index, zero based 188 * @returns: 0 on success, non-0 on failure 189 */ 190 int i2c_set_bus_num(unsigned int bus) 191 { 192 if ((bus < 0) || (bus >= CONFIG_SYS_MAX_I2C_BUS)) { 193 printf("Bad bus: %d\n", bus); 194 return -1; 195 } 196 197 switch (bus) { 198 case 0: 199 base = (void *)CONFIG_SH_I2C_BASE0; 200 break; 201 case 1: 202 base = (void *)CONFIG_SH_I2C_BASE1; 203 break; 204 #ifdef CONFIG_SH_I2C_BASE2 205 case 2: 206 base = (void *)CONFIG_SH_I2C_BASE2; 207 break; 208 #endif 209 #ifdef CONFIG_SH_I2C_BASE3 210 case 3: 211 base = (void *)CONFIG_SH_I2C_BASE3; 212 break; 213 #endif 214 #ifdef CONFIG_SH_I2C_BASE4 215 case 4: 216 base = (void *)CONFIG_SH_I2C_BASE4; 217 break; 218 #endif 219 default: 220 return -1; 221 } 222 current_bus = bus; 223 224 return 0; 225 } 226 227 /** 228 * i2c_get_bus_num - returns index of active I2C bus 229 */ 230 unsigned int i2c_get_bus_num(void) 231 { 232 return current_bus; 233 } 234 #endif 235 236 #define SH_I2C_ICCL_CALC(clk, date, t_low, t_high) \ 237 ((clk / rate) * (t_low / t_low + t_high)) 238 #define SH_I2C_ICCH_CALC(clk, date, t_low, t_high) \ 239 ((clk / rate) * (t_high / t_low + t_high)) 240 241 void i2c_init(int speed, int slaveaddr) 242 { 243 int num, denom, tmp; 244 245 /* No i2c support prior to relocation */ 246 if (!(gd->flags & GD_FLG_RELOC)) 247 return; 248 249 #ifdef CONFIG_I2C_MULTI_BUS 250 current_bus = 0; 251 #endif 252 base = (struct sh_i2c *)CONFIG_SH_I2C_BASE0; 253 254 /* 255 * Calculate the value for iccl. From the data sheet: 256 * iccl = (p-clock / transfer-rate) * (L / (L + H)) 257 * where L and H are the SCL low and high ratio. 258 */ 259 num = CONFIG_SH_I2C_CLOCK * CONFIG_SH_I2C_DATA_LOW; 260 denom = speed * (CONFIG_SH_I2C_DATA_HIGH + CONFIG_SH_I2C_DATA_LOW); 261 tmp = num * 10 / denom; 262 if (tmp % 10 >= 5) 263 iccl = (u16)((num/denom) + 1); 264 else 265 iccl = (u16)(num/denom); 266 267 /* Calculate the value for icch. From the data sheet: 268 icch = (p clock / transfer rate) * (H / (L + H)) */ 269 num = CONFIG_SH_I2C_CLOCK * CONFIG_SH_I2C_DATA_HIGH; 270 tmp = num * 10 / denom; 271 if (tmp % 10 >= 5) 272 icch = (u16)((num/denom) + 1); 273 else 274 icch = (u16)(num/denom); 275 } 276 277 /* 278 * i2c_read: - Read multiple bytes from an i2c device 279 * 280 * The higher level routines take into account that this function is only 281 * called with len < page length of the device (see configuration file) 282 * 283 * @chip: address of the chip which is to be read 284 * @addr: i2c data address within the chip 285 * @alen: length of the i2c data address (1..2 bytes) 286 * @buffer: where to write the data 287 * @len: how much byte do we want to read 288 * @return: 0 in case of success 289 */ 290 int i2c_read(u8 chip, u32 addr, int alen, u8 *buffer, int len) 291 { 292 int ret; 293 int i = 0; 294 for (i = 0 ; i < len ; i++) { 295 ret = i2c_raw_read(base, chip, addr + i); 296 if (ret < 0) 297 return -1; 298 buffer[i] = ret & 0xff; 299 } 300 return 0; 301 } 302 303 /* 304 * i2c_write: - Write multiple bytes to an i2c device 305 * 306 * The higher level routines take into account that this function is only 307 * called with len < page length of the device (see configuration file) 308 * 309 * @chip: address of the chip which is to be written 310 * @addr: i2c data address within the chip 311 * @alen: length of the i2c data address (1..2 bytes) 312 * @buffer: where to find the data to be written 313 * @len: how much byte do we want to read 314 * @return: 0 in case of success 315 */ 316 int i2c_write(u8 chip, u32 addr, int alen, u8 *buffer, int len) 317 { 318 int i = 0; 319 for (i = 0; i < len ; i++) 320 if (i2c_raw_write(base, chip, addr + i, buffer[i]) != 0) 321 return -1; 322 return 0; 323 } 324 325 /* 326 * i2c_probe: - Test if a chip answers for a given i2c address 327 * 328 * @chip: address of the chip which is searched for 329 * @return: 0 if a chip was found, -1 otherwhise 330 */ 331 int i2c_probe(u8 chip) 332 { 333 int ret; 334 335 ret = i2c_set_addr(base, chip, 0, 1); 336 i2c_finish(base); 337 return ret; 338 } 339