1 /* 2 * Copyright (C) 2011 Renesas Solutions Corp. 3 * Copyright (C) 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> 4 * 5 * This program is free software; you can redistribute it and/or 6 * modify it under the terms of the GNU General Public License as 7 * published by the Free Software Foundation; either version 2 of 8 * the License, or (at your option) any later version. 9 * 10 * This program is distributed in the hope that it will be useful, 11 * but WITHOUT ANY WARRANTY; without even the implied warranty of 12 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 13 * GNU General Public License for more details. 14 * 15 * You should have received a copy of the GNU General Public License 16 * along with this program; if not, write to the Free Software 17 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 18 * MA 02111-1307 USA 19 */ 20 21 #include <common.h> 22 #include <asm/io.h> 23 24 /* Every register is 32bit aligned, but only 8bits in size */ 25 #define ureg(name) u8 name; u8 __pad_##name##0; u16 __pad_##name##1; 26 struct sh_i2c { 27 ureg(icdr); 28 ureg(iccr); 29 ureg(icsr); 30 ureg(icic); 31 ureg(iccl); 32 ureg(icch); 33 }; 34 #undef ureg 35 36 static struct sh_i2c *base; 37 38 /* ICCR */ 39 #define SH_I2C_ICCR_ICE (1 << 7) 40 #define SH_I2C_ICCR_RACK (1 << 6) 41 #define SH_I2C_ICCR_RTS (1 << 4) 42 #define SH_I2C_ICCR_BUSY (1 << 2) 43 #define SH_I2C_ICCR_SCP (1 << 0) 44 45 /* ICSR / ICIC */ 46 #define SH_IC_BUSY (1 << 3) 47 #define SH_IC_TACK (1 << 2) 48 #define SH_IC_WAIT (1 << 1) 49 #define SH_IC_DTE (1 << 0) 50 51 static u8 iccl, icch; 52 53 #define IRQ_WAIT 1000 54 55 static void irq_dte(struct sh_i2c *base) 56 { 57 int i; 58 59 for (i = 0 ; i < IRQ_WAIT ; i++) { 60 if (SH_IC_DTE & readb(&base->icsr)) 61 break; 62 udelay(10); 63 } 64 } 65 66 static void irq_busy(struct sh_i2c *base) 67 { 68 int i; 69 70 for (i = 0 ; i < IRQ_WAIT ; i++) { 71 if (!(SH_IC_BUSY & readb(&base->icsr))) 72 break; 73 udelay(10); 74 } 75 } 76 77 static void i2c_set_addr(struct sh_i2c *base, u8 id, u8 reg, int stop) 78 { 79 writeb(readb(&base->iccr) & ~SH_I2C_ICCR_ICE, &base->iccr); 80 writeb(readb(&base->iccr) | SH_I2C_ICCR_ICE, &base->iccr); 81 82 writeb(iccl, &base->iccl); 83 writeb(icch, &base->icch); 84 writeb(0, &base->icic); 85 86 writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &base->iccr); 87 irq_dte(base); 88 89 writeb(id << 1, &base->icdr); 90 irq_dte(base); 91 92 writeb(reg, &base->icdr); 93 if (stop) 94 writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS), &base->iccr); 95 96 irq_dte(base); 97 } 98 99 static void i2c_finish(struct sh_i2c *base) 100 { 101 writeb(0, &base->icsr); 102 writeb(readb(&base->iccr) & ~SH_I2C_ICCR_ICE, &base->iccr); 103 } 104 105 static void i2c_raw_write(struct sh_i2c *base, u8 id, u8 reg, u8 val) 106 { 107 i2c_set_addr(base, id, reg, 0); 108 udelay(10); 109 110 writeb(val, &base->icdr); 111 irq_dte(base); 112 113 writeb((SH_I2C_ICCR_ICE | SH_I2C_ICCR_RTS), &base->iccr); 114 irq_dte(base); 115 irq_busy(base); 116 117 i2c_finish(base); 118 } 119 120 static u8 i2c_raw_read(struct sh_i2c *base, u8 id, u8 reg) 121 { 122 u8 ret; 123 124 i2c_set_addr(base, id, reg, 1); 125 udelay(100); 126 127 writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &base->iccr); 128 irq_dte(base); 129 130 writeb(id << 1 | 0x01, &base->icdr); 131 irq_dte(base); 132 133 writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_SCP), &base->iccr); 134 irq_dte(base); 135 136 ret = readb(&base->icdr); 137 138 writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RACK), &base->iccr); 139 readb(&base->icdr); /* Dummy read */ 140 irq_busy(base); 141 142 i2c_finish(base); 143 144 return ret; 145 } 146 147 #ifdef CONFIG_I2C_MULTI_BUS 148 static unsigned int current_bus; 149 150 /** 151 * i2c_set_bus_num - change active I2C bus 152 * @bus: bus index, zero based 153 * @returns: 0 on success, non-0 on failure 154 */ 155 int i2c_set_bus_num(unsigned int bus) 156 { 157 if ((bus < 0) || (bus >= CONFIG_SYS_MAX_I2C_BUS)) { 158 printf("Bad bus: %d\n", bus); 159 return -1; 160 } 161 162 switch (bus) { 163 case 0: 164 base = (void *)CONFIG_SH_I2C_BASE0; 165 break; 166 case 1: 167 base = (void *)CONFIG_SH_I2C_BASE1; 168 break; 169 default: 170 return -1; 171 } 172 current_bus = bus; 173 174 return 0; 175 } 176 177 /** 178 * i2c_get_bus_num - returns index of active I2C bus 179 */ 180 unsigned int i2c_get_bus_num(void) 181 { 182 return current_bus; 183 } 184 #endif 185 186 #define SH_I2C_ICCL_CALC(clk, date, t_low, t_high) \ 187 ((clk / rate) * (t_low / t_low + t_high)) 188 #define SH_I2C_ICCH_CALC(clk, date, t_low, t_high) \ 189 ((clk / rate) * (t_high / t_low + t_high)) 190 191 void i2c_init(int speed, int slaveaddr) 192 { 193 int num, denom, tmp; 194 195 #ifdef CONFIG_I2C_MULTI_BUS 196 current_bus = 0; 197 #endif 198 base = (struct sh_i2c *)CONFIG_SH_I2C_BASE0; 199 200 /* 201 * Calculate the value for iccl. From the data sheet: 202 * iccl = (p-clock / transfer-rate) * (L / (L + H)) 203 * where L and H are the SCL low and high ratio. 204 */ 205 num = CONFIG_SH_I2C_CLOCK * CONFIG_SH_I2C_DATA_LOW; 206 denom = speed * (CONFIG_SH_I2C_DATA_HIGH + CONFIG_SH_I2C_DATA_LOW); 207 tmp = num * 10 / denom; 208 if (tmp % 10 >= 5) 209 iccl = (u8)((num/denom) + 1); 210 else 211 iccl = (u8)(num/denom); 212 213 /* Calculate the value for icch. From the data sheet: 214 icch = (p clock / transfer rate) * (H / (L + H)) */ 215 num = CONFIG_SH_I2C_CLOCK * CONFIG_SH_I2C_DATA_HIGH; 216 tmp = num * 10 / denom; 217 if (tmp % 10 >= 5) 218 icch = (u8)((num/denom) + 1); 219 else 220 icch = (u8)(num/denom); 221 } 222 223 /* 224 * i2c_read: - Read multiple bytes from an i2c device 225 * 226 * The higher level routines take into account that this function is only 227 * called with len < page length of the device (see configuration file) 228 * 229 * @chip: address of the chip which is to be read 230 * @addr: i2c data address within the chip 231 * @alen: length of the i2c data address (1..2 bytes) 232 * @buffer: where to write the data 233 * @len: how much byte do we want to read 234 * @return: 0 in case of success 235 */ 236 int i2c_read(u8 chip, u32 addr, int alen, u8 *buffer, int len) 237 { 238 int i = 0; 239 for (i = 0 ; i < len ; i++) 240 buffer[i] = i2c_raw_read(base, chip, addr + i); 241 242 return 0; 243 } 244 245 /* 246 * i2c_write: - Write multiple bytes to an i2c device 247 * 248 * The higher level routines take into account that this function is only 249 * called with len < page length of the device (see configuration file) 250 * 251 * @chip: address of the chip which is to be written 252 * @addr: i2c data address within the chip 253 * @alen: length of the i2c data address (1..2 bytes) 254 * @buffer: where to find the data to be written 255 * @len: how much byte do we want to read 256 * @return: 0 in case of success 257 */ 258 int i2c_write(u8 chip, u32 addr, int alen, u8 *buffer, int len) 259 { 260 int i = 0; 261 for (i = 0; i < len ; i++) 262 i2c_raw_write(base, chip, addr + i, buffer[i]); 263 264 return 0; 265 } 266 267 /* 268 * i2c_probe: - Test if a chip answers for a given i2c address 269 * 270 * @chip: address of the chip which is searched for 271 * @return: 0 if a chip was found, -1 otherwhise 272 */ 273 int i2c_probe(u8 chip) 274 { 275 return 0; 276 } 277