13dab3e0eSNobuhiro Iwamatsu /* 23dab3e0eSNobuhiro Iwamatsu * Copyright (C) 2011 Renesas Solutions Corp. 33dab3e0eSNobuhiro Iwamatsu * Copyright (C) 2011 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> 43dab3e0eSNobuhiro Iwamatsu * 5*1a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 63dab3e0eSNobuhiro Iwamatsu */ 73dab3e0eSNobuhiro Iwamatsu 83dab3e0eSNobuhiro Iwamatsu #include <common.h> 93dab3e0eSNobuhiro Iwamatsu #include <asm/io.h> 103dab3e0eSNobuhiro Iwamatsu 113dab3e0eSNobuhiro Iwamatsu /* Every register is 32bit aligned, but only 8bits in size */ 123dab3e0eSNobuhiro Iwamatsu #define ureg(name) u8 name; u8 __pad_##name##0; u16 __pad_##name##1; 133dab3e0eSNobuhiro Iwamatsu struct sh_i2c { 143dab3e0eSNobuhiro Iwamatsu ureg(icdr); 153dab3e0eSNobuhiro Iwamatsu ureg(iccr); 163dab3e0eSNobuhiro Iwamatsu ureg(icsr); 173dab3e0eSNobuhiro Iwamatsu ureg(icic); 183dab3e0eSNobuhiro Iwamatsu ureg(iccl); 193dab3e0eSNobuhiro Iwamatsu ureg(icch); 203dab3e0eSNobuhiro Iwamatsu }; 213dab3e0eSNobuhiro Iwamatsu #undef ureg 223dab3e0eSNobuhiro Iwamatsu 233dab3e0eSNobuhiro Iwamatsu static struct sh_i2c *base; 243dab3e0eSNobuhiro Iwamatsu 253dab3e0eSNobuhiro Iwamatsu /* ICCR */ 263dab3e0eSNobuhiro Iwamatsu #define SH_I2C_ICCR_ICE (1 << 7) 273dab3e0eSNobuhiro Iwamatsu #define SH_I2C_ICCR_RACK (1 << 6) 283dab3e0eSNobuhiro Iwamatsu #define SH_I2C_ICCR_RTS (1 << 4) 293dab3e0eSNobuhiro Iwamatsu #define SH_I2C_ICCR_BUSY (1 << 2) 303dab3e0eSNobuhiro Iwamatsu #define SH_I2C_ICCR_SCP (1 << 0) 313dab3e0eSNobuhiro Iwamatsu 323dab3e0eSNobuhiro Iwamatsu /* ICSR / ICIC */ 3357d7c804STetsuyuki Kobayashi #define SH_IC_BUSY (1 << 4) 343dab3e0eSNobuhiro Iwamatsu #define SH_IC_TACK (1 << 2) 353dab3e0eSNobuhiro Iwamatsu #define SH_IC_WAIT (1 << 1) 363dab3e0eSNobuhiro Iwamatsu #define SH_IC_DTE (1 << 0) 373dab3e0eSNobuhiro Iwamatsu 38b1af67feSTetsuyuki Kobayashi #ifdef CONFIG_SH_I2C_8BIT 39b1af67feSTetsuyuki Kobayashi /* store 8th bit of iccl and icch in ICIC register */ 40b1af67feSTetsuyuki Kobayashi #define SH_I2C_ICIC_ICCLB8 (1 << 7) 41b1af67feSTetsuyuki Kobayashi #define SH_I2C_ICIC_ICCHB8 (1 << 6) 42b1af67feSTetsuyuki Kobayashi #endif 43b1af67feSTetsuyuki Kobayashi 44b1af67feSTetsuyuki Kobayashi static u16 iccl, icch; 453dab3e0eSNobuhiro Iwamatsu 463dab3e0eSNobuhiro Iwamatsu #define IRQ_WAIT 1000 473dab3e0eSNobuhiro Iwamatsu 483dab3e0eSNobuhiro Iwamatsu static void irq_dte(struct sh_i2c *base) 493dab3e0eSNobuhiro Iwamatsu { 503dab3e0eSNobuhiro Iwamatsu int i; 513dab3e0eSNobuhiro Iwamatsu 523dab3e0eSNobuhiro Iwamatsu for (i = 0 ; i < IRQ_WAIT ; i++) { 533dab3e0eSNobuhiro Iwamatsu if (SH_IC_DTE & readb(&base->icsr)) 543dab3e0eSNobuhiro Iwamatsu break; 553dab3e0eSNobuhiro Iwamatsu udelay(10); 563dab3e0eSNobuhiro Iwamatsu } 573dab3e0eSNobuhiro Iwamatsu } 583dab3e0eSNobuhiro Iwamatsu 59d042d712STetsuyuki Kobayashi static int irq_dte_with_tack(struct sh_i2c *base) 60d042d712STetsuyuki Kobayashi { 61d042d712STetsuyuki Kobayashi int i; 62d042d712STetsuyuki Kobayashi 63d042d712STetsuyuki Kobayashi for (i = 0 ; i < IRQ_WAIT ; i++) { 64d042d712STetsuyuki Kobayashi if (SH_IC_DTE & readb(&base->icsr)) 65d042d712STetsuyuki Kobayashi break; 66d042d712STetsuyuki Kobayashi if (SH_IC_TACK & readb(&base->icsr)) 67d042d712STetsuyuki Kobayashi return -1; 68d042d712STetsuyuki Kobayashi udelay(10); 69d042d712STetsuyuki Kobayashi } 70d042d712STetsuyuki Kobayashi return 0; 71d042d712STetsuyuki Kobayashi } 72d042d712STetsuyuki Kobayashi 733dab3e0eSNobuhiro Iwamatsu static void irq_busy(struct sh_i2c *base) 743dab3e0eSNobuhiro Iwamatsu { 753dab3e0eSNobuhiro Iwamatsu int i; 763dab3e0eSNobuhiro Iwamatsu 773dab3e0eSNobuhiro Iwamatsu for (i = 0 ; i < IRQ_WAIT ; i++) { 783dab3e0eSNobuhiro Iwamatsu if (!(SH_IC_BUSY & readb(&base->icsr))) 793dab3e0eSNobuhiro Iwamatsu break; 803dab3e0eSNobuhiro Iwamatsu udelay(10); 813dab3e0eSNobuhiro Iwamatsu } 823dab3e0eSNobuhiro Iwamatsu } 833dab3e0eSNobuhiro Iwamatsu 84d042d712STetsuyuki Kobayashi static int i2c_set_addr(struct sh_i2c *base, u8 id, u8 reg, int stop) 853dab3e0eSNobuhiro Iwamatsu { 86d042d712STetsuyuki Kobayashi u8 icic = SH_IC_TACK; 87b1af67feSTetsuyuki Kobayashi 88f539094fSTetsuyuki Kobayashi clrbits_8(&base->iccr, SH_I2C_ICCR_ICE); 89f539094fSTetsuyuki Kobayashi setbits_8(&base->iccr, SH_I2C_ICCR_ICE); 903dab3e0eSNobuhiro Iwamatsu 91b1af67feSTetsuyuki Kobayashi writeb(iccl & 0xff, &base->iccl); 92b1af67feSTetsuyuki Kobayashi writeb(icch & 0xff, &base->icch); 93b1af67feSTetsuyuki Kobayashi #ifdef CONFIG_SH_I2C_8BIT 94b1af67feSTetsuyuki Kobayashi if (iccl > 0xff) 95b1af67feSTetsuyuki Kobayashi icic |= SH_I2C_ICIC_ICCLB8; 96b1af67feSTetsuyuki Kobayashi if (icch > 0xff) 97b1af67feSTetsuyuki Kobayashi icic |= SH_I2C_ICIC_ICCHB8; 98b1af67feSTetsuyuki Kobayashi #endif 99b1af67feSTetsuyuki Kobayashi writeb(icic, &base->icic); 1003dab3e0eSNobuhiro Iwamatsu 1013dab3e0eSNobuhiro Iwamatsu writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &base->iccr); 1023dab3e0eSNobuhiro Iwamatsu irq_dte(base); 1033dab3e0eSNobuhiro Iwamatsu 104f539094fSTetsuyuki Kobayashi clrbits_8(&base->icsr, SH_IC_TACK); 1053dab3e0eSNobuhiro Iwamatsu writeb(id << 1, &base->icdr); 106d042d712STetsuyuki Kobayashi if (irq_dte_with_tack(base) != 0) 107d042d712STetsuyuki Kobayashi return -1; 1083dab3e0eSNobuhiro Iwamatsu 1093dab3e0eSNobuhiro Iwamatsu writeb(reg, &base->icdr); 1103dab3e0eSNobuhiro Iwamatsu if (stop) 1113dab3e0eSNobuhiro Iwamatsu writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS), &base->iccr); 1123dab3e0eSNobuhiro Iwamatsu 113d042d712STetsuyuki Kobayashi if (irq_dte_with_tack(base) != 0) 114d042d712STetsuyuki Kobayashi return -1; 115d042d712STetsuyuki Kobayashi return 0; 1163dab3e0eSNobuhiro Iwamatsu } 1173dab3e0eSNobuhiro Iwamatsu 1183dab3e0eSNobuhiro Iwamatsu static void i2c_finish(struct sh_i2c *base) 1193dab3e0eSNobuhiro Iwamatsu { 1203dab3e0eSNobuhiro Iwamatsu writeb(0, &base->icsr); 121f539094fSTetsuyuki Kobayashi clrbits_8(&base->iccr, SH_I2C_ICCR_ICE); 1223dab3e0eSNobuhiro Iwamatsu } 1233dab3e0eSNobuhiro Iwamatsu 1240e5fb33cSTetsuyuki Kobayashi static int i2c_raw_write(struct sh_i2c *base, u8 id, u8 reg, u8 val) 1253dab3e0eSNobuhiro Iwamatsu { 1260e5fb33cSTetsuyuki Kobayashi int ret = -1; 1270e5fb33cSTetsuyuki Kobayashi if (i2c_set_addr(base, id, reg, 0) != 0) 1280e5fb33cSTetsuyuki Kobayashi goto exit0; 1293dab3e0eSNobuhiro Iwamatsu udelay(10); 1303dab3e0eSNobuhiro Iwamatsu 1313dab3e0eSNobuhiro Iwamatsu writeb(val, &base->icdr); 1320e5fb33cSTetsuyuki Kobayashi if (irq_dte_with_tack(base) != 0) 1330e5fb33cSTetsuyuki Kobayashi goto exit0; 1343dab3e0eSNobuhiro Iwamatsu 1353dab3e0eSNobuhiro Iwamatsu writeb((SH_I2C_ICCR_ICE | SH_I2C_ICCR_RTS), &base->iccr); 1360e5fb33cSTetsuyuki Kobayashi if (irq_dte_with_tack(base) != 0) 1370e5fb33cSTetsuyuki Kobayashi goto exit0; 1383dab3e0eSNobuhiro Iwamatsu irq_busy(base); 1390e5fb33cSTetsuyuki Kobayashi ret = 0; 1400e5fb33cSTetsuyuki Kobayashi exit0: 1413dab3e0eSNobuhiro Iwamatsu i2c_finish(base); 1420e5fb33cSTetsuyuki Kobayashi return ret; 1433dab3e0eSNobuhiro Iwamatsu } 1443dab3e0eSNobuhiro Iwamatsu 1450e5fb33cSTetsuyuki Kobayashi static int i2c_raw_read(struct sh_i2c *base, u8 id, u8 reg) 1463dab3e0eSNobuhiro Iwamatsu { 1470e5fb33cSTetsuyuki Kobayashi int ret = -1; 1483dab3e0eSNobuhiro Iwamatsu 1493ce2703dSTetsuyuki Kobayashi #if defined(CONFIG_SH73A0) 1500e5fb33cSTetsuyuki Kobayashi if (i2c_set_addr(base, id, reg, 0) != 0) 1510e5fb33cSTetsuyuki Kobayashi goto exit0; 1523ce2703dSTetsuyuki Kobayashi #else 1530e5fb33cSTetsuyuki Kobayashi if (i2c_set_addr(base, id, reg, 1) != 0) 1540e5fb33cSTetsuyuki Kobayashi goto exit0; 1553dab3e0eSNobuhiro Iwamatsu udelay(100); 1563ce2703dSTetsuyuki Kobayashi #endif 1573dab3e0eSNobuhiro Iwamatsu 1583dab3e0eSNobuhiro Iwamatsu writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RTS|SH_I2C_ICCR_BUSY), &base->iccr); 1593dab3e0eSNobuhiro Iwamatsu irq_dte(base); 1603dab3e0eSNobuhiro Iwamatsu 1613dab3e0eSNobuhiro Iwamatsu writeb(id << 1 | 0x01, &base->icdr); 1620e5fb33cSTetsuyuki Kobayashi if (irq_dte_with_tack(base) != 0) 1630e5fb33cSTetsuyuki Kobayashi goto exit0; 1643dab3e0eSNobuhiro Iwamatsu 1653dab3e0eSNobuhiro Iwamatsu writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_SCP), &base->iccr); 1660e5fb33cSTetsuyuki Kobayashi if (irq_dte_with_tack(base) != 0) 1670e5fb33cSTetsuyuki Kobayashi goto exit0; 1683dab3e0eSNobuhiro Iwamatsu 1690e5fb33cSTetsuyuki Kobayashi ret = readb(&base->icdr) & 0xff; 1703dab3e0eSNobuhiro Iwamatsu 1713dab3e0eSNobuhiro Iwamatsu writeb((SH_I2C_ICCR_ICE|SH_I2C_ICCR_RACK), &base->iccr); 1723dab3e0eSNobuhiro Iwamatsu readb(&base->icdr); /* Dummy read */ 1733dab3e0eSNobuhiro Iwamatsu irq_busy(base); 1740e5fb33cSTetsuyuki Kobayashi exit0: 1753dab3e0eSNobuhiro Iwamatsu i2c_finish(base); 1763dab3e0eSNobuhiro Iwamatsu 1773dab3e0eSNobuhiro Iwamatsu return ret; 1783dab3e0eSNobuhiro Iwamatsu } 1793dab3e0eSNobuhiro Iwamatsu 1803dab3e0eSNobuhiro Iwamatsu #ifdef CONFIG_I2C_MULTI_BUS 1813dab3e0eSNobuhiro Iwamatsu static unsigned int current_bus; 1823dab3e0eSNobuhiro Iwamatsu 1833dab3e0eSNobuhiro Iwamatsu /** 1843dab3e0eSNobuhiro Iwamatsu * i2c_set_bus_num - change active I2C bus 1853dab3e0eSNobuhiro Iwamatsu * @bus: bus index, zero based 1863dab3e0eSNobuhiro Iwamatsu * @returns: 0 on success, non-0 on failure 1873dab3e0eSNobuhiro Iwamatsu */ 1883dab3e0eSNobuhiro Iwamatsu int i2c_set_bus_num(unsigned int bus) 1893dab3e0eSNobuhiro Iwamatsu { 1903dab3e0eSNobuhiro Iwamatsu if ((bus < 0) || (bus >= CONFIG_SYS_MAX_I2C_BUS)) { 1913dab3e0eSNobuhiro Iwamatsu printf("Bad bus: %d\n", bus); 1923dab3e0eSNobuhiro Iwamatsu return -1; 1933dab3e0eSNobuhiro Iwamatsu } 1943dab3e0eSNobuhiro Iwamatsu 1953dab3e0eSNobuhiro Iwamatsu switch (bus) { 1963dab3e0eSNobuhiro Iwamatsu case 0: 1973dab3e0eSNobuhiro Iwamatsu base = (void *)CONFIG_SH_I2C_BASE0; 1983dab3e0eSNobuhiro Iwamatsu break; 1993dab3e0eSNobuhiro Iwamatsu case 1: 2003dab3e0eSNobuhiro Iwamatsu base = (void *)CONFIG_SH_I2C_BASE1; 2013dab3e0eSNobuhiro Iwamatsu break; 202020ec727STetsuyuki Kobayashi #ifdef CONFIG_SH_I2C_BASE2 203020ec727STetsuyuki Kobayashi case 2: 204020ec727STetsuyuki Kobayashi base = (void *)CONFIG_SH_I2C_BASE2; 205020ec727STetsuyuki Kobayashi break; 206020ec727STetsuyuki Kobayashi #endif 207020ec727STetsuyuki Kobayashi #ifdef CONFIG_SH_I2C_BASE3 208020ec727STetsuyuki Kobayashi case 3: 209020ec727STetsuyuki Kobayashi base = (void *)CONFIG_SH_I2C_BASE3; 210020ec727STetsuyuki Kobayashi break; 211020ec727STetsuyuki Kobayashi #endif 212020ec727STetsuyuki Kobayashi #ifdef CONFIG_SH_I2C_BASE4 213020ec727STetsuyuki Kobayashi case 4: 214020ec727STetsuyuki Kobayashi base = (void *)CONFIG_SH_I2C_BASE4; 215020ec727STetsuyuki Kobayashi break; 216020ec727STetsuyuki Kobayashi #endif 2173dab3e0eSNobuhiro Iwamatsu default: 2183dab3e0eSNobuhiro Iwamatsu return -1; 2193dab3e0eSNobuhiro Iwamatsu } 2203dab3e0eSNobuhiro Iwamatsu current_bus = bus; 2213dab3e0eSNobuhiro Iwamatsu 2223dab3e0eSNobuhiro Iwamatsu return 0; 2233dab3e0eSNobuhiro Iwamatsu } 2243dab3e0eSNobuhiro Iwamatsu 2253dab3e0eSNobuhiro Iwamatsu /** 2263dab3e0eSNobuhiro Iwamatsu * i2c_get_bus_num - returns index of active I2C bus 2273dab3e0eSNobuhiro Iwamatsu */ 2283dab3e0eSNobuhiro Iwamatsu unsigned int i2c_get_bus_num(void) 2293dab3e0eSNobuhiro Iwamatsu { 2303dab3e0eSNobuhiro Iwamatsu return current_bus; 2313dab3e0eSNobuhiro Iwamatsu } 2323dab3e0eSNobuhiro Iwamatsu #endif 2333dab3e0eSNobuhiro Iwamatsu 2343dab3e0eSNobuhiro Iwamatsu #define SH_I2C_ICCL_CALC(clk, date, t_low, t_high) \ 2353dab3e0eSNobuhiro Iwamatsu ((clk / rate) * (t_low / t_low + t_high)) 2363dab3e0eSNobuhiro Iwamatsu #define SH_I2C_ICCH_CALC(clk, date, t_low, t_high) \ 2373dab3e0eSNobuhiro Iwamatsu ((clk / rate) * (t_high / t_low + t_high)) 2383dab3e0eSNobuhiro Iwamatsu 2393dab3e0eSNobuhiro Iwamatsu void i2c_init(int speed, int slaveaddr) 2403dab3e0eSNobuhiro Iwamatsu { 2413dab3e0eSNobuhiro Iwamatsu int num, denom, tmp; 2423dab3e0eSNobuhiro Iwamatsu 2433dab3e0eSNobuhiro Iwamatsu #ifdef CONFIG_I2C_MULTI_BUS 2443dab3e0eSNobuhiro Iwamatsu current_bus = 0; 2453dab3e0eSNobuhiro Iwamatsu #endif 2463dab3e0eSNobuhiro Iwamatsu base = (struct sh_i2c *)CONFIG_SH_I2C_BASE0; 2473dab3e0eSNobuhiro Iwamatsu 2483dab3e0eSNobuhiro Iwamatsu /* 2493dab3e0eSNobuhiro Iwamatsu * Calculate the value for iccl. From the data sheet: 2503dab3e0eSNobuhiro Iwamatsu * iccl = (p-clock / transfer-rate) * (L / (L + H)) 2513dab3e0eSNobuhiro Iwamatsu * where L and H are the SCL low and high ratio. 2523dab3e0eSNobuhiro Iwamatsu */ 2533dab3e0eSNobuhiro Iwamatsu num = CONFIG_SH_I2C_CLOCK * CONFIG_SH_I2C_DATA_LOW; 2543dab3e0eSNobuhiro Iwamatsu denom = speed * (CONFIG_SH_I2C_DATA_HIGH + CONFIG_SH_I2C_DATA_LOW); 2553dab3e0eSNobuhiro Iwamatsu tmp = num * 10 / denom; 2563dab3e0eSNobuhiro Iwamatsu if (tmp % 10 >= 5) 257b1af67feSTetsuyuki Kobayashi iccl = (u16)((num/denom) + 1); 2583dab3e0eSNobuhiro Iwamatsu else 259b1af67feSTetsuyuki Kobayashi iccl = (u16)(num/denom); 2603dab3e0eSNobuhiro Iwamatsu 2613dab3e0eSNobuhiro Iwamatsu /* Calculate the value for icch. From the data sheet: 2623dab3e0eSNobuhiro Iwamatsu icch = (p clock / transfer rate) * (H / (L + H)) */ 2633dab3e0eSNobuhiro Iwamatsu num = CONFIG_SH_I2C_CLOCK * CONFIG_SH_I2C_DATA_HIGH; 2643dab3e0eSNobuhiro Iwamatsu tmp = num * 10 / denom; 2653dab3e0eSNobuhiro Iwamatsu if (tmp % 10 >= 5) 266b1af67feSTetsuyuki Kobayashi icch = (u16)((num/denom) + 1); 2673dab3e0eSNobuhiro Iwamatsu else 268b1af67feSTetsuyuki Kobayashi icch = (u16)(num/denom); 2693dab3e0eSNobuhiro Iwamatsu } 2703dab3e0eSNobuhiro Iwamatsu 2713dab3e0eSNobuhiro Iwamatsu /* 2723dab3e0eSNobuhiro Iwamatsu * i2c_read: - Read multiple bytes from an i2c device 2733dab3e0eSNobuhiro Iwamatsu * 2743dab3e0eSNobuhiro Iwamatsu * The higher level routines take into account that this function is only 2753dab3e0eSNobuhiro Iwamatsu * called with len < page length of the device (see configuration file) 2763dab3e0eSNobuhiro Iwamatsu * 2773dab3e0eSNobuhiro Iwamatsu * @chip: address of the chip which is to be read 2783dab3e0eSNobuhiro Iwamatsu * @addr: i2c data address within the chip 2793dab3e0eSNobuhiro Iwamatsu * @alen: length of the i2c data address (1..2 bytes) 2803dab3e0eSNobuhiro Iwamatsu * @buffer: where to write the data 2813dab3e0eSNobuhiro Iwamatsu * @len: how much byte do we want to read 2823dab3e0eSNobuhiro Iwamatsu * @return: 0 in case of success 2833dab3e0eSNobuhiro Iwamatsu */ 2843dab3e0eSNobuhiro Iwamatsu int i2c_read(u8 chip, u32 addr, int alen, u8 *buffer, int len) 2853dab3e0eSNobuhiro Iwamatsu { 2860e5fb33cSTetsuyuki Kobayashi int ret; 2873dab3e0eSNobuhiro Iwamatsu int i = 0; 2880e5fb33cSTetsuyuki Kobayashi for (i = 0 ; i < len ; i++) { 2890e5fb33cSTetsuyuki Kobayashi ret = i2c_raw_read(base, chip, addr + i); 2900e5fb33cSTetsuyuki Kobayashi if (ret < 0) 2910e5fb33cSTetsuyuki Kobayashi return -1; 2920e5fb33cSTetsuyuki Kobayashi buffer[i] = ret & 0xff; 2930e5fb33cSTetsuyuki Kobayashi } 2943dab3e0eSNobuhiro Iwamatsu return 0; 2953dab3e0eSNobuhiro Iwamatsu } 2963dab3e0eSNobuhiro Iwamatsu 2973dab3e0eSNobuhiro Iwamatsu /* 2983dab3e0eSNobuhiro Iwamatsu * i2c_write: - Write multiple bytes to an i2c device 2993dab3e0eSNobuhiro Iwamatsu * 3003dab3e0eSNobuhiro Iwamatsu * The higher level routines take into account that this function is only 3013dab3e0eSNobuhiro Iwamatsu * called with len < page length of the device (see configuration file) 3023dab3e0eSNobuhiro Iwamatsu * 3033dab3e0eSNobuhiro Iwamatsu * @chip: address of the chip which is to be written 3043dab3e0eSNobuhiro Iwamatsu * @addr: i2c data address within the chip 3053dab3e0eSNobuhiro Iwamatsu * @alen: length of the i2c data address (1..2 bytes) 3063dab3e0eSNobuhiro Iwamatsu * @buffer: where to find the data to be written 3073dab3e0eSNobuhiro Iwamatsu * @len: how much byte do we want to read 3083dab3e0eSNobuhiro Iwamatsu * @return: 0 in case of success 3093dab3e0eSNobuhiro Iwamatsu */ 3103dab3e0eSNobuhiro Iwamatsu int i2c_write(u8 chip, u32 addr, int alen, u8 *buffer, int len) 3113dab3e0eSNobuhiro Iwamatsu { 3123dab3e0eSNobuhiro Iwamatsu int i = 0; 3133dab3e0eSNobuhiro Iwamatsu for (i = 0; i < len ; i++) 3140e5fb33cSTetsuyuki Kobayashi if (i2c_raw_write(base, chip, addr + i, buffer[i]) != 0) 3150e5fb33cSTetsuyuki Kobayashi return -1; 3163dab3e0eSNobuhiro Iwamatsu return 0; 3173dab3e0eSNobuhiro Iwamatsu } 3183dab3e0eSNobuhiro Iwamatsu 3193dab3e0eSNobuhiro Iwamatsu /* 3203dab3e0eSNobuhiro Iwamatsu * i2c_probe: - Test if a chip answers for a given i2c address 3213dab3e0eSNobuhiro Iwamatsu * 3223dab3e0eSNobuhiro Iwamatsu * @chip: address of the chip which is searched for 3233dab3e0eSNobuhiro Iwamatsu * @return: 0 if a chip was found, -1 otherwhise 3243dab3e0eSNobuhiro Iwamatsu */ 3253dab3e0eSNobuhiro Iwamatsu int i2c_probe(u8 chip) 3263dab3e0eSNobuhiro Iwamatsu { 327d042d712STetsuyuki Kobayashi int ret; 328d042d712STetsuyuki Kobayashi 329d042d712STetsuyuki Kobayashi ret = i2c_set_addr(base, chip, 0, 1); 330d042d712STetsuyuki Kobayashi i2c_finish(base); 331d042d712STetsuyuki Kobayashi return ret; 3323dab3e0eSNobuhiro Iwamatsu } 333