191dffb16SRajeshwari Shinde /* 291dffb16SRajeshwari Shinde * Copyright (C) 2012 Samsung Electronics 391dffb16SRajeshwari Shinde * 41a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 591dffb16SRajeshwari Shinde */ 691dffb16SRajeshwari Shinde 791dffb16SRajeshwari Shinde #ifndef _S3C24X0_I2C_H 891dffb16SRajeshwari Shinde #define _S3C24X0_I2C_H 991dffb16SRajeshwari Shinde 1091dffb16SRajeshwari Shinde struct s3c24x0_i2c { 1191dffb16SRajeshwari Shinde u32 iiccon; 1291dffb16SRajeshwari Shinde u32 iicstat; 1391dffb16SRajeshwari Shinde u32 iicadd; 1491dffb16SRajeshwari Shinde u32 iicds; 1591dffb16SRajeshwari Shinde u32 iiclc; 1691dffb16SRajeshwari Shinde }; 17a9d2ae70SRajeshwari Shinde 18296a461dSNaveen Krishna Ch struct exynos5_hsi2c { 19296a461dSNaveen Krishna Ch u32 usi_ctl; 20296a461dSNaveen Krishna Ch u32 usi_fifo_ctl; 21296a461dSNaveen Krishna Ch u32 usi_trailing_ctl; 22296a461dSNaveen Krishna Ch u32 usi_clk_ctl; 23296a461dSNaveen Krishna Ch u32 usi_clk_slot; 24296a461dSNaveen Krishna Ch u32 spi_ctl; 25296a461dSNaveen Krishna Ch u32 uart_ctl; 26296a461dSNaveen Krishna Ch u32 res1; 27296a461dSNaveen Krishna Ch u32 usi_int_en; 28296a461dSNaveen Krishna Ch u32 usi_int_stat; 29296a461dSNaveen Krishna Ch u32 usi_modem_stat; 30296a461dSNaveen Krishna Ch u32 usi_error_stat; 31296a461dSNaveen Krishna Ch u32 usi_fifo_stat; 32296a461dSNaveen Krishna Ch u32 usi_txdata; 33296a461dSNaveen Krishna Ch u32 usi_rxdata; 34296a461dSNaveen Krishna Ch u32 res2; 35296a461dSNaveen Krishna Ch u32 usi_conf; 36296a461dSNaveen Krishna Ch u32 usi_auto_conf; 37296a461dSNaveen Krishna Ch u32 usi_timeout; 38296a461dSNaveen Krishna Ch u32 usi_manual_cmd; 39296a461dSNaveen Krishna Ch u32 usi_trans_status; 40296a461dSNaveen Krishna Ch u32 usi_timing_hs1; 41296a461dSNaveen Krishna Ch u32 usi_timing_hs2; 42296a461dSNaveen Krishna Ch u32 usi_timing_hs3; 43296a461dSNaveen Krishna Ch u32 usi_timing_fs1; 44296a461dSNaveen Krishna Ch u32 usi_timing_fs2; 45296a461dSNaveen Krishna Ch u32 usi_timing_fs3; 46296a461dSNaveen Krishna Ch u32 usi_timing_sla; 47296a461dSNaveen Krishna Ch u32 i2c_addr; 48296a461dSNaveen Krishna Ch }; 49296a461dSNaveen Krishna Ch 50a9d2ae70SRajeshwari Shinde struct s3c24x0_i2c_bus { 51940dd162SSimon Glass bool active; /* port is active and available */ 52a9d2ae70SRajeshwari Shinde int node; /* device tree node */ 53a9d2ae70SRajeshwari Shinde int bus_num; /* i2c bus number */ 54a9d2ae70SRajeshwari Shinde struct s3c24x0_i2c *regs; 55296a461dSNaveen Krishna Ch struct exynos5_hsi2c *hsregs; 56296a461dSNaveen Krishna Ch int is_highspeed; /* High speed type, rather than I2C */ 57296a461dSNaveen Krishna Ch unsigned clock_frequency; 58d04df3c6SRajeshwari Shinde int id; 59296a461dSNaveen Krishna Ch unsigned clk_cycle; 60296a461dSNaveen Krishna Ch unsigned clk_div; 61a9d2ae70SRajeshwari Shinde }; 62*37b8eb37SSimon Glass 63*37b8eb37SSimon Glass #define I2C_WRITE 0 64*37b8eb37SSimon Glass #define I2C_READ 1 65*37b8eb37SSimon Glass 66*37b8eb37SSimon Glass #define I2C_OK 0 67*37b8eb37SSimon Glass #define I2C_NOK 1 68*37b8eb37SSimon Glass #define I2C_NACK 2 69*37b8eb37SSimon Glass #define I2C_NOK_LA 3 /* Lost arbitration */ 70*37b8eb37SSimon Glass #define I2C_NOK_TOUT 4 /* time out */ 71*37b8eb37SSimon Glass 72*37b8eb37SSimon Glass /* S3C I2C Controller bits */ 73*37b8eb37SSimon Glass #define I2CSTAT_BSY 0x20 /* Busy bit */ 74*37b8eb37SSimon Glass #define I2CSTAT_NACK 0x01 /* Nack bit */ 75*37b8eb37SSimon Glass #define I2CCON_ACKGEN 0x80 /* Acknowledge generation */ 76*37b8eb37SSimon Glass #define I2CCON_IRPND 0x10 /* Interrupt pending bit */ 77*37b8eb37SSimon Glass #define I2C_MODE_MT 0xC0 /* Master Transmit Mode */ 78*37b8eb37SSimon Glass #define I2C_MODE_MR 0x80 /* Master Receive Mode */ 79*37b8eb37SSimon Glass #define I2C_START_STOP 0x20 /* START / STOP */ 80*37b8eb37SSimon Glass #define I2C_TXRX_ENA 0x10 /* I2C Tx/Rx enable */ 81*37b8eb37SSimon Glass 82*37b8eb37SSimon Glass #define I2C_TIMEOUT_MS 10 /* 10 ms */ 83*37b8eb37SSimon Glass 8491dffb16SRajeshwari Shinde #endif /* _S3C24X0_I2C_H */ 85