191dffb16SRajeshwari Shinde /* 291dffb16SRajeshwari Shinde * Copyright (C) 2012 Samsung Electronics 391dffb16SRajeshwari Shinde * 41a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 591dffb16SRajeshwari Shinde */ 691dffb16SRajeshwari Shinde 791dffb16SRajeshwari Shinde #ifndef _S3C24X0_I2C_H 891dffb16SRajeshwari Shinde #define _S3C24X0_I2C_H 991dffb16SRajeshwari Shinde 1091dffb16SRajeshwari Shinde struct s3c24x0_i2c { 1191dffb16SRajeshwari Shinde u32 iiccon; 1291dffb16SRajeshwari Shinde u32 iicstat; 1391dffb16SRajeshwari Shinde u32 iicadd; 1491dffb16SRajeshwari Shinde u32 iicds; 1591dffb16SRajeshwari Shinde u32 iiclc; 1691dffb16SRajeshwari Shinde }; 17a9d2ae70SRajeshwari Shinde 18*296a461dSNaveen Krishna Ch struct exynos5_hsi2c { 19*296a461dSNaveen Krishna Ch u32 usi_ctl; 20*296a461dSNaveen Krishna Ch u32 usi_fifo_ctl; 21*296a461dSNaveen Krishna Ch u32 usi_trailing_ctl; 22*296a461dSNaveen Krishna Ch u32 usi_clk_ctl; 23*296a461dSNaveen Krishna Ch u32 usi_clk_slot; 24*296a461dSNaveen Krishna Ch u32 spi_ctl; 25*296a461dSNaveen Krishna Ch u32 uart_ctl; 26*296a461dSNaveen Krishna Ch u32 res1; 27*296a461dSNaveen Krishna Ch u32 usi_int_en; 28*296a461dSNaveen Krishna Ch u32 usi_int_stat; 29*296a461dSNaveen Krishna Ch u32 usi_modem_stat; 30*296a461dSNaveen Krishna Ch u32 usi_error_stat; 31*296a461dSNaveen Krishna Ch u32 usi_fifo_stat; 32*296a461dSNaveen Krishna Ch u32 usi_txdata; 33*296a461dSNaveen Krishna Ch u32 usi_rxdata; 34*296a461dSNaveen Krishna Ch u32 res2; 35*296a461dSNaveen Krishna Ch u32 usi_conf; 36*296a461dSNaveen Krishna Ch u32 usi_auto_conf; 37*296a461dSNaveen Krishna Ch u32 usi_timeout; 38*296a461dSNaveen Krishna Ch u32 usi_manual_cmd; 39*296a461dSNaveen Krishna Ch u32 usi_trans_status; 40*296a461dSNaveen Krishna Ch u32 usi_timing_hs1; 41*296a461dSNaveen Krishna Ch u32 usi_timing_hs2; 42*296a461dSNaveen Krishna Ch u32 usi_timing_hs3; 43*296a461dSNaveen Krishna Ch u32 usi_timing_fs1; 44*296a461dSNaveen Krishna Ch u32 usi_timing_fs2; 45*296a461dSNaveen Krishna Ch u32 usi_timing_fs3; 46*296a461dSNaveen Krishna Ch u32 usi_timing_sla; 47*296a461dSNaveen Krishna Ch u32 i2c_addr; 48*296a461dSNaveen Krishna Ch }; 49*296a461dSNaveen Krishna Ch 50a9d2ae70SRajeshwari Shinde struct s3c24x0_i2c_bus { 51940dd162SSimon Glass bool active; /* port is active and available */ 52a9d2ae70SRajeshwari Shinde int node; /* device tree node */ 53a9d2ae70SRajeshwari Shinde int bus_num; /* i2c bus number */ 54a9d2ae70SRajeshwari Shinde struct s3c24x0_i2c *regs; 55*296a461dSNaveen Krishna Ch struct exynos5_hsi2c *hsregs; 56*296a461dSNaveen Krishna Ch int is_highspeed; /* High speed type, rather than I2C */ 57*296a461dSNaveen Krishna Ch unsigned clock_frequency; 58d04df3c6SRajeshwari Shinde int id; 59*296a461dSNaveen Krishna Ch unsigned clk_cycle; 60*296a461dSNaveen Krishna Ch unsigned clk_div; 61a9d2ae70SRajeshwari Shinde }; 6291dffb16SRajeshwari Shinde #endif /* _S3C24X0_I2C_H */ 63