1*83d290c5STom Rini /* SPDX-License-Identifier: GPL-2.0+ */ 291dffb16SRajeshwari Shinde /* 391dffb16SRajeshwari Shinde * Copyright (C) 2012 Samsung Electronics 491dffb16SRajeshwari Shinde */ 591dffb16SRajeshwari Shinde 691dffb16SRajeshwari Shinde #ifndef _S3C24X0_I2C_H 791dffb16SRajeshwari Shinde #define _S3C24X0_I2C_H 891dffb16SRajeshwari Shinde 991dffb16SRajeshwari Shinde struct s3c24x0_i2c { 1091dffb16SRajeshwari Shinde u32 iiccon; 1191dffb16SRajeshwari Shinde u32 iicstat; 1291dffb16SRajeshwari Shinde u32 iicadd; 1391dffb16SRajeshwari Shinde u32 iicds; 1491dffb16SRajeshwari Shinde u32 iiclc; 1591dffb16SRajeshwari Shinde }; 16a9d2ae70SRajeshwari Shinde 17296a461dSNaveen Krishna Ch struct exynos5_hsi2c { 18296a461dSNaveen Krishna Ch u32 usi_ctl; 19296a461dSNaveen Krishna Ch u32 usi_fifo_ctl; 20296a461dSNaveen Krishna Ch u32 usi_trailing_ctl; 21296a461dSNaveen Krishna Ch u32 usi_clk_ctl; 22296a461dSNaveen Krishna Ch u32 usi_clk_slot; 23296a461dSNaveen Krishna Ch u32 spi_ctl; 24296a461dSNaveen Krishna Ch u32 uart_ctl; 25296a461dSNaveen Krishna Ch u32 res1; 26296a461dSNaveen Krishna Ch u32 usi_int_en; 27296a461dSNaveen Krishna Ch u32 usi_int_stat; 28296a461dSNaveen Krishna Ch u32 usi_modem_stat; 29296a461dSNaveen Krishna Ch u32 usi_error_stat; 30296a461dSNaveen Krishna Ch u32 usi_fifo_stat; 31296a461dSNaveen Krishna Ch u32 usi_txdata; 32296a461dSNaveen Krishna Ch u32 usi_rxdata; 33296a461dSNaveen Krishna Ch u32 res2; 34296a461dSNaveen Krishna Ch u32 usi_conf; 35296a461dSNaveen Krishna Ch u32 usi_auto_conf; 36296a461dSNaveen Krishna Ch u32 usi_timeout; 37296a461dSNaveen Krishna Ch u32 usi_manual_cmd; 38296a461dSNaveen Krishna Ch u32 usi_trans_status; 39296a461dSNaveen Krishna Ch u32 usi_timing_hs1; 40296a461dSNaveen Krishna Ch u32 usi_timing_hs2; 41296a461dSNaveen Krishna Ch u32 usi_timing_hs3; 42296a461dSNaveen Krishna Ch u32 usi_timing_fs1; 43296a461dSNaveen Krishna Ch u32 usi_timing_fs2; 44296a461dSNaveen Krishna Ch u32 usi_timing_fs3; 45296a461dSNaveen Krishna Ch u32 usi_timing_sla; 46296a461dSNaveen Krishna Ch u32 i2c_addr; 47296a461dSNaveen Krishna Ch }; 48296a461dSNaveen Krishna Ch 49a9d2ae70SRajeshwari Shinde struct s3c24x0_i2c_bus { 50940dd162SSimon Glass bool active; /* port is active and available */ 51a9d2ae70SRajeshwari Shinde int node; /* device tree node */ 52a9d2ae70SRajeshwari Shinde int bus_num; /* i2c bus number */ 53a9d2ae70SRajeshwari Shinde struct s3c24x0_i2c *regs; 54296a461dSNaveen Krishna Ch struct exynos5_hsi2c *hsregs; 55296a461dSNaveen Krishna Ch int is_highspeed; /* High speed type, rather than I2C */ 56296a461dSNaveen Krishna Ch unsigned clock_frequency; 57d04df3c6SRajeshwari Shinde int id; 58296a461dSNaveen Krishna Ch unsigned clk_cycle; 59296a461dSNaveen Krishna Ch unsigned clk_div; 60a9d2ae70SRajeshwari Shinde }; 6137b8eb37SSimon Glass 6237b8eb37SSimon Glass #define I2C_WRITE 0 6337b8eb37SSimon Glass #define I2C_READ 1 6437b8eb37SSimon Glass 6537b8eb37SSimon Glass #define I2C_OK 0 6637b8eb37SSimon Glass #define I2C_NOK 1 6737b8eb37SSimon Glass #define I2C_NACK 2 6837b8eb37SSimon Glass #define I2C_NOK_LA 3 /* Lost arbitration */ 6937b8eb37SSimon Glass #define I2C_NOK_TOUT 4 /* time out */ 7037b8eb37SSimon Glass 7137b8eb37SSimon Glass /* S3C I2C Controller bits */ 7237b8eb37SSimon Glass #define I2CSTAT_BSY 0x20 /* Busy bit */ 7337b8eb37SSimon Glass #define I2CSTAT_NACK 0x01 /* Nack bit */ 7437b8eb37SSimon Glass #define I2CCON_ACKGEN 0x80 /* Acknowledge generation */ 7537b8eb37SSimon Glass #define I2CCON_IRPND 0x10 /* Interrupt pending bit */ 7637b8eb37SSimon Glass #define I2C_MODE_MT 0xC0 /* Master Transmit Mode */ 7737b8eb37SSimon Glass #define I2C_MODE_MR 0x80 /* Master Receive Mode */ 7837b8eb37SSimon Glass #define I2C_START_STOP 0x20 /* START / STOP */ 7937b8eb37SSimon Glass #define I2C_TXRX_ENA 0x10 /* I2C Tx/Rx enable */ 8037b8eb37SSimon Glass 8137b8eb37SSimon Glass #define I2C_TIMEOUT_MS 10 /* 10 ms */ 8237b8eb37SSimon Glass 8391dffb16SRajeshwari Shinde #endif /* _S3C24X0_I2C_H */ 84