1 /* 2 * (C) Copyright 2002 3 * David Mueller, ELSOFT AG, d.mueller@elsoft.ch 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* This code should work for both the S3C2400 and the S3C2410 9 * as they seem to have the same I2C controller inside. 10 * The different address mapping is handled by the s3c24xx.h files below. 11 */ 12 13 #include <common.h> 14 #include <fdtdec.h> 15 #if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) 16 #include <asm/arch/clk.h> 17 #include <asm/arch/cpu.h> 18 #include <asm/arch/pinmux.h> 19 #else 20 #include <asm/arch/s3c24x0_cpu.h> 21 #endif 22 #include <asm/io.h> 23 #include <i2c.h> 24 #include "s3c24x0_i2c.h" 25 26 #ifdef CONFIG_HARD_I2C 27 28 #define I2C_WRITE 0 29 #define I2C_READ 1 30 31 #define I2C_OK 0 32 #define I2C_NOK 1 33 #define I2C_NACK 2 34 #define I2C_NOK_LA 3 /* Lost arbitration */ 35 #define I2C_NOK_TOUT 4 /* time out */ 36 37 #define I2CSTAT_BSY 0x20 /* Busy bit */ 38 #define I2CSTAT_NACK 0x01 /* Nack bit */ 39 #define I2CCON_ACKGEN 0x80 /* Acknowledge generation */ 40 #define I2CCON_IRPND 0x10 /* Interrupt pending bit */ 41 #define I2C_MODE_MT 0xC0 /* Master Transmit Mode */ 42 #define I2C_MODE_MR 0x80 /* Master Receive Mode */ 43 #define I2C_START_STOP 0x20 /* START / STOP */ 44 #define I2C_TXRX_ENA 0x10 /* I2C Tx/Rx enable */ 45 46 #define I2C_TIMEOUT 1 /* 1 second */ 47 48 49 /* 50 * For SPL boot some boards need i2c before SDRAM is initialised so force 51 * variables to live in SRAM 52 */ 53 static unsigned int g_current_bus __attribute__((section(".data"))); 54 #ifdef CONFIG_OF_CONTROL 55 static int i2c_busses __attribute__((section(".data"))); 56 static struct s3c24x0_i2c_bus i2c_bus[CONFIG_MAX_I2C_NUM] 57 __attribute__((section(".data"))); 58 #endif 59 60 #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) 61 static int GetI2CSDA(void) 62 { 63 struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio(); 64 65 #ifdef CONFIG_S3C2410 66 return (readl(&gpio->gpedat) & 0x8000) >> 15; 67 #endif 68 #ifdef CONFIG_S3C2400 69 return (readl(&gpio->pgdat) & 0x0020) >> 5; 70 #endif 71 } 72 73 static void SetI2CSCL(int x) 74 { 75 struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio(); 76 77 #ifdef CONFIG_S3C2410 78 writel((readl(&gpio->gpedat) & ~0x4000) | 79 (x & 1) << 14, &gpio->gpedat); 80 #endif 81 #ifdef CONFIG_S3C2400 82 writel((readl(&gpio->pgdat) & ~0x0040) | (x & 1) << 6, &gpio->pgdat); 83 #endif 84 } 85 #endif 86 87 static int WaitForXfer(struct s3c24x0_i2c *i2c) 88 { 89 int i; 90 91 i = I2C_TIMEOUT * 10000; 92 while (!(readl(&i2c->iiccon) & I2CCON_IRPND) && (i > 0)) { 93 udelay(100); 94 i--; 95 } 96 97 return (readl(&i2c->iiccon) & I2CCON_IRPND) ? I2C_OK : I2C_NOK_TOUT; 98 } 99 100 static int IsACK(struct s3c24x0_i2c *i2c) 101 { 102 return !(readl(&i2c->iicstat) & I2CSTAT_NACK); 103 } 104 105 static void ReadWriteByte(struct s3c24x0_i2c *i2c) 106 { 107 writel(readl(&i2c->iiccon) & ~I2CCON_IRPND, &i2c->iiccon); 108 } 109 110 static struct s3c24x0_i2c *get_base_i2c(void) 111 { 112 #ifdef CONFIG_EXYNOS4 113 struct s3c24x0_i2c *i2c = (struct s3c24x0_i2c *)(samsung_get_base_i2c() 114 + (EXYNOS4_I2C_SPACING 115 * g_current_bus)); 116 return i2c; 117 #elif defined CONFIG_EXYNOS5 118 struct s3c24x0_i2c *i2c = (struct s3c24x0_i2c *)(samsung_get_base_i2c() 119 + (EXYNOS5_I2C_SPACING 120 * g_current_bus)); 121 return i2c; 122 #else 123 return s3c24x0_get_base_i2c(); 124 #endif 125 } 126 127 static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd) 128 { 129 ulong freq, pres = 16, div; 130 #if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) 131 freq = get_i2c_clk(); 132 #else 133 freq = get_PCLK(); 134 #endif 135 /* calculate prescaler and divisor values */ 136 if ((freq / pres / (16 + 1)) > speed) 137 /* set prescaler to 512 */ 138 pres = 512; 139 140 div = 0; 141 while ((freq / pres / (div + 1)) > speed) 142 div++; 143 144 /* set prescaler, divisor according to freq, also set ACKGEN, IRQ */ 145 writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c->iiccon); 146 147 /* init to SLAVE REVEIVE and set slaveaddr */ 148 writel(0, &i2c->iicstat); 149 writel(slaveadd, &i2c->iicadd); 150 /* program Master Transmit (and implicit STOP) */ 151 writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat); 152 } 153 154 /* 155 * MULTI BUS I2C support 156 */ 157 158 #ifdef CONFIG_I2C_MULTI_BUS 159 int i2c_set_bus_num(unsigned int bus) 160 { 161 struct s3c24x0_i2c *i2c; 162 163 if ((bus < 0) || (bus >= CONFIG_MAX_I2C_NUM)) { 164 debug("Bad bus: %d\n", bus); 165 return -1; 166 } 167 168 g_current_bus = bus; 169 i2c = get_base_i2c(); 170 i2c_ch_init(i2c, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 171 172 return 0; 173 } 174 175 unsigned int i2c_get_bus_num(void) 176 { 177 return g_current_bus; 178 } 179 #endif 180 181 void i2c_init(int speed, int slaveadd) 182 { 183 struct s3c24x0_i2c *i2c; 184 #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) 185 struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio(); 186 #endif 187 int i; 188 189 /* By default i2c channel 0 is the current bus */ 190 g_current_bus = 0; 191 i2c = get_base_i2c(); 192 193 /* wait for some time to give previous transfer a chance to finish */ 194 i = I2C_TIMEOUT * 1000; 195 while ((readl(&i2c->iicstat) & I2CSTAT_BSY) && (i > 0)) { 196 udelay(1000); 197 i--; 198 } 199 200 #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) 201 if ((readl(&i2c->iicstat) & I2CSTAT_BSY) || GetI2CSDA() == 0) { 202 #ifdef CONFIG_S3C2410 203 ulong old_gpecon = readl(&gpio->gpecon); 204 #endif 205 #ifdef CONFIG_S3C2400 206 ulong old_gpecon = readl(&gpio->pgcon); 207 #endif 208 /* bus still busy probably by (most) previously interrupted 209 transfer */ 210 211 #ifdef CONFIG_S3C2410 212 /* set I2CSDA and I2CSCL (GPE15, GPE14) to GPIO */ 213 writel((readl(&gpio->gpecon) & ~0xF0000000) | 0x10000000, 214 &gpio->gpecon); 215 #endif 216 #ifdef CONFIG_S3C2400 217 /* set I2CSDA and I2CSCL (PG5, PG6) to GPIO */ 218 writel((readl(&gpio->pgcon) & ~0x00003c00) | 0x00001000, 219 &gpio->pgcon); 220 #endif 221 222 /* toggle I2CSCL until bus idle */ 223 SetI2CSCL(0); 224 udelay(1000); 225 i = 10; 226 while ((i > 0) && (GetI2CSDA() != 1)) { 227 SetI2CSCL(1); 228 udelay(1000); 229 SetI2CSCL(0); 230 udelay(1000); 231 i--; 232 } 233 SetI2CSCL(1); 234 udelay(1000); 235 236 /* restore pin functions */ 237 #ifdef CONFIG_S3C2410 238 writel(old_gpecon, &gpio->gpecon); 239 #endif 240 #ifdef CONFIG_S3C2400 241 writel(old_gpecon, &gpio->pgcon); 242 #endif 243 } 244 #endif /* #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) */ 245 i2c_ch_init(i2c, speed, slaveadd); 246 } 247 248 /* 249 * cmd_type is 0 for write, 1 for read. 250 * 251 * addr_len can take any value from 0-255, it is only limited 252 * by the char, we could make it larger if needed. If it is 253 * 0 we skip the address write cycle. 254 */ 255 static int i2c_transfer(struct s3c24x0_i2c *i2c, 256 unsigned char cmd_type, 257 unsigned char chip, 258 unsigned char addr[], 259 unsigned char addr_len, 260 unsigned char data[], 261 unsigned short data_len) 262 { 263 int i, result; 264 265 if (data == 0 || data_len == 0) { 266 /*Don't support data transfer of no length or to address 0 */ 267 debug("i2c_transfer: bad call\n"); 268 return I2C_NOK; 269 } 270 271 /* Check I2C bus idle */ 272 i = I2C_TIMEOUT * 1000; 273 while ((readl(&i2c->iicstat) & I2CSTAT_BSY) && (i > 0)) { 274 udelay(1000); 275 i--; 276 } 277 278 if (readl(&i2c->iicstat) & I2CSTAT_BSY) 279 return I2C_NOK_TOUT; 280 281 writel(readl(&i2c->iiccon) | I2CCON_ACKGEN, &i2c->iiccon); 282 result = I2C_OK; 283 284 switch (cmd_type) { 285 case I2C_WRITE: 286 if (addr && addr_len) { 287 writel(chip, &i2c->iicds); 288 /* send START */ 289 writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP, 290 &i2c->iicstat); 291 i = 0; 292 while ((i < addr_len) && (result == I2C_OK)) { 293 result = WaitForXfer(i2c); 294 writel(addr[i], &i2c->iicds); 295 ReadWriteByte(i2c); 296 i++; 297 } 298 i = 0; 299 while ((i < data_len) && (result == I2C_OK)) { 300 result = WaitForXfer(i2c); 301 writel(data[i], &i2c->iicds); 302 ReadWriteByte(i2c); 303 i++; 304 } 305 } else { 306 writel(chip, &i2c->iicds); 307 /* send START */ 308 writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP, 309 &i2c->iicstat); 310 i = 0; 311 while ((i < data_len) && (result == I2C_OK)) { 312 result = WaitForXfer(i2c); 313 writel(data[i], &i2c->iicds); 314 ReadWriteByte(i2c); 315 i++; 316 } 317 } 318 319 if (result == I2C_OK) 320 result = WaitForXfer(i2c); 321 322 /* send STOP */ 323 writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat); 324 ReadWriteByte(i2c); 325 break; 326 327 case I2C_READ: 328 if (addr && addr_len) { 329 writel(chip, &i2c->iicds); 330 /* send START */ 331 writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP, 332 &i2c->iicstat); 333 result = WaitForXfer(i2c); 334 if (IsACK(i2c)) { 335 i = 0; 336 while ((i < addr_len) && (result == I2C_OK)) { 337 writel(addr[i], &i2c->iicds); 338 ReadWriteByte(i2c); 339 result = WaitForXfer(i2c); 340 i++; 341 } 342 343 writel(chip, &i2c->iicds); 344 /* resend START */ 345 writel(I2C_MODE_MR | I2C_TXRX_ENA | 346 I2C_START_STOP, &i2c->iicstat); 347 ReadWriteByte(i2c); 348 result = WaitForXfer(i2c); 349 i = 0; 350 while ((i < data_len) && (result == I2C_OK)) { 351 /* disable ACK for final READ */ 352 if (i == data_len - 1) 353 writel(readl(&i2c->iiccon) 354 & ~I2CCON_ACKGEN, 355 &i2c->iiccon); 356 ReadWriteByte(i2c); 357 result = WaitForXfer(i2c); 358 data[i] = readl(&i2c->iicds); 359 i++; 360 } 361 } else { 362 result = I2C_NACK; 363 } 364 365 } else { 366 writel(chip, &i2c->iicds); 367 /* send START */ 368 writel(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP, 369 &i2c->iicstat); 370 result = WaitForXfer(i2c); 371 372 if (IsACK(i2c)) { 373 i = 0; 374 while ((i < data_len) && (result == I2C_OK)) { 375 /* disable ACK for final READ */ 376 if (i == data_len - 1) 377 writel(readl(&i2c->iiccon) & 378 ~I2CCON_ACKGEN, 379 &i2c->iiccon); 380 ReadWriteByte(i2c); 381 result = WaitForXfer(i2c); 382 data[i] = readl(&i2c->iicds); 383 i++; 384 } 385 } else { 386 result = I2C_NACK; 387 } 388 } 389 390 /* send STOP */ 391 writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat); 392 ReadWriteByte(i2c); 393 break; 394 395 default: 396 debug("i2c_transfer: bad call\n"); 397 result = I2C_NOK; 398 break; 399 } 400 401 return result; 402 } 403 404 int i2c_probe(uchar chip) 405 { 406 struct s3c24x0_i2c *i2c; 407 uchar buf[1]; 408 409 i2c = get_base_i2c(); 410 buf[0] = 0; 411 412 /* 413 * What is needed is to send the chip address and verify that the 414 * address was <ACK>ed (i.e. there was a chip at that address which 415 * drove the data line low). 416 */ 417 return i2c_transfer(i2c, I2C_READ, chip << 1, 0, 0, buf, 1) != I2C_OK; 418 } 419 420 int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) 421 { 422 struct s3c24x0_i2c *i2c; 423 uchar xaddr[4]; 424 int ret; 425 426 if (alen > 4) { 427 debug("I2C read: addr len %d not supported\n", alen); 428 return 1; 429 } 430 431 if (alen > 0) { 432 xaddr[0] = (addr >> 24) & 0xFF; 433 xaddr[1] = (addr >> 16) & 0xFF; 434 xaddr[2] = (addr >> 8) & 0xFF; 435 xaddr[3] = addr & 0xFF; 436 } 437 438 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 439 /* 440 * EEPROM chips that implement "address overflow" are ones 441 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of 442 * address and the extra bits end up in the "chip address" 443 * bit slots. This makes a 24WC08 (1Kbyte) chip look like 444 * four 256 byte chips. 445 * 446 * Note that we consider the length of the address field to 447 * still be one byte because the extra address bits are 448 * hidden in the chip address. 449 */ 450 if (alen > 0) 451 chip |= ((addr >> (alen * 8)) & 452 CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); 453 #endif 454 i2c = get_base_i2c(); 455 ret = i2c_transfer(i2c, I2C_READ, chip << 1, &xaddr[4 - alen], alen, 456 buffer, len); 457 if (ret != 0) { 458 debug("I2c read: failed %d\n", ret); 459 return 1; 460 } 461 return 0; 462 } 463 464 int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) 465 { 466 struct s3c24x0_i2c *i2c; 467 uchar xaddr[4]; 468 469 if (alen > 4) { 470 debug("I2C write: addr len %d not supported\n", alen); 471 return 1; 472 } 473 474 if (alen > 0) { 475 xaddr[0] = (addr >> 24) & 0xFF; 476 xaddr[1] = (addr >> 16) & 0xFF; 477 xaddr[2] = (addr >> 8) & 0xFF; 478 xaddr[3] = addr & 0xFF; 479 } 480 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 481 /* 482 * EEPROM chips that implement "address overflow" are ones 483 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of 484 * address and the extra bits end up in the "chip address" 485 * bit slots. This makes a 24WC08 (1Kbyte) chip look like 486 * four 256 byte chips. 487 * 488 * Note that we consider the length of the address field to 489 * still be one byte because the extra address bits are 490 * hidden in the chip address. 491 */ 492 if (alen > 0) 493 chip |= ((addr >> (alen * 8)) & 494 CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); 495 #endif 496 i2c = get_base_i2c(); 497 return (i2c_transfer 498 (i2c, I2C_WRITE, chip << 1, &xaddr[4 - alen], alen, buffer, 499 len) != 0); 500 } 501 502 #ifdef CONFIG_OF_CONTROL 503 void board_i2c_init(const void *blob) 504 { 505 int i; 506 int node_list[CONFIG_MAX_I2C_NUM]; 507 int count; 508 509 count = fdtdec_find_aliases_for_id(blob, "i2c", 510 COMPAT_SAMSUNG_S3C2440_I2C, node_list, 511 CONFIG_MAX_I2C_NUM); 512 513 for (i = 0; i < count; i++) { 514 struct s3c24x0_i2c_bus *bus; 515 int node = node_list[i]; 516 517 if (node <= 0) 518 continue; 519 bus = &i2c_bus[i]; 520 bus->regs = (struct s3c24x0_i2c *) 521 fdtdec_get_addr(blob, node, "reg"); 522 bus->id = pinmux_decode_periph_id(blob, node); 523 bus->node = node; 524 bus->bus_num = i2c_busses++; 525 exynos_pinmux_config(bus->id, 0); 526 } 527 } 528 529 static struct s3c24x0_i2c_bus *get_bus(unsigned int bus_idx) 530 { 531 if (bus_idx < i2c_busses) 532 return &i2c_bus[bus_idx]; 533 534 debug("Undefined bus: %d\n", bus_idx); 535 return NULL; 536 } 537 538 int i2c_get_bus_num_fdt(int node) 539 { 540 int i; 541 542 for (i = 0; i < i2c_busses; i++) { 543 if (node == i2c_bus[i].node) 544 return i; 545 } 546 547 debug("%s: Can't find any matched I2C bus\n", __func__); 548 return -1; 549 } 550 551 int i2c_reset_port_fdt(const void *blob, int node) 552 { 553 struct s3c24x0_i2c_bus *i2c; 554 int bus; 555 556 bus = i2c_get_bus_num_fdt(node); 557 if (bus < 0) { 558 debug("could not get bus for node %d\n", node); 559 return -1; 560 } 561 562 i2c = get_bus(bus); 563 if (!i2c) { 564 debug("get_bus() failed for node node %d\n", node); 565 return -1; 566 } 567 568 i2c_ch_init(i2c->regs, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 569 570 return 0; 571 } 572 #endif 573 574 #endif /* CONFIG_HARD_I2C */ 575