1 /* 2 * (C) Copyright 2002 3 * David Mueller, ELSOFT AG, d.mueller@elsoft.ch 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 /* This code should work for both the S3C2400 and the S3C2410 25 * as they seem to have the same I2C controller inside. 26 * The different address mapping is handled by the s3c24xx.h files below. 27 */ 28 29 #include <common.h> 30 #include <fdtdec.h> 31 #if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) 32 #include <asm/arch/clk.h> 33 #include <asm/arch/cpu.h> 34 #include <asm/arch/pinmux.h> 35 #else 36 #include <asm/arch/s3c24x0_cpu.h> 37 #endif 38 #include <asm/io.h> 39 #include <i2c.h> 40 #include "s3c24x0_i2c.h" 41 42 #ifdef CONFIG_HARD_I2C 43 44 #define I2C_WRITE 0 45 #define I2C_READ 1 46 47 #define I2C_OK 0 48 #define I2C_NOK 1 49 #define I2C_NACK 2 50 #define I2C_NOK_LA 3 /* Lost arbitration */ 51 #define I2C_NOK_TOUT 4 /* time out */ 52 53 #define I2CSTAT_BSY 0x20 /* Busy bit */ 54 #define I2CSTAT_NACK 0x01 /* Nack bit */ 55 #define I2CCON_ACKGEN 0x80 /* Acknowledge generation */ 56 #define I2CCON_IRPND 0x10 /* Interrupt pending bit */ 57 #define I2C_MODE_MT 0xC0 /* Master Transmit Mode */ 58 #define I2C_MODE_MR 0x80 /* Master Receive Mode */ 59 #define I2C_START_STOP 0x20 /* START / STOP */ 60 #define I2C_TXRX_ENA 0x10 /* I2C Tx/Rx enable */ 61 62 #define I2C_TIMEOUT 1 /* 1 second */ 63 64 65 /* 66 * For SPL boot some boards need i2c before SDRAM is initialised so force 67 * variables to live in SRAM 68 */ 69 static unsigned int g_current_bus __attribute__((section(".data"))); 70 #ifdef CONFIG_OF_CONTROL 71 static int i2c_busses __attribute__((section(".data"))); 72 static struct s3c24x0_i2c_bus i2c_bus[CONFIG_MAX_I2C_NUM] 73 __attribute__((section(".data"))); 74 #endif 75 76 #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) 77 static int GetI2CSDA(void) 78 { 79 struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio(); 80 81 #ifdef CONFIG_S3C2410 82 return (readl(&gpio->gpedat) & 0x8000) >> 15; 83 #endif 84 #ifdef CONFIG_S3C2400 85 return (readl(&gpio->pgdat) & 0x0020) >> 5; 86 #endif 87 } 88 89 #if 0 90 static void SetI2CSDA(int x) 91 { 92 rGPEDAT = (rGPEDAT & ~0x8000) | (x & 1) << 15; 93 } 94 #endif 95 96 static void SetI2CSCL(int x) 97 { 98 struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio(); 99 100 #ifdef CONFIG_S3C2410 101 writel((readl(&gpio->gpedat) & ~0x4000) | 102 (x & 1) << 14, &gpio->gpedat); 103 #endif 104 #ifdef CONFIG_S3C2400 105 writel((readl(&gpio->pgdat) & ~0x0040) | (x & 1) << 6, &gpio->pgdat); 106 #endif 107 } 108 #endif 109 110 static int WaitForXfer(struct s3c24x0_i2c *i2c) 111 { 112 int i; 113 114 i = I2C_TIMEOUT * 10000; 115 while (!(readl(&i2c->iiccon) & I2CCON_IRPND) && (i > 0)) { 116 udelay(100); 117 i--; 118 } 119 120 return (readl(&i2c->iiccon) & I2CCON_IRPND) ? I2C_OK : I2C_NOK_TOUT; 121 } 122 123 static int IsACK(struct s3c24x0_i2c *i2c) 124 { 125 return !(readl(&i2c->iicstat) & I2CSTAT_NACK); 126 } 127 128 static void ReadWriteByte(struct s3c24x0_i2c *i2c) 129 { 130 writel(readl(&i2c->iiccon) & ~I2CCON_IRPND, &i2c->iiccon); 131 } 132 133 static struct s3c24x0_i2c *get_base_i2c(void) 134 { 135 #ifdef CONFIG_EXYNOS4 136 struct s3c24x0_i2c *i2c = (struct s3c24x0_i2c *)(samsung_get_base_i2c() 137 + (EXYNOS4_I2C_SPACING 138 * g_current_bus)); 139 return i2c; 140 #elif defined CONFIG_EXYNOS5 141 struct s3c24x0_i2c *i2c = (struct s3c24x0_i2c *)(samsung_get_base_i2c() 142 + (EXYNOS5_I2C_SPACING 143 * g_current_bus)); 144 return i2c; 145 #else 146 return s3c24x0_get_base_i2c(); 147 #endif 148 } 149 150 static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd) 151 { 152 ulong freq, pres = 16, div; 153 #if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) 154 freq = get_i2c_clk(); 155 #else 156 freq = get_PCLK(); 157 #endif 158 /* calculate prescaler and divisor values */ 159 if ((freq / pres / (16 + 1)) > speed) 160 /* set prescaler to 512 */ 161 pres = 512; 162 163 div = 0; 164 while ((freq / pres / (div + 1)) > speed) 165 div++; 166 167 /* set prescaler, divisor according to freq, also set ACKGEN, IRQ */ 168 writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c->iiccon); 169 170 /* init to SLAVE REVEIVE and set slaveaddr */ 171 writel(0, &i2c->iicstat); 172 writel(slaveadd, &i2c->iicadd); 173 /* program Master Transmit (and implicit STOP) */ 174 writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat); 175 } 176 177 /* 178 * MULTI BUS I2C support 179 */ 180 181 #ifdef CONFIG_I2C_MULTI_BUS 182 int i2c_set_bus_num(unsigned int bus) 183 { 184 struct s3c24x0_i2c *i2c; 185 186 if ((bus < 0) || (bus >= CONFIG_MAX_I2C_NUM)) { 187 debug("Bad bus: %d\n", bus); 188 return -1; 189 } 190 191 g_current_bus = bus; 192 i2c = get_base_i2c(); 193 i2c_ch_init(i2c, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 194 195 return 0; 196 } 197 198 unsigned int i2c_get_bus_num(void) 199 { 200 return g_current_bus; 201 } 202 #endif 203 204 void i2c_init(int speed, int slaveadd) 205 { 206 struct s3c24x0_i2c *i2c; 207 #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) 208 struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio(); 209 #endif 210 int i; 211 212 /* By default i2c channel 0 is the current bus */ 213 g_current_bus = 0; 214 i2c = get_base_i2c(); 215 216 /* wait for some time to give previous transfer a chance to finish */ 217 i = I2C_TIMEOUT * 1000; 218 while ((readl(&i2c->iicstat) & I2CSTAT_BSY) && (i > 0)) { 219 udelay(1000); 220 i--; 221 } 222 223 #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) 224 if ((readl(&i2c->iicstat) & I2CSTAT_BSY) || GetI2CSDA() == 0) { 225 #ifdef CONFIG_S3C2410 226 ulong old_gpecon = readl(&gpio->gpecon); 227 #endif 228 #ifdef CONFIG_S3C2400 229 ulong old_gpecon = readl(&gpio->pgcon); 230 #endif 231 /* bus still busy probably by (most) previously interrupted 232 transfer */ 233 234 #ifdef CONFIG_S3C2410 235 /* set I2CSDA and I2CSCL (GPE15, GPE14) to GPIO */ 236 writel((readl(&gpio->gpecon) & ~0xF0000000) | 0x10000000, 237 &gpio->gpecon); 238 #endif 239 #ifdef CONFIG_S3C2400 240 /* set I2CSDA and I2CSCL (PG5, PG6) to GPIO */ 241 writel((readl(&gpio->pgcon) & ~0x00003c00) | 0x00001000, 242 &gpio->pgcon); 243 #endif 244 245 /* toggle I2CSCL until bus idle */ 246 SetI2CSCL(0); 247 udelay(1000); 248 i = 10; 249 while ((i > 0) && (GetI2CSDA() != 1)) { 250 SetI2CSCL(1); 251 udelay(1000); 252 SetI2CSCL(0); 253 udelay(1000); 254 i--; 255 } 256 SetI2CSCL(1); 257 udelay(1000); 258 259 /* restore pin functions */ 260 #ifdef CONFIG_S3C2410 261 writel(old_gpecon, &gpio->gpecon); 262 #endif 263 #ifdef CONFIG_S3C2400 264 writel(old_gpecon, &gpio->pgcon); 265 #endif 266 } 267 #endif /* #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) */ 268 i2c_ch_init(i2c, speed, slaveadd); 269 } 270 271 /* 272 * cmd_type is 0 for write, 1 for read. 273 * 274 * addr_len can take any value from 0-255, it is only limited 275 * by the char, we could make it larger if needed. If it is 276 * 0 we skip the address write cycle. 277 */ 278 static int i2c_transfer(struct s3c24x0_i2c *i2c, 279 unsigned char cmd_type, 280 unsigned char chip, 281 unsigned char addr[], 282 unsigned char addr_len, 283 unsigned char data[], 284 unsigned short data_len) 285 { 286 int i, result; 287 288 if (data == 0 || data_len == 0) { 289 /*Don't support data transfer of no length or to address 0 */ 290 debug("i2c_transfer: bad call\n"); 291 return I2C_NOK; 292 } 293 294 /* Check I2C bus idle */ 295 i = I2C_TIMEOUT * 1000; 296 while ((readl(&i2c->iicstat) & I2CSTAT_BSY) && (i > 0)) { 297 udelay(1000); 298 i--; 299 } 300 301 if (readl(&i2c->iicstat) & I2CSTAT_BSY) 302 return I2C_NOK_TOUT; 303 304 writel(readl(&i2c->iiccon) | I2CCON_ACKGEN, &i2c->iiccon); 305 result = I2C_OK; 306 307 switch (cmd_type) { 308 case I2C_WRITE: 309 if (addr && addr_len) { 310 writel(chip, &i2c->iicds); 311 /* send START */ 312 writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP, 313 &i2c->iicstat); 314 i = 0; 315 while ((i < addr_len) && (result == I2C_OK)) { 316 result = WaitForXfer(i2c); 317 writel(addr[i], &i2c->iicds); 318 ReadWriteByte(i2c); 319 i++; 320 } 321 i = 0; 322 while ((i < data_len) && (result == I2C_OK)) { 323 result = WaitForXfer(i2c); 324 writel(data[i], &i2c->iicds); 325 ReadWriteByte(i2c); 326 i++; 327 } 328 } else { 329 writel(chip, &i2c->iicds); 330 /* send START */ 331 writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP, 332 &i2c->iicstat); 333 i = 0; 334 while ((i < data_len) && (result = I2C_OK)) { 335 result = WaitForXfer(i2c); 336 writel(data[i], &i2c->iicds); 337 ReadWriteByte(i2c); 338 i++; 339 } 340 } 341 342 if (result == I2C_OK) 343 result = WaitForXfer(i2c); 344 345 /* send STOP */ 346 writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat); 347 ReadWriteByte(i2c); 348 break; 349 350 case I2C_READ: 351 if (addr && addr_len) { 352 writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat); 353 writel(chip, &i2c->iicds); 354 /* send START */ 355 writel(readl(&i2c->iicstat) | I2C_START_STOP, 356 &i2c->iicstat); 357 result = WaitForXfer(i2c); 358 if (IsACK(i2c)) { 359 i = 0; 360 while ((i < addr_len) && (result == I2C_OK)) { 361 writel(addr[i], &i2c->iicds); 362 ReadWriteByte(i2c); 363 result = WaitForXfer(i2c); 364 i++; 365 } 366 367 writel(chip, &i2c->iicds); 368 /* resend START */ 369 writel(I2C_MODE_MR | I2C_TXRX_ENA | 370 I2C_START_STOP, &i2c->iicstat); 371 ReadWriteByte(i2c); 372 result = WaitForXfer(i2c); 373 i = 0; 374 while ((i < data_len) && (result == I2C_OK)) { 375 /* disable ACK for final READ */ 376 if (i == data_len - 1) 377 writel(readl(&i2c->iiccon) 378 & ~I2CCON_ACKGEN, 379 &i2c->iiccon); 380 ReadWriteByte(i2c); 381 result = WaitForXfer(i2c); 382 data[i] = readl(&i2c->iicds); 383 i++; 384 } 385 } else { 386 result = I2C_NACK; 387 } 388 389 } else { 390 writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat); 391 writel(chip, &i2c->iicds); 392 /* send START */ 393 writel(readl(&i2c->iicstat) | I2C_START_STOP, 394 &i2c->iicstat); 395 result = WaitForXfer(i2c); 396 397 if (IsACK(i2c)) { 398 i = 0; 399 while ((i < data_len) && (result == I2C_OK)) { 400 /* disable ACK for final READ */ 401 if (i == data_len - 1) 402 writel(readl(&i2c->iiccon) & 403 ~I2CCON_ACKGEN, 404 &i2c->iiccon); 405 ReadWriteByte(i2c); 406 result = WaitForXfer(i2c); 407 data[i] = readl(&i2c->iicds); 408 i++; 409 } 410 } else { 411 result = I2C_NACK; 412 } 413 } 414 415 /* send STOP */ 416 writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat); 417 ReadWriteByte(i2c); 418 break; 419 420 default: 421 debug("i2c_transfer: bad call\n"); 422 result = I2C_NOK; 423 break; 424 } 425 426 return result; 427 } 428 429 int i2c_probe(uchar chip) 430 { 431 struct s3c24x0_i2c *i2c; 432 uchar buf[1]; 433 434 i2c = get_base_i2c(); 435 buf[0] = 0; 436 437 /* 438 * What is needed is to send the chip address and verify that the 439 * address was <ACK>ed (i.e. there was a chip at that address which 440 * drove the data line low). 441 */ 442 return i2c_transfer(i2c, I2C_READ, chip << 1, 0, 0, buf, 1) != I2C_OK; 443 } 444 445 int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) 446 { 447 struct s3c24x0_i2c *i2c; 448 uchar xaddr[4]; 449 int ret; 450 451 if (alen > 4) { 452 debug("I2C read: addr len %d not supported\n", alen); 453 return 1; 454 } 455 456 if (alen > 0) { 457 xaddr[0] = (addr >> 24) & 0xFF; 458 xaddr[1] = (addr >> 16) & 0xFF; 459 xaddr[2] = (addr >> 8) & 0xFF; 460 xaddr[3] = addr & 0xFF; 461 } 462 463 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 464 /* 465 * EEPROM chips that implement "address overflow" are ones 466 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of 467 * address and the extra bits end up in the "chip address" 468 * bit slots. This makes a 24WC08 (1Kbyte) chip look like 469 * four 256 byte chips. 470 * 471 * Note that we consider the length of the address field to 472 * still be one byte because the extra address bits are 473 * hidden in the chip address. 474 */ 475 if (alen > 0) 476 chip |= ((addr >> (alen * 8)) & 477 CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); 478 #endif 479 i2c = get_base_i2c(); 480 ret = i2c_transfer(i2c, I2C_READ, chip << 1, &xaddr[4 - alen], alen, 481 buffer, len); 482 if (ret != 0) { 483 debug("I2c read: failed %d\n", ret); 484 return 1; 485 } 486 return 0; 487 } 488 489 int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) 490 { 491 struct s3c24x0_i2c *i2c; 492 uchar xaddr[4]; 493 494 if (alen > 4) { 495 debug("I2C write: addr len %d not supported\n", alen); 496 return 1; 497 } 498 499 if (alen > 0) { 500 xaddr[0] = (addr >> 24) & 0xFF; 501 xaddr[1] = (addr >> 16) & 0xFF; 502 xaddr[2] = (addr >> 8) & 0xFF; 503 xaddr[3] = addr & 0xFF; 504 } 505 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 506 /* 507 * EEPROM chips that implement "address overflow" are ones 508 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of 509 * address and the extra bits end up in the "chip address" 510 * bit slots. This makes a 24WC08 (1Kbyte) chip look like 511 * four 256 byte chips. 512 * 513 * Note that we consider the length of the address field to 514 * still be one byte because the extra address bits are 515 * hidden in the chip address. 516 */ 517 if (alen > 0) 518 chip |= ((addr >> (alen * 8)) & 519 CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); 520 #endif 521 i2c = get_base_i2c(); 522 return (i2c_transfer 523 (i2c, I2C_WRITE, chip << 1, &xaddr[4 - alen], alen, buffer, 524 len) != 0); 525 } 526 527 #ifdef CONFIG_OF_CONTROL 528 void board_i2c_init(const void *blob) 529 { 530 int node_list[CONFIG_MAX_I2C_NUM]; 531 int count, i; 532 533 count = fdtdec_find_aliases_for_id(blob, "i2c", 534 COMPAT_SAMSUNG_S3C2440_I2C, node_list, 535 CONFIG_MAX_I2C_NUM); 536 537 for (i = 0; i < count; i++) { 538 struct s3c24x0_i2c_bus *bus; 539 int node = node_list[i]; 540 541 if (node <= 0) 542 continue; 543 bus = &i2c_bus[i]; 544 bus->regs = (struct s3c24x0_i2c *) 545 fdtdec_get_addr(blob, node, "reg"); 546 bus->id = pinmux_decode_periph_id(blob, node); 547 bus->node = node; 548 bus->bus_num = i2c_busses++; 549 exynos_pinmux_config(bus->id, 0); 550 } 551 } 552 553 static struct s3c24x0_i2c_bus *get_bus(unsigned int bus_idx) 554 { 555 if (bus_idx < i2c_busses) 556 return &i2c_bus[bus_idx]; 557 558 debug("Undefined bus: %d\n", bus_idx); 559 return NULL; 560 } 561 562 int i2c_get_bus_num_fdt(int node) 563 { 564 int i; 565 566 for (i = 0; i < i2c_busses; i++) { 567 if (node == i2c_bus[i].node) 568 return i; 569 } 570 571 debug("%s: Can't find any matched I2C bus\n", __func__); 572 return -1; 573 } 574 575 int i2c_reset_port_fdt(const void *blob, int node) 576 { 577 struct s3c24x0_i2c_bus *i2c; 578 int bus; 579 580 bus = i2c_get_bus_num_fdt(node); 581 if (bus < 0) { 582 debug("could not get bus for node %d\n", node); 583 return -1; 584 } 585 586 i2c = get_bus(bus); 587 if (!i2c) { 588 debug("get_bus() failed for node node %d\n", node); 589 return -1; 590 } 591 592 i2c_ch_init(i2c->regs, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 593 594 return 0; 595 } 596 #endif 597 598 #endif /* CONFIG_HARD_I2C */ 599