1 /* 2 * (C) Copyright 2002 3 * David Mueller, ELSOFT AG, d.mueller@elsoft.ch 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 /* This code should work for both the S3C2400 and the S3C2410 25 * as they seem to have the same I2C controller inside. 26 * The different address mapping is handled by the s3c24xx.h files below. 27 */ 28 29 #include <common.h> 30 #include <fdtdec.h> 31 #if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) 32 #include <asm/arch/clk.h> 33 #include <asm/arch/cpu.h> 34 #include <asm/arch/pinmux.h> 35 #else 36 #include <asm/arch/s3c24x0_cpu.h> 37 #endif 38 #include <asm/io.h> 39 #include <i2c.h> 40 #include "s3c24x0_i2c.h" 41 42 #ifdef CONFIG_HARD_I2C 43 44 #define I2C_WRITE 0 45 #define I2C_READ 1 46 47 #define I2C_OK 0 48 #define I2C_NOK 1 49 #define I2C_NACK 2 50 #define I2C_NOK_LA 3 /* Lost arbitration */ 51 #define I2C_NOK_TOUT 4 /* time out */ 52 53 #define I2CSTAT_BSY 0x20 /* Busy bit */ 54 #define I2CSTAT_NACK 0x01 /* Nack bit */ 55 #define I2CCON_ACKGEN 0x80 /* Acknowledge generation */ 56 #define I2CCON_IRPND 0x10 /* Interrupt pending bit */ 57 #define I2C_MODE_MT 0xC0 /* Master Transmit Mode */ 58 #define I2C_MODE_MR 0x80 /* Master Receive Mode */ 59 #define I2C_START_STOP 0x20 /* START / STOP */ 60 #define I2C_TXRX_ENA 0x10 /* I2C Tx/Rx enable */ 61 62 #define I2C_TIMEOUT 1 /* 1 second */ 63 64 65 /* 66 * For SPL boot some boards need i2c before SDRAM is initialised so force 67 * variables to live in SRAM 68 */ 69 static unsigned int g_current_bus __attribute__((section(".data"))); 70 #ifdef CONFIG_OF_CONTROL 71 static int i2c_busses __attribute__((section(".data"))); 72 static struct s3c24x0_i2c_bus i2c_bus[CONFIG_MAX_I2C_NUM] 73 __attribute__((section(".data"))); 74 #endif 75 76 #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) 77 static int GetI2CSDA(void) 78 { 79 struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio(); 80 81 #ifdef CONFIG_S3C2410 82 return (readl(&gpio->gpedat) & 0x8000) >> 15; 83 #endif 84 #ifdef CONFIG_S3C2400 85 return (readl(&gpio->pgdat) & 0x0020) >> 5; 86 #endif 87 } 88 89 static void SetI2CSCL(int x) 90 { 91 struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio(); 92 93 #ifdef CONFIG_S3C2410 94 writel((readl(&gpio->gpedat) & ~0x4000) | 95 (x & 1) << 14, &gpio->gpedat); 96 #endif 97 #ifdef CONFIG_S3C2400 98 writel((readl(&gpio->pgdat) & ~0x0040) | (x & 1) << 6, &gpio->pgdat); 99 #endif 100 } 101 #endif 102 103 static int WaitForXfer(struct s3c24x0_i2c *i2c) 104 { 105 int i; 106 107 i = I2C_TIMEOUT * 10000; 108 while (!(readl(&i2c->iiccon) & I2CCON_IRPND) && (i > 0)) { 109 udelay(100); 110 i--; 111 } 112 113 return (readl(&i2c->iiccon) & I2CCON_IRPND) ? I2C_OK : I2C_NOK_TOUT; 114 } 115 116 static int IsACK(struct s3c24x0_i2c *i2c) 117 { 118 return !(readl(&i2c->iicstat) & I2CSTAT_NACK); 119 } 120 121 static void ReadWriteByte(struct s3c24x0_i2c *i2c) 122 { 123 writel(readl(&i2c->iiccon) & ~I2CCON_IRPND, &i2c->iiccon); 124 } 125 126 static struct s3c24x0_i2c *get_base_i2c(void) 127 { 128 #ifdef CONFIG_EXYNOS4 129 struct s3c24x0_i2c *i2c = (struct s3c24x0_i2c *)(samsung_get_base_i2c() 130 + (EXYNOS4_I2C_SPACING 131 * g_current_bus)); 132 return i2c; 133 #elif defined CONFIG_EXYNOS5 134 struct s3c24x0_i2c *i2c = (struct s3c24x0_i2c *)(samsung_get_base_i2c() 135 + (EXYNOS5_I2C_SPACING 136 * g_current_bus)); 137 return i2c; 138 #else 139 return s3c24x0_get_base_i2c(); 140 #endif 141 } 142 143 static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd) 144 { 145 ulong freq, pres = 16, div; 146 #if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) 147 freq = get_i2c_clk(); 148 #else 149 freq = get_PCLK(); 150 #endif 151 /* calculate prescaler and divisor values */ 152 if ((freq / pres / (16 + 1)) > speed) 153 /* set prescaler to 512 */ 154 pres = 512; 155 156 div = 0; 157 while ((freq / pres / (div + 1)) > speed) 158 div++; 159 160 /* set prescaler, divisor according to freq, also set ACKGEN, IRQ */ 161 writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c->iiccon); 162 163 /* init to SLAVE REVEIVE and set slaveaddr */ 164 writel(0, &i2c->iicstat); 165 writel(slaveadd, &i2c->iicadd); 166 /* program Master Transmit (and implicit STOP) */ 167 writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat); 168 } 169 170 /* 171 * MULTI BUS I2C support 172 */ 173 174 #ifdef CONFIG_I2C_MULTI_BUS 175 int i2c_set_bus_num(unsigned int bus) 176 { 177 struct s3c24x0_i2c *i2c; 178 179 if ((bus < 0) || (bus >= CONFIG_MAX_I2C_NUM)) { 180 debug("Bad bus: %d\n", bus); 181 return -1; 182 } 183 184 g_current_bus = bus; 185 i2c = get_base_i2c(); 186 i2c_ch_init(i2c, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 187 188 return 0; 189 } 190 191 unsigned int i2c_get_bus_num(void) 192 { 193 return g_current_bus; 194 } 195 #endif 196 197 void i2c_init(int speed, int slaveadd) 198 { 199 struct s3c24x0_i2c *i2c; 200 #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) 201 struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio(); 202 #endif 203 int i; 204 205 /* By default i2c channel 0 is the current bus */ 206 g_current_bus = 0; 207 i2c = get_base_i2c(); 208 209 /* wait for some time to give previous transfer a chance to finish */ 210 i = I2C_TIMEOUT * 1000; 211 while ((readl(&i2c->iicstat) & I2CSTAT_BSY) && (i > 0)) { 212 udelay(1000); 213 i--; 214 } 215 216 #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) 217 if ((readl(&i2c->iicstat) & I2CSTAT_BSY) || GetI2CSDA() == 0) { 218 #ifdef CONFIG_S3C2410 219 ulong old_gpecon = readl(&gpio->gpecon); 220 #endif 221 #ifdef CONFIG_S3C2400 222 ulong old_gpecon = readl(&gpio->pgcon); 223 #endif 224 /* bus still busy probably by (most) previously interrupted 225 transfer */ 226 227 #ifdef CONFIG_S3C2410 228 /* set I2CSDA and I2CSCL (GPE15, GPE14) to GPIO */ 229 writel((readl(&gpio->gpecon) & ~0xF0000000) | 0x10000000, 230 &gpio->gpecon); 231 #endif 232 #ifdef CONFIG_S3C2400 233 /* set I2CSDA and I2CSCL (PG5, PG6) to GPIO */ 234 writel((readl(&gpio->pgcon) & ~0x00003c00) | 0x00001000, 235 &gpio->pgcon); 236 #endif 237 238 /* toggle I2CSCL until bus idle */ 239 SetI2CSCL(0); 240 udelay(1000); 241 i = 10; 242 while ((i > 0) && (GetI2CSDA() != 1)) { 243 SetI2CSCL(1); 244 udelay(1000); 245 SetI2CSCL(0); 246 udelay(1000); 247 i--; 248 } 249 SetI2CSCL(1); 250 udelay(1000); 251 252 /* restore pin functions */ 253 #ifdef CONFIG_S3C2410 254 writel(old_gpecon, &gpio->gpecon); 255 #endif 256 #ifdef CONFIG_S3C2400 257 writel(old_gpecon, &gpio->pgcon); 258 #endif 259 } 260 #endif /* #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) */ 261 i2c_ch_init(i2c, speed, slaveadd); 262 } 263 264 /* 265 * cmd_type is 0 for write, 1 for read. 266 * 267 * addr_len can take any value from 0-255, it is only limited 268 * by the char, we could make it larger if needed. If it is 269 * 0 we skip the address write cycle. 270 */ 271 static int i2c_transfer(struct s3c24x0_i2c *i2c, 272 unsigned char cmd_type, 273 unsigned char chip, 274 unsigned char addr[], 275 unsigned char addr_len, 276 unsigned char data[], 277 unsigned short data_len) 278 { 279 int i, result; 280 281 if (data == 0 || data_len == 0) { 282 /*Don't support data transfer of no length or to address 0 */ 283 debug("i2c_transfer: bad call\n"); 284 return I2C_NOK; 285 } 286 287 /* Check I2C bus idle */ 288 i = I2C_TIMEOUT * 1000; 289 while ((readl(&i2c->iicstat) & I2CSTAT_BSY) && (i > 0)) { 290 udelay(1000); 291 i--; 292 } 293 294 if (readl(&i2c->iicstat) & I2CSTAT_BSY) 295 return I2C_NOK_TOUT; 296 297 writel(readl(&i2c->iiccon) | I2CCON_ACKGEN, &i2c->iiccon); 298 result = I2C_OK; 299 300 switch (cmd_type) { 301 case I2C_WRITE: 302 if (addr && addr_len) { 303 writel(chip, &i2c->iicds); 304 /* send START */ 305 writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP, 306 &i2c->iicstat); 307 i = 0; 308 while ((i < addr_len) && (result == I2C_OK)) { 309 result = WaitForXfer(i2c); 310 writel(addr[i], &i2c->iicds); 311 ReadWriteByte(i2c); 312 i++; 313 } 314 i = 0; 315 while ((i < data_len) && (result == I2C_OK)) { 316 result = WaitForXfer(i2c); 317 writel(data[i], &i2c->iicds); 318 ReadWriteByte(i2c); 319 i++; 320 } 321 } else { 322 writel(chip, &i2c->iicds); 323 /* send START */ 324 writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP, 325 &i2c->iicstat); 326 i = 0; 327 while ((i < data_len) && (result == I2C_OK)) { 328 result = WaitForXfer(i2c); 329 writel(data[i], &i2c->iicds); 330 ReadWriteByte(i2c); 331 i++; 332 } 333 } 334 335 if (result == I2C_OK) 336 result = WaitForXfer(i2c); 337 338 /* send STOP */ 339 writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat); 340 ReadWriteByte(i2c); 341 break; 342 343 case I2C_READ: 344 if (addr && addr_len) { 345 writel(chip, &i2c->iicds); 346 /* send START */ 347 writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP, 348 &i2c->iicstat); 349 result = WaitForXfer(i2c); 350 if (IsACK(i2c)) { 351 i = 0; 352 while ((i < addr_len) && (result == I2C_OK)) { 353 writel(addr[i], &i2c->iicds); 354 ReadWriteByte(i2c); 355 result = WaitForXfer(i2c); 356 i++; 357 } 358 359 writel(chip, &i2c->iicds); 360 /* resend START */ 361 writel(I2C_MODE_MR | I2C_TXRX_ENA | 362 I2C_START_STOP, &i2c->iicstat); 363 ReadWriteByte(i2c); 364 result = WaitForXfer(i2c); 365 i = 0; 366 while ((i < data_len) && (result == I2C_OK)) { 367 /* disable ACK for final READ */ 368 if (i == data_len - 1) 369 writel(readl(&i2c->iiccon) 370 & ~I2CCON_ACKGEN, 371 &i2c->iiccon); 372 ReadWriteByte(i2c); 373 result = WaitForXfer(i2c); 374 data[i] = readl(&i2c->iicds); 375 i++; 376 } 377 } else { 378 result = I2C_NACK; 379 } 380 381 } else { 382 writel(chip, &i2c->iicds); 383 /* send START */ 384 writel(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP, 385 &i2c->iicstat); 386 result = WaitForXfer(i2c); 387 388 if (IsACK(i2c)) { 389 i = 0; 390 while ((i < data_len) && (result == I2C_OK)) { 391 /* disable ACK for final READ */ 392 if (i == data_len - 1) 393 writel(readl(&i2c->iiccon) & 394 ~I2CCON_ACKGEN, 395 &i2c->iiccon); 396 ReadWriteByte(i2c); 397 result = WaitForXfer(i2c); 398 data[i] = readl(&i2c->iicds); 399 i++; 400 } 401 } else { 402 result = I2C_NACK; 403 } 404 } 405 406 /* send STOP */ 407 writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat); 408 ReadWriteByte(i2c); 409 break; 410 411 default: 412 debug("i2c_transfer: bad call\n"); 413 result = I2C_NOK; 414 break; 415 } 416 417 return result; 418 } 419 420 int i2c_probe(uchar chip) 421 { 422 struct s3c24x0_i2c *i2c; 423 uchar buf[1]; 424 425 i2c = get_base_i2c(); 426 buf[0] = 0; 427 428 /* 429 * What is needed is to send the chip address and verify that the 430 * address was <ACK>ed (i.e. there was a chip at that address which 431 * drove the data line low). 432 */ 433 return i2c_transfer(i2c, I2C_READ, chip << 1, 0, 0, buf, 1) != I2C_OK; 434 } 435 436 int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) 437 { 438 struct s3c24x0_i2c *i2c; 439 uchar xaddr[4]; 440 int ret; 441 442 if (alen > 4) { 443 debug("I2C read: addr len %d not supported\n", alen); 444 return 1; 445 } 446 447 if (alen > 0) { 448 xaddr[0] = (addr >> 24) & 0xFF; 449 xaddr[1] = (addr >> 16) & 0xFF; 450 xaddr[2] = (addr >> 8) & 0xFF; 451 xaddr[3] = addr & 0xFF; 452 } 453 454 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 455 /* 456 * EEPROM chips that implement "address overflow" are ones 457 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of 458 * address and the extra bits end up in the "chip address" 459 * bit slots. This makes a 24WC08 (1Kbyte) chip look like 460 * four 256 byte chips. 461 * 462 * Note that we consider the length of the address field to 463 * still be one byte because the extra address bits are 464 * hidden in the chip address. 465 */ 466 if (alen > 0) 467 chip |= ((addr >> (alen * 8)) & 468 CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); 469 #endif 470 i2c = get_base_i2c(); 471 ret = i2c_transfer(i2c, I2C_READ, chip << 1, &xaddr[4 - alen], alen, 472 buffer, len); 473 if (ret != 0) { 474 debug("I2c read: failed %d\n", ret); 475 return 1; 476 } 477 return 0; 478 } 479 480 int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) 481 { 482 struct s3c24x0_i2c *i2c; 483 uchar xaddr[4]; 484 485 if (alen > 4) { 486 debug("I2C write: addr len %d not supported\n", alen); 487 return 1; 488 } 489 490 if (alen > 0) { 491 xaddr[0] = (addr >> 24) & 0xFF; 492 xaddr[1] = (addr >> 16) & 0xFF; 493 xaddr[2] = (addr >> 8) & 0xFF; 494 xaddr[3] = addr & 0xFF; 495 } 496 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 497 /* 498 * EEPROM chips that implement "address overflow" are ones 499 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of 500 * address and the extra bits end up in the "chip address" 501 * bit slots. This makes a 24WC08 (1Kbyte) chip look like 502 * four 256 byte chips. 503 * 504 * Note that we consider the length of the address field to 505 * still be one byte because the extra address bits are 506 * hidden in the chip address. 507 */ 508 if (alen > 0) 509 chip |= ((addr >> (alen * 8)) & 510 CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); 511 #endif 512 i2c = get_base_i2c(); 513 return (i2c_transfer 514 (i2c, I2C_WRITE, chip << 1, &xaddr[4 - alen], alen, buffer, 515 len) != 0); 516 } 517 518 #ifdef CONFIG_OF_CONTROL 519 void board_i2c_init(const void *blob) 520 { 521 int node_list[CONFIG_MAX_I2C_NUM]; 522 int count, i; 523 524 count = fdtdec_find_aliases_for_id(blob, "i2c", 525 COMPAT_SAMSUNG_S3C2440_I2C, node_list, 526 CONFIG_MAX_I2C_NUM); 527 528 for (i = 0; i < count; i++) { 529 struct s3c24x0_i2c_bus *bus; 530 int node = node_list[i]; 531 532 if (node <= 0) 533 continue; 534 bus = &i2c_bus[i]; 535 bus->regs = (struct s3c24x0_i2c *) 536 fdtdec_get_addr(blob, node, "reg"); 537 bus->id = pinmux_decode_periph_id(blob, node); 538 bus->node = node; 539 bus->bus_num = i2c_busses++; 540 exynos_pinmux_config(bus->id, 0); 541 } 542 } 543 544 static struct s3c24x0_i2c_bus *get_bus(unsigned int bus_idx) 545 { 546 if (bus_idx < i2c_busses) 547 return &i2c_bus[bus_idx]; 548 549 debug("Undefined bus: %d\n", bus_idx); 550 return NULL; 551 } 552 553 int i2c_get_bus_num_fdt(int node) 554 { 555 int i; 556 557 for (i = 0; i < i2c_busses; i++) { 558 if (node == i2c_bus[i].node) 559 return i; 560 } 561 562 debug("%s: Can't find any matched I2C bus\n", __func__); 563 return -1; 564 } 565 566 int i2c_reset_port_fdt(const void *blob, int node) 567 { 568 struct s3c24x0_i2c_bus *i2c; 569 int bus; 570 571 bus = i2c_get_bus_num_fdt(node); 572 if (bus < 0) { 573 debug("could not get bus for node %d\n", node); 574 return -1; 575 } 576 577 i2c = get_bus(bus); 578 if (!i2c) { 579 debug("get_bus() failed for node node %d\n", node); 580 return -1; 581 } 582 583 i2c_ch_init(i2c->regs, CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 584 585 return 0; 586 } 587 #endif 588 589 #endif /* CONFIG_HARD_I2C */ 590