1 /* 2 * (C) Copyright 2002 3 * David Mueller, ELSOFT AG, d.mueller@elsoft.ch 4 * 5 * SPDX-License-Identifier: GPL-2.0+ 6 */ 7 8 /* This code should work for both the S3C2400 and the S3C2410 9 * as they seem to have the same I2C controller inside. 10 * The different address mapping is handled by the s3c24xx.h files below. 11 */ 12 13 #include <common.h> 14 #include <fdtdec.h> 15 #if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) 16 #include <asm/arch/clk.h> 17 #include <asm/arch/cpu.h> 18 #include <asm/arch/pinmux.h> 19 #else 20 #include <asm/arch/s3c24x0_cpu.h> 21 #endif 22 #include <asm/io.h> 23 #include <i2c.h> 24 #include "s3c24x0_i2c.h" 25 26 #ifdef CONFIG_HARD_I2C 27 28 #define I2C_WRITE 0 29 #define I2C_READ 1 30 31 #define I2C_OK 0 32 #define I2C_NOK 1 33 #define I2C_NACK 2 34 #define I2C_NOK_LA 3 /* Lost arbitration */ 35 #define I2C_NOK_TOUT 4 /* time out */ 36 37 /* HSI2C specific register description */ 38 39 /* I2C_CTL Register bits */ 40 #define HSI2C_FUNC_MODE_I2C (1u << 0) 41 #define HSI2C_MASTER (1u << 3) 42 #define HSI2C_RXCHON (1u << 6) /* Write/Send */ 43 #define HSI2C_TXCHON (1u << 7) /* Read/Receive */ 44 #define HSI2C_SW_RST (1u << 31) 45 46 /* I2C_FIFO_CTL Register bits */ 47 #define HSI2C_RXFIFO_EN (1u << 0) 48 #define HSI2C_TXFIFO_EN (1u << 1) 49 #define HSI2C_TXFIFO_TRIGGER_LEVEL (0x20 << 16) 50 #define HSI2C_RXFIFO_TRIGGER_LEVEL (0x20 << 4) 51 52 /* I2C_TRAILING_CTL Register bits */ 53 #define HSI2C_TRAILING_COUNT (0xff) 54 55 /* I2C_INT_EN Register bits */ 56 #define HSI2C_TX_UNDERRUN_EN (1u << 2) 57 #define HSI2C_TX_OVERRUN_EN (1u << 3) 58 #define HSI2C_RX_UNDERRUN_EN (1u << 4) 59 #define HSI2C_RX_OVERRUN_EN (1u << 5) 60 #define HSI2C_INT_TRAILING_EN (1u << 6) 61 #define HSI2C_INT_I2C_EN (1u << 9) 62 63 #define HSI2C_INT_ERROR_MASK (HSI2C_TX_UNDERRUN_EN |\ 64 HSI2C_TX_OVERRUN_EN |\ 65 HSI2C_RX_UNDERRUN_EN |\ 66 HSI2C_RX_OVERRUN_EN |\ 67 HSI2C_INT_TRAILING_EN) 68 69 /* I2C_CONF Register bits */ 70 #define HSI2C_AUTO_MODE (1u << 31) 71 #define HSI2C_10BIT_ADDR_MODE (1u << 30) 72 #define HSI2C_HS_MODE (1u << 29) 73 74 /* I2C_AUTO_CONF Register bits */ 75 #define HSI2C_READ_WRITE (1u << 16) 76 #define HSI2C_STOP_AFTER_TRANS (1u << 17) 77 #define HSI2C_MASTER_RUN (1u << 31) 78 79 /* I2C_TIMEOUT Register bits */ 80 #define HSI2C_TIMEOUT_EN (1u << 31) 81 82 /* I2C_TRANS_STATUS register bits */ 83 #define HSI2C_MASTER_BUSY (1u << 17) 84 #define HSI2C_SLAVE_BUSY (1u << 16) 85 #define HSI2C_TIMEOUT_AUTO (1u << 4) 86 #define HSI2C_NO_DEV (1u << 3) 87 #define HSI2C_NO_DEV_ACK (1u << 2) 88 #define HSI2C_TRANS_ABORT (1u << 1) 89 #define HSI2C_TRANS_SUCCESS (1u << 0) 90 #define HSI2C_TRANS_ERROR_MASK (HSI2C_TIMEOUT_AUTO |\ 91 HSI2C_NO_DEV | HSI2C_NO_DEV_ACK |\ 92 HSI2C_TRANS_ABORT) 93 #define HSI2C_TRANS_FINISHED_MASK (HSI2C_TRANS_ERROR_MASK | HSI2C_TRANS_SUCCESS) 94 95 96 /* I2C_FIFO_STAT Register bits */ 97 #define HSI2C_RX_FIFO_EMPTY (1u << 24) 98 #define HSI2C_RX_FIFO_FULL (1u << 23) 99 #define HSI2C_TX_FIFO_EMPTY (1u << 8) 100 #define HSI2C_TX_FIFO_FULL (1u << 7) 101 #define HSI2C_RX_FIFO_LEVEL(x) (((x) >> 16) & 0x7f) 102 #define HSI2C_TX_FIFO_LEVEL(x) ((x) & 0x7f) 103 104 #define HSI2C_SLV_ADDR_MAS(x) ((x & 0x3ff) << 10) 105 106 /* S3C I2C Controller bits */ 107 #define I2CSTAT_BSY 0x20 /* Busy bit */ 108 #define I2CSTAT_NACK 0x01 /* Nack bit */ 109 #define I2CCON_ACKGEN 0x80 /* Acknowledge generation */ 110 #define I2CCON_IRPND 0x10 /* Interrupt pending bit */ 111 #define I2C_MODE_MT 0xC0 /* Master Transmit Mode */ 112 #define I2C_MODE_MR 0x80 /* Master Receive Mode */ 113 #define I2C_START_STOP 0x20 /* START / STOP */ 114 #define I2C_TXRX_ENA 0x10 /* I2C Tx/Rx enable */ 115 116 #define I2C_TIMEOUT_MS 1000 /* 1 second */ 117 118 #define HSI2C_TIMEOUT_US 100000 /* 100 ms, finer granularity */ 119 120 121 /* To support VCMA9 boards and other who dont define max_i2c_num */ 122 #ifndef CONFIG_MAX_I2C_NUM 123 #define CONFIG_MAX_I2C_NUM 1 124 #endif 125 126 /* 127 * For SPL boot some boards need i2c before SDRAM is initialised so force 128 * variables to live in SRAM 129 */ 130 static unsigned int g_current_bus __attribute__((section(".data"))); 131 static struct s3c24x0_i2c_bus i2c_bus[CONFIG_MAX_I2C_NUM] 132 __attribute__((section(".data"))); 133 134 /** 135 * Get a pointer to the given bus index 136 * 137 * @bus_idx: Bus index to look up 138 * @return pointer to bus, or NULL if invalid or not available 139 */ 140 static struct s3c24x0_i2c_bus *get_bus(unsigned int bus_idx) 141 { 142 if (bus_idx < ARRAY_SIZE(i2c_bus)) { 143 struct s3c24x0_i2c_bus *bus; 144 145 bus = &i2c_bus[bus_idx]; 146 if (bus->active) 147 return bus; 148 } 149 150 debug("Undefined bus: %d\n", bus_idx); 151 return NULL; 152 } 153 154 #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) 155 static int GetI2CSDA(void) 156 { 157 struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio(); 158 159 #ifdef CONFIG_S3C2410 160 return (readl(&gpio->gpedat) & 0x8000) >> 15; 161 #endif 162 #ifdef CONFIG_S3C2400 163 return (readl(&gpio->pgdat) & 0x0020) >> 5; 164 #endif 165 } 166 167 static void SetI2CSCL(int x) 168 { 169 struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio(); 170 171 #ifdef CONFIG_S3C2410 172 writel((readl(&gpio->gpedat) & ~0x4000) | 173 (x & 1) << 14, &gpio->gpedat); 174 #endif 175 #ifdef CONFIG_S3C2400 176 writel((readl(&gpio->pgdat) & ~0x0040) | (x & 1) << 6, &gpio->pgdat); 177 #endif 178 } 179 #endif 180 181 /* 182 * Wait til the byte transfer is completed. 183 * 184 * @param i2c- pointer to the appropriate i2c register bank. 185 * @return I2C_OK, if transmission was ACKED 186 * I2C_NACK, if transmission was NACKED 187 * I2C_NOK_TIMEOUT, if transaction did not complete in I2C_TIMEOUT_MS 188 */ 189 190 static int WaitForXfer(struct s3c24x0_i2c *i2c) 191 { 192 ulong start_time = get_timer(0); 193 194 do { 195 if (readl(&i2c->iiccon) & I2CCON_IRPND) 196 return (readl(&i2c->iicstat) & I2CSTAT_NACK) ? 197 I2C_NACK : I2C_OK; 198 } while (get_timer(start_time) < I2C_TIMEOUT_MS); 199 200 return I2C_NOK_TOUT; 201 } 202 203 /* 204 * Wait for transfer completion. 205 * 206 * This function reads the interrupt status register waiting for the INT_I2C 207 * bit to be set, which indicates copletion of a transaction. 208 * 209 * @param i2c: pointer to the appropriate register bank 210 * 211 * @return: I2C_OK in case of successful completion, I2C_NOK_TIMEOUT in case 212 * the status bits do not get set in time, or an approrpiate error 213 * value in case of transfer errors. 214 */ 215 static int hsi2c_wait_for_trx(struct exynos5_hsi2c *i2c) 216 { 217 int i = HSI2C_TIMEOUT_US; 218 219 while (i-- > 0) { 220 u32 int_status = readl(&i2c->usi_int_stat); 221 222 if (int_status & HSI2C_INT_I2C_EN) { 223 u32 trans_status = readl(&i2c->usi_trans_status); 224 225 /* Deassert pending interrupt. */ 226 writel(int_status, &i2c->usi_int_stat); 227 228 if (trans_status & HSI2C_NO_DEV_ACK) { 229 debug("%s: no ACK from device\n", __func__); 230 return I2C_NACK; 231 } 232 if (trans_status & HSI2C_NO_DEV) { 233 debug("%s: no device\n", __func__); 234 return I2C_NOK; 235 } 236 if (trans_status & HSI2C_TRANS_ABORT) { 237 debug("%s: arbitration lost\n", __func__); 238 return I2C_NOK_LA; 239 } 240 if (trans_status & HSI2C_TIMEOUT_AUTO) { 241 debug("%s: device timed out\n", __func__); 242 return I2C_NOK_TOUT; 243 } 244 return I2C_OK; 245 } 246 udelay(1); 247 } 248 debug("%s: transaction timeout!\n", __func__); 249 return I2C_NOK_TOUT; 250 } 251 252 static void ReadWriteByte(struct s3c24x0_i2c *i2c) 253 { 254 writel(readl(&i2c->iiccon) & ~I2CCON_IRPND, &i2c->iiccon); 255 } 256 257 static struct s3c24x0_i2c *get_base_i2c(void) 258 { 259 #ifdef CONFIG_EXYNOS4 260 struct s3c24x0_i2c *i2c = (struct s3c24x0_i2c *)(samsung_get_base_i2c() 261 + (EXYNOS4_I2C_SPACING 262 * g_current_bus)); 263 return i2c; 264 #elif defined CONFIG_EXYNOS5 265 struct s3c24x0_i2c *i2c = (struct s3c24x0_i2c *)(samsung_get_base_i2c() 266 + (EXYNOS5_I2C_SPACING 267 * g_current_bus)); 268 return i2c; 269 #else 270 return s3c24x0_get_base_i2c(); 271 #endif 272 } 273 274 static void i2c_ch_init(struct s3c24x0_i2c *i2c, int speed, int slaveadd) 275 { 276 ulong freq, pres = 16, div; 277 #if (defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) 278 freq = get_i2c_clk(); 279 #else 280 freq = get_PCLK(); 281 #endif 282 /* calculate prescaler and divisor values */ 283 if ((freq / pres / (16 + 1)) > speed) 284 /* set prescaler to 512 */ 285 pres = 512; 286 287 div = 0; 288 while ((freq / pres / (div + 1)) > speed) 289 div++; 290 291 /* set prescaler, divisor according to freq, also set ACKGEN, IRQ */ 292 writel((div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0), &i2c->iiccon); 293 294 /* init to SLAVE REVEIVE and set slaveaddr */ 295 writel(0, &i2c->iicstat); 296 writel(slaveadd, &i2c->iicadd); 297 /* program Master Transmit (and implicit STOP) */ 298 writel(I2C_MODE_MT | I2C_TXRX_ENA, &i2c->iicstat); 299 } 300 301 #ifdef CONFIG_I2C_MULTI_BUS 302 static int hsi2c_get_clk_details(struct s3c24x0_i2c_bus *i2c_bus) 303 { 304 struct exynos5_hsi2c *hsregs = i2c_bus->hsregs; 305 ulong clkin; 306 unsigned int op_clk = i2c_bus->clock_frequency; 307 unsigned int i = 0, utemp0 = 0, utemp1 = 0; 308 unsigned int t_ftl_cycle; 309 310 #if defined CONFIG_EXYNOS5 311 clkin = get_i2c_clk(); 312 #endif 313 /* FPCLK / FI2C = 314 * (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) + 8 + 2 * FLT_CYCLE 315 * uTemp0 = (CLK_DIV + 1) * (TSCLK_L + TSCLK_H + 2) 316 * uTemp1 = (TSCLK_L + TSCLK_H + 2) 317 * uTemp2 = TSCLK_L + TSCLK_H 318 */ 319 t_ftl_cycle = (readl(&hsregs->usi_conf) >> 16) & 0x7; 320 utemp0 = (clkin / op_clk) - 8 - 2 * t_ftl_cycle; 321 322 /* CLK_DIV max is 256 */ 323 for (i = 0; i < 256; i++) { 324 utemp1 = utemp0 / (i + 1); 325 if ((utemp1 < 512) && (utemp1 > 4)) { 326 i2c_bus->clk_cycle = utemp1 - 2; 327 i2c_bus->clk_div = i; 328 return 0; 329 } 330 } 331 return -1; 332 } 333 #endif 334 335 static void hsi2c_ch_init(struct s3c24x0_i2c_bus *i2c_bus) 336 { 337 struct exynos5_hsi2c *hsregs = i2c_bus->hsregs; 338 unsigned int t_sr_release; 339 unsigned int n_clkdiv; 340 unsigned int t_start_su, t_start_hd; 341 unsigned int t_stop_su; 342 unsigned int t_data_su, t_data_hd; 343 unsigned int t_scl_l, t_scl_h; 344 u32 i2c_timing_s1; 345 u32 i2c_timing_s2; 346 u32 i2c_timing_s3; 347 u32 i2c_timing_sla; 348 349 n_clkdiv = i2c_bus->clk_div; 350 t_scl_l = i2c_bus->clk_cycle / 2; 351 t_scl_h = i2c_bus->clk_cycle / 2; 352 t_start_su = t_scl_l; 353 t_start_hd = t_scl_l; 354 t_stop_su = t_scl_l; 355 t_data_su = t_scl_l / 2; 356 t_data_hd = t_scl_l / 2; 357 t_sr_release = i2c_bus->clk_cycle; 358 359 i2c_timing_s1 = t_start_su << 24 | t_start_hd << 16 | t_stop_su << 8; 360 i2c_timing_s2 = t_data_su << 24 | t_scl_l << 8 | t_scl_h << 0; 361 i2c_timing_s3 = n_clkdiv << 16 | t_sr_release << 0; 362 i2c_timing_sla = t_data_hd << 0; 363 364 writel(HSI2C_TRAILING_COUNT, &hsregs->usi_trailing_ctl); 365 366 /* Clear to enable Timeout */ 367 clrsetbits_le32(&hsregs->usi_timeout, HSI2C_TIMEOUT_EN, 0); 368 369 /* set AUTO mode */ 370 writel(readl(&hsregs->usi_conf) | HSI2C_AUTO_MODE, &hsregs->usi_conf); 371 372 /* Enable completion conditions' reporting. */ 373 writel(HSI2C_INT_I2C_EN, &hsregs->usi_int_en); 374 375 /* Enable FIFOs */ 376 writel(HSI2C_RXFIFO_EN | HSI2C_TXFIFO_EN, &hsregs->usi_fifo_ctl); 377 378 /* Currently operating in Fast speed mode. */ 379 writel(i2c_timing_s1, &hsregs->usi_timing_fs1); 380 writel(i2c_timing_s2, &hsregs->usi_timing_fs2); 381 writel(i2c_timing_s3, &hsregs->usi_timing_fs3); 382 writel(i2c_timing_sla, &hsregs->usi_timing_sla); 383 } 384 385 /* SW reset for the high speed bus */ 386 static void exynos5_i2c_reset(struct s3c24x0_i2c_bus *i2c_bus) 387 { 388 struct exynos5_hsi2c *i2c = i2c_bus->hsregs; 389 u32 i2c_ctl; 390 391 /* Set and clear the bit for reset */ 392 i2c_ctl = readl(&i2c->usi_ctl); 393 i2c_ctl |= HSI2C_SW_RST; 394 writel(i2c_ctl, &i2c->usi_ctl); 395 396 i2c_ctl = readl(&i2c->usi_ctl); 397 i2c_ctl &= ~HSI2C_SW_RST; 398 writel(i2c_ctl, &i2c->usi_ctl); 399 400 /* Initialize the configure registers */ 401 hsi2c_ch_init(i2c_bus); 402 } 403 404 /* 405 * MULTI BUS I2C support 406 */ 407 408 #ifdef CONFIG_I2C_MULTI_BUS 409 int i2c_set_bus_num(unsigned int bus) 410 { 411 struct s3c24x0_i2c_bus *i2c_bus; 412 413 i2c_bus = get_bus(bus); 414 if (!i2c_bus) 415 return -1; 416 g_current_bus = bus; 417 418 if (i2c_bus->is_highspeed) { 419 if (hsi2c_get_clk_details(i2c_bus)) 420 return -1; 421 hsi2c_ch_init(i2c_bus); 422 } else { 423 i2c_ch_init(i2c_bus->regs, i2c_bus->clock_frequency, 424 CONFIG_SYS_I2C_SLAVE); 425 } 426 427 return 0; 428 } 429 430 unsigned int i2c_get_bus_num(void) 431 { 432 return g_current_bus; 433 } 434 #endif 435 436 void i2c_init(int speed, int slaveadd) 437 { 438 struct s3c24x0_i2c *i2c; 439 #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) 440 struct s3c24x0_gpio *gpio = s3c24x0_get_base_gpio(); 441 #endif 442 ulong start_time = get_timer(0); 443 444 /* By default i2c channel 0 is the current bus */ 445 g_current_bus = 0; 446 i2c = get_base_i2c(); 447 448 /* 449 * In case the previous transfer is still going, wait to give it a 450 * chance to finish. 451 */ 452 while (readl(&i2c->iicstat) & I2CSTAT_BSY) { 453 if (get_timer(start_time) > I2C_TIMEOUT_MS) { 454 printf("%s: I2C bus busy for %p\n", __func__, 455 &i2c->iicstat); 456 return; 457 } 458 } 459 460 #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) 461 int i; 462 463 if ((readl(&i2c->iicstat) & I2CSTAT_BSY) || GetI2CSDA() == 0) { 464 #ifdef CONFIG_S3C2410 465 ulong old_gpecon = readl(&gpio->gpecon); 466 #endif 467 #ifdef CONFIG_S3C2400 468 ulong old_gpecon = readl(&gpio->pgcon); 469 #endif 470 /* bus still busy probably by (most) previously interrupted 471 transfer */ 472 473 #ifdef CONFIG_S3C2410 474 /* set I2CSDA and I2CSCL (GPE15, GPE14) to GPIO */ 475 writel((readl(&gpio->gpecon) & ~0xF0000000) | 0x10000000, 476 &gpio->gpecon); 477 #endif 478 #ifdef CONFIG_S3C2400 479 /* set I2CSDA and I2CSCL (PG5, PG6) to GPIO */ 480 writel((readl(&gpio->pgcon) & ~0x00003c00) | 0x00001000, 481 &gpio->pgcon); 482 #endif 483 484 /* toggle I2CSCL until bus idle */ 485 SetI2CSCL(0); 486 udelay(1000); 487 i = 10; 488 while ((i > 0) && (GetI2CSDA() != 1)) { 489 SetI2CSCL(1); 490 udelay(1000); 491 SetI2CSCL(0); 492 udelay(1000); 493 i--; 494 } 495 SetI2CSCL(1); 496 udelay(1000); 497 498 /* restore pin functions */ 499 #ifdef CONFIG_S3C2410 500 writel(old_gpecon, &gpio->gpecon); 501 #endif 502 #ifdef CONFIG_S3C2400 503 writel(old_gpecon, &gpio->pgcon); 504 #endif 505 } 506 #endif /* #if !(defined CONFIG_EXYNOS4 || defined CONFIG_EXYNOS5) */ 507 i2c_ch_init(i2c, speed, slaveadd); 508 } 509 510 /* 511 * Poll the appropriate bit of the fifo status register until the interface is 512 * ready to process the next byte or timeout expires. 513 * 514 * In addition to the FIFO status register this function also polls the 515 * interrupt status register to be able to detect unexpected transaction 516 * completion. 517 * 518 * When FIFO is ready to process the next byte, this function returns I2C_OK. 519 * If in course of polling the INT_I2C assertion is detected, the function 520 * returns I2C_NOK. If timeout happens before any of the above conditions is 521 * met - the function returns I2C_NOK_TOUT; 522 523 * @param i2c: pointer to the appropriate i2c register bank. 524 * @param rx_transfer: set to True if the receive transaction is in progress. 525 * @return: as described above. 526 */ 527 static unsigned hsi2c_poll_fifo(struct exynos5_hsi2c *i2c, bool rx_transfer) 528 { 529 u32 fifo_bit = rx_transfer ? HSI2C_RX_FIFO_EMPTY : HSI2C_TX_FIFO_FULL; 530 int i = HSI2C_TIMEOUT_US; 531 532 while (readl(&i2c->usi_fifo_stat) & fifo_bit) { 533 if (readl(&i2c->usi_int_stat) & HSI2C_INT_I2C_EN) { 534 /* 535 * There is a chance that assertion of 536 * HSI2C_INT_I2C_EN and deassertion of 537 * HSI2C_RX_FIFO_EMPTY happen simultaneously. Let's 538 * give FIFO status priority and check it one more 539 * time before reporting interrupt. The interrupt will 540 * be reported next time this function is called. 541 */ 542 if (rx_transfer && 543 !(readl(&i2c->usi_fifo_stat) & fifo_bit)) 544 break; 545 return I2C_NOK; 546 } 547 if (!i--) { 548 debug("%s: FIFO polling timeout!\n", __func__); 549 return I2C_NOK_TOUT; 550 } 551 udelay(1); 552 } 553 return I2C_OK; 554 } 555 556 /* 557 * Preapre hsi2c transaction, either read or write. 558 * 559 * Set up transfer as described in section 27.5.1.2 'I2C Channel Auto Mode' of 560 * the 5420 UM. 561 * 562 * @param i2c: pointer to the appropriate i2c register bank. 563 * @param chip: slave address on the i2c bus (with read/write bit exlcuded) 564 * @param len: number of bytes expected to be sent or received 565 * @param rx_transfer: set to true for receive transactions 566 * @param: issue_stop: set to true if i2c stop condition should be generated 567 * after this transaction. 568 * @return: I2C_NOK_TOUT in case the bus remained busy for HSI2C_TIMEOUT_US, 569 * I2C_OK otherwise. 570 */ 571 static int hsi2c_prepare_transaction(struct exynos5_hsi2c *i2c, 572 u8 chip, 573 u16 len, 574 bool rx_transfer, 575 bool issue_stop) 576 { 577 u32 conf; 578 579 conf = len | HSI2C_MASTER_RUN; 580 581 if (issue_stop) 582 conf |= HSI2C_STOP_AFTER_TRANS; 583 584 /* Clear to enable Timeout */ 585 writel(readl(&i2c->usi_timeout) & ~HSI2C_TIMEOUT_EN, &i2c->usi_timeout); 586 587 /* Set slave address */ 588 writel(HSI2C_SLV_ADDR_MAS(chip), &i2c->i2c_addr); 589 590 if (rx_transfer) { 591 /* i2c master, read transaction */ 592 writel((HSI2C_RXCHON | HSI2C_FUNC_MODE_I2C | HSI2C_MASTER), 593 &i2c->usi_ctl); 594 595 /* read up to len bytes, stop after transaction is finished */ 596 writel(conf | HSI2C_READ_WRITE, &i2c->usi_auto_conf); 597 } else { 598 /* i2c master, write transaction */ 599 writel((HSI2C_TXCHON | HSI2C_FUNC_MODE_I2C | HSI2C_MASTER), 600 &i2c->usi_ctl); 601 602 /* write up to len bytes, stop after transaction is finished */ 603 writel(conf, &i2c->usi_auto_conf); 604 } 605 606 /* Reset all pending interrupt status bits we care about, if any */ 607 writel(HSI2C_INT_I2C_EN, &i2c->usi_int_stat); 608 609 return I2C_OK; 610 } 611 612 /* 613 * Wait while i2c bus is settling down (mostly stop gets completed). 614 */ 615 static int hsi2c_wait_while_busy(struct exynos5_hsi2c *i2c) 616 { 617 int i = HSI2C_TIMEOUT_US; 618 619 while (readl(&i2c->usi_trans_status) & HSI2C_MASTER_BUSY) { 620 if (!i--) { 621 debug("%s: bus busy\n", __func__); 622 return I2C_NOK_TOUT; 623 } 624 udelay(1); 625 } 626 return I2C_OK; 627 } 628 629 static int hsi2c_write(struct exynos5_hsi2c *i2c, 630 unsigned char chip, 631 unsigned char addr[], 632 unsigned char alen, 633 unsigned char data[], 634 unsigned short len, 635 bool issue_stop) 636 { 637 int i, rv = 0; 638 639 if (!(len + alen)) { 640 /* Writes of zero length not supported in auto mode. */ 641 debug("%s: zero length writes not supported\n", __func__); 642 return I2C_NOK; 643 } 644 645 rv = hsi2c_prepare_transaction 646 (i2c, chip, len + alen, false, issue_stop); 647 if (rv != I2C_OK) 648 return rv; 649 650 /* Move address, if any, and the data, if any, into the FIFO. */ 651 for (i = 0; i < alen; i++) { 652 rv = hsi2c_poll_fifo(i2c, false); 653 if (rv != I2C_OK) { 654 debug("%s: address write failed\n", __func__); 655 goto write_error; 656 } 657 writel(addr[i], &i2c->usi_txdata); 658 } 659 660 for (i = 0; i < len; i++) { 661 rv = hsi2c_poll_fifo(i2c, false); 662 if (rv != I2C_OK) { 663 debug("%s: data write failed\n", __func__); 664 goto write_error; 665 } 666 writel(data[i], &i2c->usi_txdata); 667 } 668 669 rv = hsi2c_wait_for_trx(i2c); 670 671 write_error: 672 if (issue_stop) { 673 int tmp_ret = hsi2c_wait_while_busy(i2c); 674 if (rv == I2C_OK) 675 rv = tmp_ret; 676 } 677 678 writel(HSI2C_FUNC_MODE_I2C, &i2c->usi_ctl); /* done */ 679 return rv; 680 } 681 682 static int hsi2c_read(struct exynos5_hsi2c *i2c, 683 unsigned char chip, 684 unsigned char addr[], 685 unsigned char alen, 686 unsigned char data[], 687 unsigned short len) 688 { 689 int i, rv, tmp_ret; 690 bool drop_data = false; 691 692 if (!len) { 693 /* Reads of zero length not supported in auto mode. */ 694 debug("%s: zero length read adjusted\n", __func__); 695 drop_data = true; 696 len = 1; 697 } 698 699 if (alen) { 700 /* Internal register adress needs to be written first. */ 701 rv = hsi2c_write(i2c, chip, addr, alen, NULL, 0, false); 702 if (rv != I2C_OK) 703 return rv; 704 } 705 706 rv = hsi2c_prepare_transaction(i2c, chip, len, true, true); 707 708 if (rv != I2C_OK) 709 return rv; 710 711 for (i = 0; i < len; i++) { 712 rv = hsi2c_poll_fifo(i2c, true); 713 if (rv != I2C_OK) 714 goto read_err; 715 if (drop_data) 716 continue; 717 data[i] = readl(&i2c->usi_rxdata); 718 } 719 720 rv = hsi2c_wait_for_trx(i2c); 721 722 read_err: 723 tmp_ret = hsi2c_wait_while_busy(i2c); 724 if (rv == I2C_OK) 725 rv = tmp_ret; 726 727 writel(HSI2C_FUNC_MODE_I2C, &i2c->usi_ctl); /* done */ 728 return rv; 729 } 730 731 /* 732 * cmd_type is 0 for write, 1 for read. 733 * 734 * addr_len can take any value from 0-255, it is only limited 735 * by the char, we could make it larger if needed. If it is 736 * 0 we skip the address write cycle. 737 */ 738 static int i2c_transfer(struct s3c24x0_i2c *i2c, 739 unsigned char cmd_type, 740 unsigned char chip, 741 unsigned char addr[], 742 unsigned char addr_len, 743 unsigned char data[], 744 unsigned short data_len) 745 { 746 int i = 0, result; 747 ulong start_time = get_timer(0); 748 749 if (data == 0 || data_len == 0) { 750 /*Don't support data transfer of no length or to address 0 */ 751 debug("i2c_transfer: bad call\n"); 752 return I2C_NOK; 753 } 754 755 while (readl(&i2c->iicstat) & I2CSTAT_BSY) { 756 if (get_timer(start_time) > I2C_TIMEOUT_MS) 757 return I2C_NOK_TOUT; 758 } 759 760 writel(readl(&i2c->iiccon) | I2CCON_ACKGEN, &i2c->iiccon); 761 762 /* Get the slave chip address going */ 763 writel(chip, &i2c->iicds); 764 if ((cmd_type == I2C_WRITE) || (addr && addr_len)) 765 writel(I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP, 766 &i2c->iicstat); 767 else 768 writel(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP, 769 &i2c->iicstat); 770 771 /* Wait for chip address to transmit. */ 772 result = WaitForXfer(i2c); 773 if (result != I2C_OK) 774 goto bailout; 775 776 /* If register address needs to be transmitted - do it now. */ 777 if (addr && addr_len) { 778 while ((i < addr_len) && (result == I2C_OK)) { 779 writel(addr[i++], &i2c->iicds); 780 ReadWriteByte(i2c); 781 result = WaitForXfer(i2c); 782 } 783 i = 0; 784 if (result != I2C_OK) 785 goto bailout; 786 } 787 788 switch (cmd_type) { 789 case I2C_WRITE: 790 while ((i < data_len) && (result == I2C_OK)) { 791 writel(data[i++], &i2c->iicds); 792 ReadWriteByte(i2c); 793 result = WaitForXfer(i2c); 794 } 795 break; 796 797 case I2C_READ: 798 if (addr && addr_len) { 799 /* 800 * Register address has been sent, now send slave chip 801 * address again to start the actual read transaction. 802 */ 803 writel(chip, &i2c->iicds); 804 805 /* Generate a re-START. */ 806 writel(I2C_MODE_MR | I2C_TXRX_ENA | I2C_START_STOP, 807 &i2c->iicstat); 808 ReadWriteByte(i2c); 809 result = WaitForXfer(i2c); 810 811 if (result != I2C_OK) 812 goto bailout; 813 } 814 815 while ((i < data_len) && (result == I2C_OK)) { 816 /* disable ACK for final READ */ 817 if (i == data_len - 1) 818 writel(readl(&i2c->iiccon) 819 & ~I2CCON_ACKGEN, 820 &i2c->iiccon); 821 ReadWriteByte(i2c); 822 result = WaitForXfer(i2c); 823 data[i++] = readl(&i2c->iicds); 824 } 825 if (result == I2C_NACK) 826 result = I2C_OK; /* Normal terminated read. */ 827 break; 828 829 default: 830 debug("i2c_transfer: bad call\n"); 831 result = I2C_NOK; 832 break; 833 } 834 835 bailout: 836 /* Send STOP. */ 837 writel(I2C_MODE_MR | I2C_TXRX_ENA, &i2c->iicstat); 838 ReadWriteByte(i2c); 839 840 return result; 841 } 842 843 int i2c_probe(uchar chip) 844 { 845 struct s3c24x0_i2c_bus *i2c_bus; 846 uchar buf[1]; 847 int ret; 848 849 i2c_bus = get_bus(g_current_bus); 850 if (!i2c_bus) 851 return -1; 852 buf[0] = 0; 853 854 /* 855 * What is needed is to send the chip address and verify that the 856 * address was <ACK>ed (i.e. there was a chip at that address which 857 * drove the data line low). 858 */ 859 if (i2c_bus->is_highspeed) { 860 ret = hsi2c_read(i2c_bus->hsregs, 861 chip, 0, 0, buf, 1); 862 } else { 863 ret = i2c_transfer(i2c_bus->regs, 864 I2C_READ, chip << 1, 0, 0, buf, 1); 865 } 866 867 868 return ret != I2C_OK; 869 } 870 871 int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) 872 { 873 struct s3c24x0_i2c_bus *i2c_bus; 874 uchar xaddr[4]; 875 int ret; 876 877 if (alen > 4) { 878 debug("I2C read: addr len %d not supported\n", alen); 879 return 1; 880 } 881 882 if (alen > 0) { 883 xaddr[0] = (addr >> 24) & 0xFF; 884 xaddr[1] = (addr >> 16) & 0xFF; 885 xaddr[2] = (addr >> 8) & 0xFF; 886 xaddr[3] = addr & 0xFF; 887 } 888 889 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 890 /* 891 * EEPROM chips that implement "address overflow" are ones 892 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of 893 * address and the extra bits end up in the "chip address" 894 * bit slots. This makes a 24WC08 (1Kbyte) chip look like 895 * four 256 byte chips. 896 * 897 * Note that we consider the length of the address field to 898 * still be one byte because the extra address bits are 899 * hidden in the chip address. 900 */ 901 if (alen > 0) 902 chip |= ((addr >> (alen * 8)) & 903 CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); 904 #endif 905 i2c_bus = get_bus(g_current_bus); 906 if (!i2c_bus) 907 return -1; 908 909 if (i2c_bus->is_highspeed) 910 ret = hsi2c_read(i2c_bus->hsregs, chip, &xaddr[4 - alen], 911 alen, buffer, len); 912 else 913 ret = i2c_transfer(i2c_bus->regs, I2C_READ, chip << 1, 914 &xaddr[4 - alen], alen, buffer, len); 915 916 if (ret) { 917 if (i2c_bus->is_highspeed) 918 exynos5_i2c_reset(i2c_bus); 919 debug("I2c read failed %d\n", ret); 920 return 1; 921 } 922 return 0; 923 } 924 925 int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) 926 { 927 struct s3c24x0_i2c_bus *i2c_bus; 928 uchar xaddr[4]; 929 int ret; 930 931 if (alen > 4) { 932 debug("I2C write: addr len %d not supported\n", alen); 933 return 1; 934 } 935 936 if (alen > 0) { 937 xaddr[0] = (addr >> 24) & 0xFF; 938 xaddr[1] = (addr >> 16) & 0xFF; 939 xaddr[2] = (addr >> 8) & 0xFF; 940 xaddr[3] = addr & 0xFF; 941 } 942 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 943 /* 944 * EEPROM chips that implement "address overflow" are ones 945 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of 946 * address and the extra bits end up in the "chip address" 947 * bit slots. This makes a 24WC08 (1Kbyte) chip look like 948 * four 256 byte chips. 949 * 950 * Note that we consider the length of the address field to 951 * still be one byte because the extra address bits are 952 * hidden in the chip address. 953 */ 954 if (alen > 0) 955 chip |= ((addr >> (alen * 8)) & 956 CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); 957 #endif 958 i2c_bus = get_bus(g_current_bus); 959 if (!i2c_bus) 960 return -1; 961 962 if (i2c_bus->is_highspeed) 963 ret = hsi2c_write(i2c_bus->hsregs, chip, &xaddr[4 - alen], 964 alen, buffer, len, true); 965 else 966 ret = i2c_transfer(i2c_bus->regs, I2C_WRITE, chip << 1, 967 &xaddr[4 - alen], alen, buffer, len); 968 969 if (ret != 0) { 970 if (i2c_bus->is_highspeed) 971 exynos5_i2c_reset(i2c_bus); 972 return 1; 973 } else { 974 return 0; 975 } 976 } 977 978 #ifdef CONFIG_OF_CONTROL 979 static void process_nodes(const void *blob, int node_list[], int count, 980 int is_highspeed) 981 { 982 struct s3c24x0_i2c_bus *bus; 983 int i; 984 985 for (i = 0; i < count; i++) { 986 int node = node_list[i]; 987 988 if (node <= 0) 989 continue; 990 991 bus = &i2c_bus[i]; 992 bus->active = true; 993 bus->is_highspeed = is_highspeed; 994 995 if (is_highspeed) 996 bus->hsregs = (struct exynos5_hsi2c *) 997 fdtdec_get_addr(blob, node, "reg"); 998 else 999 bus->regs = (struct s3c24x0_i2c *) 1000 fdtdec_get_addr(blob, node, "reg"); 1001 1002 bus->id = pinmux_decode_periph_id(blob, node); 1003 bus->clock_frequency = fdtdec_get_int(blob, node, 1004 "clock-frequency", 1005 CONFIG_SYS_I2C_SPEED); 1006 bus->node = node; 1007 bus->bus_num = i; 1008 exynos_pinmux_config(bus->id, 0); 1009 1010 /* Mark position as used */ 1011 node_list[i] = -1; 1012 } 1013 } 1014 1015 void board_i2c_init(const void *blob) 1016 { 1017 int node_list[CONFIG_MAX_I2C_NUM]; 1018 int count; 1019 1020 /* First get the normal i2c ports */ 1021 count = fdtdec_find_aliases_for_id(blob, "i2c", 1022 COMPAT_SAMSUNG_S3C2440_I2C, node_list, 1023 CONFIG_MAX_I2C_NUM); 1024 process_nodes(blob, node_list, count, 0); 1025 1026 /* Now look for high speed i2c ports */ 1027 count = fdtdec_find_aliases_for_id(blob, "i2c", 1028 COMPAT_SAMSUNG_EXYNOS5_I2C, node_list, 1029 CONFIG_MAX_I2C_NUM); 1030 process_nodes(blob, node_list, count, 1); 1031 1032 } 1033 1034 int i2c_get_bus_num_fdt(int node) 1035 { 1036 int i; 1037 1038 for (i = 0; i < ARRAY_SIZE(i2c_bus); i++) { 1039 if (node == i2c_bus[i].node) 1040 return i; 1041 } 1042 1043 debug("%s: Can't find any matched I2C bus\n", __func__); 1044 return -1; 1045 } 1046 1047 #ifdef CONFIG_I2C_MULTI_BUS 1048 int i2c_reset_port_fdt(const void *blob, int node) 1049 { 1050 struct s3c24x0_i2c_bus *i2c_bus; 1051 int bus; 1052 1053 bus = i2c_get_bus_num_fdt(node); 1054 if (bus < 0) { 1055 debug("could not get bus for node %d\n", node); 1056 return -1; 1057 } 1058 1059 i2c_bus = get_bus(bus); 1060 if (!i2c_bus) { 1061 debug("get_bus() failed for node node %d\n", node); 1062 return -1; 1063 } 1064 1065 if (i2c_bus->is_highspeed) { 1066 if (hsi2c_get_clk_details(i2c_bus)) 1067 return -1; 1068 hsi2c_ch_init(i2c_bus); 1069 } else { 1070 i2c_ch_init(i2c_bus->regs, i2c_bus->clock_frequency, 1071 CONFIG_SYS_I2C_SLAVE); 1072 } 1073 1074 return 0; 1075 } 1076 #endif 1077 #endif 1078 1079 #endif /* CONFIG_HARD_I2C */ 1080