1 /* 2 * (C) Copyright 2002 3 * David Mueller, ELSOFT AG, d.mueller@elsoft.ch 4 * 5 * See file CREDITS for list of people who contributed to this 6 * project. 7 * 8 * This program is free software; you can redistribute it and/or 9 * modify it under the terms of the GNU General Public License as 10 * published by the Free Software Foundation; either version 2 of 11 * the License, or (at your option) any later version. 12 * 13 * This program is distributed in the hope that it will be useful, 14 * but WITHOUT ANY WARRANTY; without even the implied warranty of 15 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 16 * GNU General Public License for more details. 17 * 18 * You should have received a copy of the GNU General Public License 19 * along with this program; if not, write to the Free Software 20 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 21 * MA 02111-1307 USA 22 */ 23 24 /* This code should work for both the S3C2400 and the S3C2410 25 * as they seem to have the same I2C controller inside. 26 * The different address mapping is handled by the s3c24xx.h files below. 27 */ 28 29 #include <common.h> 30 #if defined(CONFIG_S3C2400) 31 #include <s3c2400.h> 32 #elif defined(CONFIG_S3C2410) 33 #include <s3c2410.h> 34 #endif 35 #include <i2c.h> 36 37 #ifdef CONFIG_HARD_I2C 38 39 #define I2C_WRITE 0 40 #define I2C_READ 1 41 42 #define I2C_OK 0 43 #define I2C_NOK 1 44 #define I2C_NACK 2 45 #define I2C_NOK_LA 3 /* Lost arbitration */ 46 #define I2C_NOK_TOUT 4 /* time out */ 47 48 #define I2CSTAT_BSY 0x20 /* Busy bit */ 49 #define I2CSTAT_NACK 0x01 /* Nack bit */ 50 #define I2CCON_IRPND 0x10 /* Interrupt pending bit */ 51 #define I2C_MODE_MT 0xC0 /* Master Transmit Mode */ 52 #define I2C_MODE_MR 0x80 /* Master Receive Mode */ 53 #define I2C_START_STOP 0x20 /* START / STOP */ 54 #define I2C_TXRX_ENA 0x10 /* I2C Tx/Rx enable */ 55 56 #define I2C_TIMEOUT 1 /* 1 second */ 57 58 59 static int GetI2CSDA(void) 60 { 61 S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); 62 63 #ifdef CONFIG_S3C2410 64 return (gpio->GPEDAT & 0x8000) >> 15; 65 #endif 66 #ifdef CONFIG_S3C2400 67 return (gpio->PGDAT & 0x0020) >> 5; 68 #endif 69 } 70 71 #if 0 72 static void SetI2CSDA(int x) 73 { 74 rGPEDAT = (rGPEDAT & ~0x8000) | (x&1) << 15; 75 } 76 #endif 77 78 static void SetI2CSCL(int x) 79 { 80 S3C24X0_GPIO * const gpio = S3C24X0_GetBase_GPIO(); 81 82 #ifdef CONFIG_S3C2410 83 gpio->GPEDAT = (gpio->GPEDAT & ~0x4000) | (x&1) << 14; 84 #endif 85 #ifdef CONFIG_S3C2400 86 gpio->PGDAT = (gpio->PGDAT & ~0x0040) | (x&1) << 6; 87 #endif 88 } 89 90 91 static int WaitForXfer (void) 92 { 93 S3C24X0_I2C *const i2c = S3C24X0_GetBase_I2C (); 94 int i, status; 95 96 i = I2C_TIMEOUT * 10000; 97 status = i2c->IICCON; 98 while ((i > 0) && !(status & I2CCON_IRPND)) { 99 udelay (100); 100 status = i2c->IICCON; 101 i--; 102 } 103 104 return (status & I2CCON_IRPND) ? I2C_OK : I2C_NOK_TOUT; 105 } 106 107 static int IsACK (void) 108 { 109 S3C24X0_I2C *const i2c = S3C24X0_GetBase_I2C (); 110 111 return (!(i2c->IICSTAT & I2CSTAT_NACK)); 112 } 113 114 static void ReadWriteByte (void) 115 { 116 S3C24X0_I2C *const i2c = S3C24X0_GetBase_I2C (); 117 118 i2c->IICCON &= ~I2CCON_IRPND; 119 } 120 121 void i2c_init (int speed, int slaveadd) 122 { 123 S3C24X0_I2C *const i2c = S3C24X0_GetBase_I2C (); 124 S3C24X0_GPIO *const gpio = S3C24X0_GetBase_GPIO (); 125 ulong freq, pres = 16, div; 126 int i, status; 127 128 /* wait for some time to give previous transfer a chance to finish */ 129 130 i = I2C_TIMEOUT * 1000; 131 status = i2c->IICSTAT; 132 while ((i > 0) && (status & I2CSTAT_BSY)) { 133 udelay (1000); 134 status = i2c->IICSTAT; 135 i--; 136 } 137 138 if ((status & I2CSTAT_BSY) || GetI2CSDA () == 0) { 139 #ifdef CONFIG_S3C2410 140 ulong old_gpecon = gpio->GPECON; 141 #endif 142 #ifdef CONFIG_S3C2400 143 ulong old_gpecon = gpio->PGCON; 144 #endif 145 /* bus still busy probably by (most) previously interrupted transfer */ 146 147 #ifdef CONFIG_S3C2410 148 /* set I2CSDA and I2CSCL (GPE15, GPE14) to GPIO */ 149 gpio->GPECON = (gpio->GPECON & ~0xF0000000) | 0x10000000; 150 #endif 151 #ifdef CONFIG_S3C2400 152 /* set I2CSDA and I2CSCL (PG5, PG6) to GPIO */ 153 gpio->PGCON = (gpio->PGCON & ~0x00003c00) | 0x00001000; 154 #endif 155 156 /* toggle I2CSCL until bus idle */ 157 SetI2CSCL (0); 158 udelay (1000); 159 i = 10; 160 while ((i > 0) && (GetI2CSDA () != 1)) { 161 SetI2CSCL (1); 162 udelay (1000); 163 SetI2CSCL (0); 164 udelay (1000); 165 i--; 166 } 167 SetI2CSCL (1); 168 udelay (1000); 169 170 /* restore pin functions */ 171 #ifdef CONFIG_S3C2410 172 gpio->GPECON = old_gpecon; 173 #endif 174 #ifdef CONFIG_S3C2400 175 gpio->PGCON = old_gpecon; 176 #endif 177 } 178 179 /* calculate prescaler and divisor values */ 180 freq = get_PCLK (); 181 if ((freq / pres / (16 + 1)) > speed) 182 /* set prescaler to 512 */ 183 pres = 512; 184 185 div = 0; 186 while ((freq / pres / (div + 1)) > speed) 187 div++; 188 189 /* set prescaler, divisor according to freq, also set 190 * ACKGEN, IRQ */ 191 i2c->IICCON = (div & 0x0F) | 0xA0 | ((pres == 512) ? 0x40 : 0); 192 193 /* init to SLAVE REVEIVE and set slaveaddr */ 194 i2c->IICSTAT = 0; 195 i2c->IICADD = slaveadd; 196 /* program Master Transmit (and implicit STOP) */ 197 i2c->IICSTAT = I2C_MODE_MT | I2C_TXRX_ENA; 198 199 } 200 201 /* 202 * cmd_type is 0 for write, 1 for read. 203 * 204 * addr_len can take any value from 0-255, it is only limited 205 * by the char, we could make it larger if needed. If it is 206 * 0 we skip the address write cycle. 207 */ 208 static 209 int i2c_transfer (unsigned char cmd_type, 210 unsigned char chip, 211 unsigned char addr[], 212 unsigned char addr_len, 213 unsigned char data[], unsigned short data_len) 214 { 215 S3C24X0_I2C *const i2c = S3C24X0_GetBase_I2C (); 216 int i, status, result; 217 218 if (data == 0 || data_len == 0) { 219 /*Don't support data transfer of no length or to address 0 */ 220 printf ("i2c_transfer: bad call\n"); 221 return I2C_NOK; 222 } 223 224 /* Check I2C bus idle */ 225 i = I2C_TIMEOUT * 1000; 226 status = i2c->IICSTAT; 227 while ((i > 0) && (status & I2CSTAT_BSY)) { 228 udelay (1000); 229 status = i2c->IICSTAT; 230 i--; 231 } 232 233 if (status & I2CSTAT_BSY) 234 return I2C_NOK_TOUT; 235 236 i2c->IICCON |= 0x80; 237 result = I2C_OK; 238 239 switch (cmd_type) { 240 case I2C_WRITE: 241 if (addr && addr_len) { 242 i2c->IICDS = chip; 243 /* send START */ 244 i2c->IICSTAT = I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP; 245 i = 0; 246 while ((i < addr_len) && (result == I2C_OK)) { 247 result = WaitForXfer (); 248 i2c->IICDS = addr[i]; 249 ReadWriteByte (); 250 i++; 251 } 252 i = 0; 253 while ((i < data_len) && (result == I2C_OK)) { 254 result = WaitForXfer (); 255 i2c->IICDS = data[i]; 256 ReadWriteByte (); 257 i++; 258 } 259 } else { 260 i2c->IICDS = chip; 261 /* send START */ 262 i2c->IICSTAT = I2C_MODE_MT | I2C_TXRX_ENA | I2C_START_STOP; 263 i = 0; 264 while ((i < data_len) && (result = I2C_OK)) { 265 result = WaitForXfer (); 266 i2c->IICDS = data[i]; 267 ReadWriteByte (); 268 i++; 269 } 270 } 271 272 if (result == I2C_OK) 273 result = WaitForXfer (); 274 275 /* send STOP */ 276 i2c->IICSTAT = I2C_MODE_MR | I2C_TXRX_ENA; 277 ReadWriteByte (); 278 break; 279 280 case I2C_READ: 281 if (addr && addr_len) { 282 i2c->IICSTAT = I2C_MODE_MT | I2C_TXRX_ENA; 283 i2c->IICDS = chip; 284 /* send START */ 285 i2c->IICSTAT |= I2C_START_STOP; 286 result = WaitForXfer (); 287 if (IsACK ()) { 288 i = 0; 289 while ((i < addr_len) && (result == I2C_OK)) { 290 i2c->IICDS = addr[i]; 291 ReadWriteByte (); 292 result = WaitForXfer (); 293 i++; 294 } 295 296 i2c->IICDS = chip; 297 /* resend START */ 298 i2c->IICSTAT = I2C_MODE_MR | I2C_TXRX_ENA | 299 I2C_START_STOP; 300 ReadWriteByte (); 301 result = WaitForXfer (); 302 i = 0; 303 while ((i < data_len) && (result == I2C_OK)) { 304 /* disable ACK for final READ */ 305 if (i == data_len - 1) 306 i2c->IICCON &= ~0x80; 307 ReadWriteByte (); 308 result = WaitForXfer (); 309 data[i] = i2c->IICDS; 310 i++; 311 } 312 } else { 313 result = I2C_NACK; 314 } 315 316 } else { 317 i2c->IICSTAT = I2C_MODE_MR | I2C_TXRX_ENA; 318 i2c->IICDS = chip; 319 /* send START */ 320 i2c->IICSTAT |= I2C_START_STOP; 321 result = WaitForXfer (); 322 323 if (IsACK ()) { 324 i = 0; 325 while ((i < data_len) && (result == I2C_OK)) { 326 /* disable ACK for final READ */ 327 if (i == data_len - 1) 328 i2c->IICCON &= ~0x80; 329 ReadWriteByte (); 330 result = WaitForXfer (); 331 data[i] = i2c->IICDS; 332 i++; 333 } 334 } else { 335 result = I2C_NACK; 336 } 337 } 338 339 /* send STOP */ 340 i2c->IICSTAT = I2C_MODE_MR | I2C_TXRX_ENA; 341 ReadWriteByte (); 342 break; 343 344 default: 345 printf ("i2c_transfer: bad call\n"); 346 result = I2C_NOK; 347 break; 348 } 349 350 return (result); 351 } 352 353 int i2c_probe (uchar chip) 354 { 355 uchar buf[1]; 356 357 buf[0] = 0; 358 359 /* 360 * What is needed is to send the chip address and verify that the 361 * address was <ACK>ed (i.e. there was a chip at that address which 362 * drove the data line low). 363 */ 364 return (i2c_transfer (I2C_READ, chip << 1, 0, 0, buf, 1) != I2C_OK); 365 } 366 367 int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len) 368 { 369 uchar xaddr[4]; 370 int ret; 371 372 if (alen > 4) { 373 printf ("I2C read: addr len %d not supported\n", alen); 374 return 1; 375 } 376 377 if (alen > 0) { 378 xaddr[0] = (addr >> 24) & 0xFF; 379 xaddr[1] = (addr >> 16) & 0xFF; 380 xaddr[2] = (addr >> 8) & 0xFF; 381 xaddr[3] = addr & 0xFF; 382 } 383 384 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 385 /* 386 * EEPROM chips that implement "address overflow" are ones 387 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of 388 * address and the extra bits end up in the "chip address" 389 * bit slots. This makes a 24WC08 (1Kbyte) chip look like 390 * four 256 byte chips. 391 * 392 * Note that we consider the length of the address field to 393 * still be one byte because the extra address bits are 394 * hidden in the chip address. 395 */ 396 if (alen > 0) 397 chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); 398 #endif 399 if ((ret = 400 i2c_transfer (I2C_READ, chip << 1, &xaddr[4 - alen], alen, 401 buffer, len)) != 0) { 402 printf ("I2c read: failed %d\n", ret); 403 return 1; 404 } 405 return 0; 406 } 407 408 int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len) 409 { 410 uchar xaddr[4]; 411 412 if (alen > 4) { 413 printf ("I2C write: addr len %d not supported\n", alen); 414 return 1; 415 } 416 417 if (alen > 0) { 418 xaddr[0] = (addr >> 24) & 0xFF; 419 xaddr[1] = (addr >> 16) & 0xFF; 420 xaddr[2] = (addr >> 8) & 0xFF; 421 xaddr[3] = addr & 0xFF; 422 } 423 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 424 /* 425 * EEPROM chips that implement "address overflow" are ones 426 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of 427 * address and the extra bits end up in the "chip address" 428 * bit slots. This makes a 24WC08 (1Kbyte) chip look like 429 * four 256 byte chips. 430 * 431 * Note that we consider the length of the address field to 432 * still be one byte because the extra address bits are 433 * hidden in the chip address. 434 */ 435 if (alen > 0) 436 chip |= ((addr >> (alen * 8)) & CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); 437 #endif 438 return (i2c_transfer 439 (I2C_WRITE, chip << 1, &xaddr[4 - alen], alen, buffer, 440 len) != 0); 441 } 442 #endif /* CONFIG_HARD_I2C */ 443