1 // SPDX-License-Identifier: GPL-2.0+ 2 /* 3 * (C) Copyright 2015 Google, Inc 4 * 5 * (C) Copyright 2008-2014 Rockchip Electronics 6 * Peter, Software Engineering, <superpeter.cai@gmail.com>. 7 */ 8 9 #include <common.h> 10 #include <clk.h> 11 #include <dm.h> 12 #include <errno.h> 13 #include <i2c.h> 14 #include <asm/io.h> 15 #include <asm/arch/clock.h> 16 #include <asm/arch/i2c.h> 17 #include <asm/arch/periph.h> 18 #include <dm/pinctrl.h> 19 #include <linux/sizes.h> 20 21 /* i2c timerout */ 22 #define I2C_TIMEOUT_MS 100 23 #define I2C_RETRY_COUNT 3 24 25 /* rk i2c fifo max transfer bytes */ 26 #define RK_I2C_FIFO_SIZE 32 27 28 struct rk_i2c { 29 struct clk clk; 30 struct i2c_regs *regs; 31 unsigned int speed; 32 }; 33 34 enum { 35 RK_I2C_LEGACY, 36 RK_I2C_NEW, 37 }; 38 39 /** 40 * @controller_type: i2c controller type 41 */ 42 struct rk_i2c_soc_data { 43 int controller_type; 44 }; 45 46 static inline void rk_i2c_get_div(int div, int *divh, int *divl) 47 { 48 *divl = div / 2; 49 if (div % 2 == 0) 50 *divh = div / 2; 51 else 52 *divh = DIV_ROUND_UP(div, 2); 53 } 54 55 /* 56 * SCL Divisor = 8 * (CLKDIVL+1 + CLKDIVH+1) 57 * SCL = PCLK / SCLK Divisor 58 * i2c_rate = PCLK 59 */ 60 static void rk_i2c_set_clk(struct rk_i2c *i2c, uint32_t scl_rate) 61 { 62 uint32_t i2c_rate; 63 int div, divl, divh; 64 65 /* First get i2c rate from pclk */ 66 i2c_rate = clk_get_rate(&i2c->clk); 67 68 div = DIV_ROUND_UP(i2c_rate, scl_rate * 8) - 2; 69 divh = 0; 70 divl = 0; 71 if (div >= 0) 72 rk_i2c_get_div(div, &divh, &divl); 73 writel(I2C_CLKDIV_VAL(divl, divh), &i2c->regs->clkdiv); 74 75 debug("rk_i2c_set_clk: i2c rate = %d, scl rate = %d\n", i2c_rate, 76 scl_rate); 77 debug("set i2c clk div = %d, divh = %d, divl = %d\n", div, divh, divl); 78 debug("set clk(I2C_CLKDIV: 0x%08x)\n", readl(&i2c->regs->clkdiv)); 79 } 80 81 static void rk_i2c_show_regs(struct i2c_regs *regs) 82 { 83 #ifdef DEBUG 84 uint i; 85 86 debug("i2c_con: 0x%08x\n", readl(®s->con)); 87 debug("i2c_clkdiv: 0x%08x\n", readl(®s->clkdiv)); 88 debug("i2c_mrxaddr: 0x%08x\n", readl(®s->mrxaddr)); 89 debug("i2c_mrxraddR: 0x%08x\n", readl(®s->mrxraddr)); 90 debug("i2c_mtxcnt: 0x%08x\n", readl(®s->mtxcnt)); 91 debug("i2c_mrxcnt: 0x%08x\n", readl(®s->mrxcnt)); 92 debug("i2c_ien: 0x%08x\n", readl(®s->ien)); 93 debug("i2c_ipd: 0x%08x\n", readl(®s->ipd)); 94 debug("i2c_fcnt: 0x%08x\n", readl(®s->fcnt)); 95 for (i = 0; i < 8; i++) 96 debug("i2c_txdata%d: 0x%08x\n", i, readl(®s->txdata[i])); 97 for (i = 0; i < 8; i++) 98 debug("i2c_rxdata%d: 0x%08x\n", i, readl(®s->rxdata[i])); 99 #endif 100 } 101 102 static int rk_i2c_send_start_bit(struct rk_i2c *i2c) 103 { 104 struct i2c_regs *regs = i2c->regs; 105 ulong start; 106 107 debug("I2c Send Start bit.\n"); 108 writel(I2C_IPD_ALL_CLEAN, ®s->ipd); 109 110 writel(I2C_CON_EN | I2C_CON_START, ®s->con); 111 writel(I2C_STARTIEN, ®s->ien); 112 113 start = get_timer(0); 114 while (1) { 115 if (readl(®s->ipd) & I2C_STARTIPD) { 116 writel(I2C_STARTIPD, ®s->ipd); 117 break; 118 } 119 if (get_timer(start) > I2C_TIMEOUT_MS) { 120 debug("I2C Send Start Bit Timeout\n"); 121 rk_i2c_show_regs(regs); 122 return -ETIMEDOUT; 123 } 124 udelay(1); 125 } 126 127 return 0; 128 } 129 130 static int rk_i2c_send_stop_bit(struct rk_i2c *i2c) 131 { 132 struct i2c_regs *regs = i2c->regs; 133 ulong start; 134 135 debug("I2c Send Stop bit.\n"); 136 writel(I2C_IPD_ALL_CLEAN, ®s->ipd); 137 138 writel(I2C_CON_EN | I2C_CON_STOP, ®s->con); 139 writel(I2C_CON_STOP, ®s->ien); 140 141 start = get_timer(0); 142 while (1) { 143 if (readl(®s->ipd) & I2C_STOPIPD) { 144 writel(I2C_STOPIPD, ®s->ipd); 145 break; 146 } 147 if (get_timer(start) > I2C_TIMEOUT_MS) { 148 debug("I2C Send Start Bit Timeout\n"); 149 rk_i2c_show_regs(regs); 150 return -ETIMEDOUT; 151 } 152 udelay(1); 153 } 154 155 return 0; 156 } 157 158 static inline void rk_i2c_disable(struct rk_i2c *i2c) 159 { 160 writel(0, &i2c->regs->con); 161 } 162 163 static int rk_i2c_read(struct rk_i2c *i2c, uchar chip, uint reg, uint r_len, 164 uchar *buf, uint b_len) 165 { 166 struct i2c_regs *regs = i2c->regs; 167 uchar *pbuf = buf; 168 uint bytes_remain_len = b_len; 169 uint bytes_xferred = 0; 170 uint words_xferred = 0; 171 ulong start; 172 uint con = 0; 173 uint rxdata; 174 uint i, j; 175 int err; 176 bool snd_chunk = false; 177 178 debug("rk_i2c_read: chip = %d, reg = %d, r_len = %d, b_len = %d\n", 179 chip, reg, r_len, b_len); 180 181 err = rk_i2c_send_start_bit(i2c); 182 if (err) 183 return err; 184 185 writel(I2C_MRXADDR_SET(1, chip << 1 | 1), ®s->mrxaddr); 186 if (r_len == 0) { 187 writel(0, ®s->mrxraddr); 188 } else if (r_len < 4) { 189 writel(I2C_MRXRADDR_SET(r_len, reg), ®s->mrxraddr); 190 } else { 191 debug("I2C Read: addr len %d not supported\n", r_len); 192 return -EIO; 193 } 194 195 while (bytes_remain_len) { 196 if (bytes_remain_len > RK_I2C_FIFO_SIZE) { 197 con = I2C_CON_EN; 198 bytes_xferred = 32; 199 } else { 200 /* 201 * The hw can read up to 32 bytes at a time. If we need 202 * more than one chunk, send an ACK after the last byte. 203 */ 204 con = I2C_CON_EN | I2C_CON_LASTACK; 205 bytes_xferred = bytes_remain_len; 206 } 207 words_xferred = DIV_ROUND_UP(bytes_xferred, 4); 208 209 /* 210 * make sure we are in plain RX mode if we read a second chunk 211 */ 212 if (snd_chunk) 213 con |= I2C_CON_MOD(I2C_MODE_RX); 214 else 215 con |= I2C_CON_MOD(I2C_MODE_TRX); 216 217 writel(con, ®s->con); 218 writel(bytes_xferred, ®s->mrxcnt); 219 writel(I2C_MBRFIEN | I2C_NAKRCVIEN, ®s->ien); 220 221 start = get_timer(0); 222 while (1) { 223 if (readl(®s->ipd) & I2C_NAKRCVIPD) { 224 writel(I2C_NAKRCVIPD, ®s->ipd); 225 err = -EREMOTEIO; 226 } 227 if (readl(®s->ipd) & I2C_MBRFIPD) { 228 writel(I2C_MBRFIPD, ®s->ipd); 229 break; 230 } 231 if (get_timer(start) > I2C_TIMEOUT_MS) { 232 debug("I2C Read Data Timeout\n"); 233 err = -ETIMEDOUT; 234 rk_i2c_show_regs(regs); 235 goto i2c_exit; 236 } 237 udelay(1); 238 } 239 240 for (i = 0; i < words_xferred; i++) { 241 rxdata = readl(®s->rxdata[i]); 242 debug("I2c Read RXDATA[%d] = 0x%x\n", i, rxdata); 243 for (j = 0; j < 4; j++) { 244 if ((i * 4 + j) == bytes_xferred) 245 break; 246 *pbuf++ = (rxdata >> (j * 8)) & 0xff; 247 } 248 } 249 250 bytes_remain_len -= bytes_xferred; 251 snd_chunk = true; 252 debug("I2C Read bytes_remain_len %d\n", bytes_remain_len); 253 } 254 255 i2c_exit: 256 rk_i2c_send_stop_bit(i2c); 257 rk_i2c_disable(i2c); 258 259 return err; 260 } 261 262 static int rk_i2c_write(struct rk_i2c *i2c, uchar chip, uint reg, uint r_len, 263 uchar *buf, uint b_len) 264 { 265 struct i2c_regs *regs = i2c->regs; 266 int err; 267 uchar *pbuf = buf; 268 uint bytes_remain_len = b_len + r_len + 1; 269 uint bytes_xferred = 0; 270 uint words_xferred = 0; 271 ulong start; 272 uint txdata; 273 uint i, j; 274 275 debug("rk_i2c_write: chip = %d, reg = %d, r_len = %d, b_len = %d\n", 276 chip, reg, r_len, b_len); 277 err = rk_i2c_send_start_bit(i2c); 278 if (err) 279 return err; 280 281 while (bytes_remain_len) { 282 if (bytes_remain_len > RK_I2C_FIFO_SIZE) 283 bytes_xferred = RK_I2C_FIFO_SIZE; 284 else 285 bytes_xferred = bytes_remain_len; 286 words_xferred = DIV_ROUND_UP(bytes_xferred, 4); 287 288 for (i = 0; i < words_xferred; i++) { 289 txdata = 0; 290 for (j = 0; j < 4; j++) { 291 if ((i * 4 + j) == bytes_xferred) 292 break; 293 294 if (i == 0 && j == 0 && pbuf == buf) { 295 txdata |= (chip << 1); 296 } else if (i == 0 && j <= r_len && pbuf == buf) { 297 txdata |= (reg & 298 (0xff << ((j - 1) * 8))) << 8; 299 } else { 300 txdata |= (*pbuf++)<<(j * 8); 301 } 302 } 303 writel(txdata, ®s->txdata[i]); 304 debug("I2c Write TXDATA[%d] = 0x%08x\n", i, txdata); 305 } 306 307 writel(I2C_CON_EN | I2C_CON_MOD(I2C_MODE_TX), ®s->con); 308 writel(bytes_xferred, ®s->mtxcnt); 309 writel(I2C_MBTFIEN | I2C_NAKRCVIEN, ®s->ien); 310 311 start = get_timer(0); 312 while (1) { 313 if (readl(®s->ipd) & I2C_NAKRCVIPD) { 314 writel(I2C_NAKRCVIPD, ®s->ipd); 315 err = -EREMOTEIO; 316 } 317 if (readl(®s->ipd) & I2C_MBTFIPD) { 318 writel(I2C_MBTFIPD, ®s->ipd); 319 break; 320 } 321 if (get_timer(start) > I2C_TIMEOUT_MS) { 322 debug("I2C Write Data Timeout\n"); 323 err = -ETIMEDOUT; 324 rk_i2c_show_regs(regs); 325 goto i2c_exit; 326 } 327 udelay(1); 328 } 329 330 bytes_remain_len -= bytes_xferred; 331 debug("I2C Write bytes_remain_len %d\n", bytes_remain_len); 332 } 333 334 i2c_exit: 335 rk_i2c_send_stop_bit(i2c); 336 rk_i2c_disable(i2c); 337 338 return err; 339 } 340 341 static int rockchip_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, 342 int nmsgs) 343 { 344 struct rk_i2c *i2c = dev_get_priv(bus); 345 int ret; 346 347 debug("i2c_xfer: %d messages\n", nmsgs); 348 for (; nmsgs > 0; nmsgs--, msg++) { 349 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len); 350 if (msg->flags & I2C_M_RD) { 351 ret = rk_i2c_read(i2c, msg->addr, 0, 0, msg->buf, 352 msg->len); 353 } else { 354 ret = rk_i2c_write(i2c, msg->addr, 0, 0, msg->buf, 355 msg->len); 356 } 357 if (ret) { 358 debug("i2c_write: error sending\n"); 359 return -EREMOTEIO; 360 } 361 } 362 363 return 0; 364 } 365 366 int rockchip_i2c_set_bus_speed(struct udevice *bus, unsigned int speed) 367 { 368 struct rk_i2c *i2c = dev_get_priv(bus); 369 370 rk_i2c_set_clk(i2c, speed); 371 372 return 0; 373 } 374 375 static int rockchip_i2c_ofdata_to_platdata(struct udevice *bus) 376 { 377 struct rk_i2c *priv = dev_get_priv(bus); 378 int ret; 379 380 ret = clk_get_by_index(bus, 0, &priv->clk); 381 if (ret < 0) { 382 debug("%s: Could not get clock for %s: %d\n", __func__, 383 bus->name, ret); 384 return ret; 385 } 386 387 return 0; 388 } 389 390 static int rockchip_i2c_probe(struct udevice *bus) 391 { 392 struct rk_i2c *priv = dev_get_priv(bus); 393 struct rk_i2c_soc_data *soc_data; 394 struct udevice *pinctrl; 395 int bus_nr; 396 int ret; 397 398 priv->regs = dev_read_addr_ptr(bus); 399 400 soc_data = (struct rk_i2c_soc_data*)dev_get_driver_data(bus); 401 402 if (soc_data->controller_type == RK_I2C_LEGACY) { 403 ret = dev_read_alias_seq(bus, &bus_nr); 404 if (ret < 0) { 405 debug("%s: Could not get alias for %s: %d\n", 406 __func__, bus->name, ret); 407 return ret; 408 } 409 410 ret = uclass_get_device(UCLASS_PINCTRL, 0, &pinctrl); 411 if (ret) { 412 debug("%s: Cannot find pinctrl device\n", __func__); 413 return ret; 414 } 415 416 /* pinctrl will switch I2C to new type */ 417 ret = pinctrl_request_noflags(pinctrl, PERIPH_ID_I2C0 + bus_nr); 418 if (ret) { 419 debug("%s: Failed to switch I2C to new type %s: %d\n", 420 __func__, bus->name, ret); 421 return ret; 422 } 423 } 424 425 return 0; 426 } 427 428 static const struct dm_i2c_ops rockchip_i2c_ops = { 429 .xfer = rockchip_i2c_xfer, 430 .set_bus_speed = rockchip_i2c_set_bus_speed, 431 }; 432 433 static const struct rk_i2c_soc_data rk3066_soc_data = { 434 .controller_type = RK_I2C_LEGACY, 435 }; 436 437 static const struct rk_i2c_soc_data rk3188_soc_data = { 438 .controller_type = RK_I2C_LEGACY, 439 }; 440 441 static const struct rk_i2c_soc_data rk3228_soc_data = { 442 .controller_type = RK_I2C_NEW, 443 }; 444 445 static const struct rk_i2c_soc_data rk3288_soc_data = { 446 .controller_type = RK_I2C_NEW, 447 }; 448 449 static const struct rk_i2c_soc_data rk3328_soc_data = { 450 .controller_type = RK_I2C_NEW, 451 }; 452 453 static const struct rk_i2c_soc_data rk3399_soc_data = { 454 .controller_type = RK_I2C_NEW, 455 }; 456 457 static const struct udevice_id rockchip_i2c_ids[] = { 458 { 459 .compatible = "rockchip,rk3066-i2c", 460 .data = (ulong)&rk3066_soc_data, 461 }, 462 { 463 .compatible = "rockchip,rk3188-i2c", 464 .data = (ulong)&rk3188_soc_data, 465 }, 466 { 467 .compatible = "rockchip,rk3228-i2c", 468 .data = (ulong)&rk3228_soc_data, 469 }, 470 { 471 .compatible = "rockchip,rk3288-i2c", 472 .data = (ulong)&rk3288_soc_data, 473 }, 474 { 475 .compatible = "rockchip,rk3328-i2c", 476 .data = (ulong)&rk3328_soc_data, 477 }, 478 { 479 .compatible = "rockchip,rk3399-i2c", 480 .data = (ulong)&rk3399_soc_data, 481 }, 482 { } 483 }; 484 485 U_BOOT_DRIVER(i2c_rockchip) = { 486 .name = "i2c_rockchip", 487 .id = UCLASS_I2C, 488 .of_match = rockchip_i2c_ids, 489 .ofdata_to_platdata = rockchip_i2c_ofdata_to_platdata, 490 .probe = rockchip_i2c_probe, 491 .priv_auto_alloc_size = sizeof(struct rk_i2c), 492 .ops = &rockchip_i2c_ops, 493 }; 494