xref: /openbmc/u-boot/drivers/i2c/rk_i2c.c (revision 3ce88cd7)
1 /*
2  * (C) Copyright 2015 Google, Inc
3  *
4  * (C) Copyright 2008-2014 Rockchip Electronics
5  * Peter, Software Engineering, <superpeter.cai@gmail.com>.
6  *
7  * SPDX-License-Identifier:     GPL-2.0+
8  */
9 
10 #include <common.h>
11 #include <clk.h>
12 #include <dm.h>
13 #include <errno.h>
14 #include <i2c.h>
15 #include <asm/io.h>
16 #include <asm/arch/clock.h>
17 #include <asm/arch/i2c.h>
18 #include <asm/arch/periph.h>
19 #include <dm/pinctrl.h>
20 #include <linux/sizes.h>
21 
22 /* i2c timerout */
23 #define I2C_TIMEOUT_MS		100
24 #define I2C_RETRY_COUNT		3
25 
26 /* rk i2c fifo max transfer bytes */
27 #define RK_I2C_FIFO_SIZE	32
28 
29 struct rk_i2c {
30 	struct clk clk;
31 	struct i2c_regs *regs;
32 	unsigned int speed;
33 };
34 
35 static inline void rk_i2c_get_div(int div, int *divh, int *divl)
36 {
37 	*divl = div / 2;
38 	if (div % 2 == 0)
39 		*divh = div / 2;
40 	else
41 		*divh = DIV_ROUND_UP(div, 2);
42 }
43 
44 /*
45  * SCL Divisor = 8 * (CLKDIVL+1 + CLKDIVH+1)
46  * SCL = PCLK / SCLK Divisor
47  * i2c_rate = PCLK
48  */
49 static void rk_i2c_set_clk(struct rk_i2c *i2c, uint32_t scl_rate)
50 {
51 	uint32_t i2c_rate;
52 	int div, divl, divh;
53 
54 	/* First get i2c rate from pclk */
55 	i2c_rate = clk_get_rate(&i2c->clk);
56 
57 	div = DIV_ROUND_UP(i2c_rate, scl_rate * 8) - 2;
58 	divh = 0;
59 	divl = 0;
60 	if (div >= 0)
61 		rk_i2c_get_div(div, &divh, &divl);
62 	writel(I2C_CLKDIV_VAL(divl, divh), &i2c->regs->clkdiv);
63 
64 	debug("rk_i2c_set_clk: i2c rate = %d, scl rate = %d\n", i2c_rate,
65 	      scl_rate);
66 	debug("set i2c clk div = %d, divh = %d, divl = %d\n", div, divh, divl);
67 	debug("set clk(I2C_CLKDIV: 0x%08x)\n", readl(&i2c->regs->clkdiv));
68 }
69 
70 static void rk_i2c_show_regs(struct i2c_regs *regs)
71 {
72 #ifdef DEBUG
73 	uint i;
74 
75 	debug("i2c_con: 0x%08x\n", readl(&regs->con));
76 	debug("i2c_clkdiv: 0x%08x\n", readl(&regs->clkdiv));
77 	debug("i2c_mrxaddr: 0x%08x\n", readl(&regs->mrxaddr));
78 	debug("i2c_mrxraddR: 0x%08x\n", readl(&regs->mrxraddr));
79 	debug("i2c_mtxcnt: 0x%08x\n", readl(&regs->mtxcnt));
80 	debug("i2c_mrxcnt: 0x%08x\n", readl(&regs->mrxcnt));
81 	debug("i2c_ien: 0x%08x\n", readl(&regs->ien));
82 	debug("i2c_ipd: 0x%08x\n", readl(&regs->ipd));
83 	debug("i2c_fcnt: 0x%08x\n", readl(&regs->fcnt));
84 	for (i = 0; i < 8; i++)
85 		debug("i2c_txdata%d: 0x%08x\n", i, readl(&regs->txdata[i]));
86 	for (i = 0; i < 8; i++)
87 		debug("i2c_rxdata%d: 0x%08x\n", i, readl(&regs->rxdata[i]));
88 #endif
89 }
90 
91 static int rk_i2c_send_start_bit(struct rk_i2c *i2c)
92 {
93 	struct i2c_regs *regs = i2c->regs;
94 	ulong start;
95 
96 	debug("I2c Send Start bit.\n");
97 	writel(I2C_IPD_ALL_CLEAN, &regs->ipd);
98 
99 	writel(I2C_CON_EN | I2C_CON_START, &regs->con);
100 	writel(I2C_STARTIEN, &regs->ien);
101 
102 	start = get_timer(0);
103 	while (1) {
104 		if (readl(&regs->ipd) & I2C_STARTIPD) {
105 			writel(I2C_STARTIPD, &regs->ipd);
106 			break;
107 		}
108 		if (get_timer(start) > I2C_TIMEOUT_MS) {
109 			debug("I2C Send Start Bit Timeout\n");
110 			rk_i2c_show_regs(regs);
111 			return -ETIMEDOUT;
112 		}
113 		udelay(1);
114 	}
115 
116 	return 0;
117 }
118 
119 static int rk_i2c_send_stop_bit(struct rk_i2c *i2c)
120 {
121 	struct i2c_regs *regs = i2c->regs;
122 	ulong start;
123 
124 	debug("I2c Send Stop bit.\n");
125 	writel(I2C_IPD_ALL_CLEAN, &regs->ipd);
126 
127 	writel(I2C_CON_EN | I2C_CON_STOP, &regs->con);
128 	writel(I2C_CON_STOP, &regs->ien);
129 
130 	start = get_timer(0);
131 	while (1) {
132 		if (readl(&regs->ipd) & I2C_STOPIPD) {
133 			writel(I2C_STOPIPD, &regs->ipd);
134 			break;
135 		}
136 		if (get_timer(start) > I2C_TIMEOUT_MS) {
137 			debug("I2C Send Start Bit Timeout\n");
138 			rk_i2c_show_regs(regs);
139 			return -ETIMEDOUT;
140 		}
141 		udelay(1);
142 	}
143 
144 	return 0;
145 }
146 
147 static inline void rk_i2c_disable(struct rk_i2c *i2c)
148 {
149 	writel(0, &i2c->regs->con);
150 }
151 
152 static int rk_i2c_read(struct rk_i2c *i2c, uchar chip, uint reg, uint r_len,
153 		       uchar *buf, uint b_len)
154 {
155 	struct i2c_regs *regs = i2c->regs;
156 	uchar *pbuf = buf;
157 	uint bytes_remain_len = b_len;
158 	uint bytes_xferred = 0;
159 	uint words_xferred = 0;
160 	ulong start;
161 	uint con = 0;
162 	uint rxdata;
163 	uint i, j;
164 	int err;
165 	bool snd_chunk = false;
166 
167 	debug("rk_i2c_read: chip = %d, reg = %d, r_len = %d, b_len = %d\n",
168 	      chip, reg, r_len, b_len);
169 
170 	err = rk_i2c_send_start_bit(i2c);
171 	if (err)
172 		return err;
173 
174 	writel(I2C_MRXADDR_SET(1, chip << 1 | 1), &regs->mrxaddr);
175 	if (r_len == 0) {
176 		writel(0, &regs->mrxraddr);
177 	} else if (r_len < 4) {
178 		writel(I2C_MRXRADDR_SET(r_len, reg), &regs->mrxraddr);
179 	} else {
180 		debug("I2C Read: addr len %d not supported\n", r_len);
181 		return -EIO;
182 	}
183 
184 	while (bytes_remain_len) {
185 		if (bytes_remain_len > RK_I2C_FIFO_SIZE) {
186 			con = I2C_CON_EN;
187 			bytes_xferred = 32;
188 		} else {
189 			/*
190 			 * The hw can read up to 32 bytes at a time. If we need
191 			 * more than one chunk, send an ACK after the last byte.
192 			 */
193 			con = I2C_CON_EN | I2C_CON_LASTACK;
194 			bytes_xferred = bytes_remain_len;
195 		}
196 		words_xferred = DIV_ROUND_UP(bytes_xferred, 4);
197 
198 		/*
199 		 * make sure we are in plain RX mode if we read a second chunk
200 		 */
201 		if (snd_chunk)
202 			con |= I2C_CON_MOD(I2C_MODE_RX);
203 		else
204 			con |= I2C_CON_MOD(I2C_MODE_TRX);
205 
206 		writel(con, &regs->con);
207 		writel(bytes_xferred, &regs->mrxcnt);
208 		writel(I2C_MBRFIEN | I2C_NAKRCVIEN, &regs->ien);
209 
210 		start = get_timer(0);
211 		while (1) {
212 			if (readl(&regs->ipd) & I2C_NAKRCVIPD) {
213 				writel(I2C_NAKRCVIPD, &regs->ipd);
214 				err = -EREMOTEIO;
215 			}
216 			if (readl(&regs->ipd) & I2C_MBRFIPD) {
217 				writel(I2C_MBRFIPD, &regs->ipd);
218 				break;
219 			}
220 			if (get_timer(start) > I2C_TIMEOUT_MS) {
221 				debug("I2C Read Data Timeout\n");
222 				err =  -ETIMEDOUT;
223 				rk_i2c_show_regs(regs);
224 				goto i2c_exit;
225 			}
226 			udelay(1);
227 		}
228 
229 		for (i = 0; i < words_xferred; i++) {
230 			rxdata = readl(&regs->rxdata[i]);
231 			debug("I2c Read RXDATA[%d] = 0x%x\n", i, rxdata);
232 			for (j = 0; j < 4; j++) {
233 				if ((i * 4 + j) == bytes_xferred)
234 					break;
235 				*pbuf++ = (rxdata >> (j * 8)) & 0xff;
236 			}
237 		}
238 
239 		bytes_remain_len -= bytes_xferred;
240 		snd_chunk = true;
241 		debug("I2C Read bytes_remain_len %d\n", bytes_remain_len);
242 	}
243 
244 i2c_exit:
245 	rk_i2c_send_stop_bit(i2c);
246 	rk_i2c_disable(i2c);
247 
248 	return err;
249 }
250 
251 static int rk_i2c_write(struct rk_i2c *i2c, uchar chip, uint reg, uint r_len,
252 			uchar *buf, uint b_len)
253 {
254 	struct i2c_regs *regs = i2c->regs;
255 	int err;
256 	uchar *pbuf = buf;
257 	uint bytes_remain_len = b_len + r_len + 1;
258 	uint bytes_xferred = 0;
259 	uint words_xferred = 0;
260 	ulong start;
261 	uint txdata;
262 	uint i, j;
263 
264 	debug("rk_i2c_write: chip = %d, reg = %d, r_len = %d, b_len = %d\n",
265 	      chip, reg, r_len, b_len);
266 	err = rk_i2c_send_start_bit(i2c);
267 	if (err)
268 		return err;
269 
270 	while (bytes_remain_len) {
271 		if (bytes_remain_len > RK_I2C_FIFO_SIZE)
272 			bytes_xferred = RK_I2C_FIFO_SIZE;
273 		else
274 			bytes_xferred = bytes_remain_len;
275 		words_xferred = DIV_ROUND_UP(bytes_xferred, 4);
276 
277 		for (i = 0; i < words_xferred; i++) {
278 			txdata = 0;
279 			for (j = 0; j < 4; j++) {
280 				if ((i * 4 + j) == bytes_xferred)
281 					break;
282 
283 				if (i == 0 && j == 0 && pbuf == buf) {
284 					txdata |= (chip << 1);
285 				} else if (i == 0 && j <= r_len && pbuf == buf) {
286 					txdata |= (reg &
287 						(0xff << ((j - 1) * 8))) << 8;
288 				} else {
289 					txdata |= (*pbuf++)<<(j * 8);
290 				}
291 			}
292 			writel(txdata, &regs->txdata[i]);
293 			debug("I2c Write TXDATA[%d] = 0x%08x\n", i, txdata);
294 		}
295 
296 		writel(I2C_CON_EN | I2C_CON_MOD(I2C_MODE_TX), &regs->con);
297 		writel(bytes_xferred, &regs->mtxcnt);
298 		writel(I2C_MBTFIEN | I2C_NAKRCVIEN, &regs->ien);
299 
300 		start = get_timer(0);
301 		while (1) {
302 			if (readl(&regs->ipd) & I2C_NAKRCVIPD) {
303 				writel(I2C_NAKRCVIPD, &regs->ipd);
304 				err = -EREMOTEIO;
305 			}
306 			if (readl(&regs->ipd) & I2C_MBTFIPD) {
307 				writel(I2C_MBTFIPD, &regs->ipd);
308 				break;
309 			}
310 			if (get_timer(start) > I2C_TIMEOUT_MS) {
311 				debug("I2C Write Data Timeout\n");
312 				err =  -ETIMEDOUT;
313 				rk_i2c_show_regs(regs);
314 				goto i2c_exit;
315 			}
316 			udelay(1);
317 		}
318 
319 		bytes_remain_len -= bytes_xferred;
320 		debug("I2C Write bytes_remain_len %d\n", bytes_remain_len);
321 	}
322 
323 i2c_exit:
324 	rk_i2c_send_stop_bit(i2c);
325 	rk_i2c_disable(i2c);
326 
327 	return err;
328 }
329 
330 static int rockchip_i2c_xfer(struct udevice *bus, struct i2c_msg *msg,
331 			     int nmsgs)
332 {
333 	struct rk_i2c *i2c = dev_get_priv(bus);
334 	int ret;
335 
336 	debug("i2c_xfer: %d messages\n", nmsgs);
337 	for (; nmsgs > 0; nmsgs--, msg++) {
338 		debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len);
339 		if (msg->flags & I2C_M_RD) {
340 			ret = rk_i2c_read(i2c, msg->addr, 0, 0, msg->buf,
341 					  msg->len);
342 		} else {
343 			ret = rk_i2c_write(i2c, msg->addr, 0, 0, msg->buf,
344 					   msg->len);
345 		}
346 		if (ret) {
347 			debug("i2c_write: error sending\n");
348 			return -EREMOTEIO;
349 		}
350 	}
351 
352 	return 0;
353 }
354 
355 int rockchip_i2c_set_bus_speed(struct udevice *bus, unsigned int speed)
356 {
357 	struct rk_i2c *i2c = dev_get_priv(bus);
358 
359 	rk_i2c_set_clk(i2c, speed);
360 
361 	return 0;
362 }
363 
364 static int rockchip_i2c_ofdata_to_platdata(struct udevice *bus)
365 {
366 	struct rk_i2c *priv = dev_get_priv(bus);
367 	int ret;
368 
369 	ret = clk_get_by_index(bus, 0, &priv->clk);
370 	if (ret < 0) {
371 		debug("%s: Could not get clock for %s: %d\n", __func__,
372 		      bus->name, ret);
373 		return ret;
374 	}
375 
376 	return 0;
377 }
378 
379 static int rockchip_i2c_probe(struct udevice *bus)
380 {
381 	struct rk_i2c *priv = dev_get_priv(bus);
382 
383 	priv->regs = dev_read_addr_ptr(bus);
384 
385 	return 0;
386 }
387 
388 static const struct dm_i2c_ops rockchip_i2c_ops = {
389 	.xfer		= rockchip_i2c_xfer,
390 	.set_bus_speed	= rockchip_i2c_set_bus_speed,
391 };
392 
393 static const struct udevice_id rockchip_i2c_ids[] = {
394 	{ .compatible = "rockchip,rk3066-i2c" },
395 	{ .compatible = "rockchip,rk3188-i2c" },
396 	{ .compatible = "rockchip,rk3288-i2c" },
397 	{ .compatible = "rockchip,rk3328-i2c" },
398 	{ .compatible = "rockchip,rk3399-i2c" },
399 	{ }
400 };
401 
402 U_BOOT_DRIVER(i2c_rockchip) = {
403 	.name	= "i2c_rockchip",
404 	.id	= UCLASS_I2C,
405 	.of_match = rockchip_i2c_ids,
406 	.ofdata_to_platdata = rockchip_i2c_ofdata_to_platdata,
407 	.probe	= rockchip_i2c_probe,
408 	.priv_auto_alloc_size = sizeof(struct rk_i2c),
409 	.ops	= &rockchip_i2c_ops,
410 };
411