1 // SPDX-License-Identifier: GPL-2.0 2 /* 3 * drivers/i2c/rcar_i2c.c 4 * 5 * Copyright (C) 2013 Renesas Electronics Corporation 6 * Copyright (C) 2013 Nobuhiro Iwamatsu <nobuhiro.iwamatsu.yj@renesas.com> 7 * 8 * NOTE: This driver should be converted to driver model before June 2017. 9 * Please see doc/driver-model/i2c-howto.txt for instructions. 10 */ 11 12 #include <common.h> 13 #include <i2c.h> 14 #include <asm/io.h> 15 16 DECLARE_GLOBAL_DATA_PTR; 17 18 struct rcar_i2c { 19 u32 icscr; 20 u32 icmcr; 21 u32 icssr; 22 u32 icmsr; 23 u32 icsier; 24 u32 icmier; 25 u32 icccr; 26 u32 icsar; 27 u32 icmar; 28 u32 icrxdtxd; 29 u32 icccr2; 30 u32 icmpr; 31 u32 ichpr; 32 u32 iclpr; 33 }; 34 35 #define MCR_MDBS 0x80 /* non-fifo mode switch */ 36 #define MCR_FSCL 0x40 /* override SCL pin */ 37 #define MCR_FSDA 0x20 /* override SDA pin */ 38 #define MCR_OBPC 0x10 /* override pins */ 39 #define MCR_MIE 0x08 /* master if enable */ 40 #define MCR_TSBE 0x04 41 #define MCR_FSB 0x02 /* force stop bit */ 42 #define MCR_ESG 0x01 /* en startbit gen. */ 43 44 #define MSR_MASK 0x7f 45 #define MSR_MNR 0x40 /* nack received */ 46 #define MSR_MAL 0x20 /* arbitration lost */ 47 #define MSR_MST 0x10 /* sent a stop */ 48 #define MSR_MDE 0x08 49 #define MSR_MDT 0x04 50 #define MSR_MDR 0x02 51 #define MSR_MAT 0x01 /* slave addr xfer done */ 52 53 static const struct rcar_i2c *i2c_dev[CONFIF_SYS_RCAR_I2C_NUM_CONTROLLERS] = { 54 (struct rcar_i2c *)CONFIG_SYS_RCAR_I2C0_BASE, 55 (struct rcar_i2c *)CONFIG_SYS_RCAR_I2C1_BASE, 56 (struct rcar_i2c *)CONFIG_SYS_RCAR_I2C2_BASE, 57 (struct rcar_i2c *)CONFIG_SYS_RCAR_I2C3_BASE, 58 }; 59 60 static void rcar_i2c_raw_rw_common(struct rcar_i2c *dev, u8 chip, uint addr) 61 { 62 /* set slave address */ 63 writel(chip << 1, &dev->icmar); 64 /* set register address */ 65 writel(addr, &dev->icrxdtxd); 66 /* clear status */ 67 writel(0, &dev->icmsr); 68 /* start master send */ 69 writel(MCR_MDBS | MCR_MIE | MCR_ESG, &dev->icmcr); 70 71 while ((readl(&dev->icmsr) & (MSR_MAT | MSR_MDE)) 72 != (MSR_MAT | MSR_MDE)) 73 udelay(10); 74 75 /* clear ESG */ 76 writel(MCR_MDBS | MCR_MIE, &dev->icmcr); 77 /* start SCLclk */ 78 writel(~(MSR_MAT | MSR_MDE), &dev->icmsr); 79 80 while (!(readl(&dev->icmsr) & MSR_MDE)) 81 udelay(10); 82 } 83 84 static void rcar_i2c_raw_rw_finish(struct rcar_i2c *dev) 85 { 86 while (!(readl(&dev->icmsr) & MSR_MST)) 87 udelay(10); 88 89 writel(0, &dev->icmcr); 90 } 91 92 static int 93 rcar_i2c_raw_write(struct rcar_i2c *dev, u8 chip, uint addr, u8 *val, int size) 94 { 95 rcar_i2c_raw_rw_common(dev, chip, addr); 96 97 /* set send date */ 98 writel(*val, &dev->icrxdtxd); 99 /* start SCLclk */ 100 writel(~MSR_MDE, &dev->icmsr); 101 102 while (!(readl(&dev->icmsr) & MSR_MDE)) 103 udelay(10); 104 105 /* set stop condition */ 106 writel(MCR_MDBS | MCR_MIE | MCR_FSB, &dev->icmcr); 107 /* start SCLclk */ 108 writel(~MSR_MDE, &dev->icmsr); 109 110 rcar_i2c_raw_rw_finish(dev); 111 112 return 0; 113 } 114 115 static u8 116 rcar_i2c_raw_read(struct rcar_i2c *dev, u8 chip, uint addr) 117 { 118 u8 ret; 119 120 rcar_i2c_raw_rw_common(dev, chip, addr); 121 122 /* set slave address, receive */ 123 writel((chip << 1) | 1, &dev->icmar); 124 /* start master receive */ 125 writel(MCR_MDBS | MCR_MIE | MCR_ESG, &dev->icmcr); 126 /* clear status */ 127 writel(0, &dev->icmsr); 128 129 while ((readl(&dev->icmsr) & (MSR_MAT | MSR_MDR)) 130 != (MSR_MAT | MSR_MDR)) 131 udelay(10); 132 133 /* clear ESG */ 134 writel(MCR_MDBS | MCR_MIE, &dev->icmcr); 135 /* prepare stop condition */ 136 writel(MCR_MDBS | MCR_MIE | MCR_FSB, &dev->icmcr); 137 /* start SCLclk */ 138 writel(~(MSR_MAT | MSR_MDR), &dev->icmsr); 139 140 while (!(readl(&dev->icmsr) & MSR_MDR)) 141 udelay(10); 142 143 /* get receive data */ 144 ret = (u8)readl(&dev->icrxdtxd); 145 /* start SCLclk */ 146 writel(~MSR_MDR, &dev->icmsr); 147 148 rcar_i2c_raw_rw_finish(dev); 149 150 return ret; 151 } 152 153 /* 154 * SCL = iicck / (20 + SCGD * 8 + F[(ticf + tr + intd) * iicck]) 155 * iicck : I2C internal clock < 20 MHz 156 * ticf : I2C SCL falling time: 35 ns 157 * tr : I2C SCL rising time: 200 ns 158 * intd : LSI internal delay: I2C0: 50 ns I2C1-3: 5 159 * F[n] : n rounded up to an integer 160 */ 161 static u32 rcar_clock_gen(int i2c_no, u32 bus_speed) 162 { 163 u32 iicck, f, scl, scgd; 164 u32 intd = 5; 165 166 int bit = 0, cdf_width = 3; 167 for (bit = 0; bit < (1 << cdf_width); bit++) { 168 iicck = CONFIG_HP_CLK_FREQ / (1 + bit); 169 if (iicck < 20000000) 170 break; 171 } 172 173 if (bit > (1 << cdf_width)) { 174 puts("rcar-i2c: Can not get CDF\n"); 175 return 0; 176 } 177 178 if (i2c_no == 0) 179 intd = 50; 180 181 f = (35 + 200 + intd) * (iicck / 1000000000); 182 183 for (scgd = 0; scgd < 0x40; scgd++) { 184 scl = iicck / (20 + (scgd * 8) + f); 185 if (scl <= bus_speed) 186 break; 187 } 188 189 if (scgd > 0x40) { 190 puts("rcar-i2c: Can not get SDGB\n"); 191 return 0; 192 } 193 194 debug("%s: scl: %d\n", __func__, scl); 195 debug("%s: bit %x\n", __func__, bit); 196 debug("%s: scgd %x\n", __func__, scgd); 197 debug("%s: iccr %x\n", __func__, (scgd << (cdf_width) | bit)); 198 199 return scgd << (cdf_width) | bit; 200 } 201 202 static void 203 rcar_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd) 204 { 205 struct rcar_i2c *dev = (struct rcar_i2c *)i2c_dev[adap->hwadapnr]; 206 u32 icccr = 0; 207 208 /* No i2c support prior to relocation */ 209 if (!(gd->flags & GD_FLG_RELOC)) 210 return; 211 212 /* 213 * reset slave mode. 214 * slave mode is not used on this driver 215 */ 216 writel(0, &dev->icsier); 217 writel(0, &dev->icsar); 218 writel(0, &dev->icscr); 219 writel(0, &dev->icssr); 220 221 /* reset master mode */ 222 writel(0, &dev->icmier); 223 writel(0, &dev->icmcr); 224 writel(0, &dev->icmsr); 225 writel(0, &dev->icmar); 226 227 icccr = rcar_clock_gen(adap->hwadapnr, adap->speed); 228 if (icccr == 0) 229 puts("I2C: Init failed\n"); 230 else 231 writel(icccr, &dev->icccr); 232 } 233 234 static int rcar_i2c_read(struct i2c_adapter *adap, uint8_t chip, 235 uint addr, int alen, u8 *data, int len) 236 { 237 struct rcar_i2c *dev = (struct rcar_i2c *)i2c_dev[adap->hwadapnr]; 238 int i; 239 240 for (i = 0; i < len; i++) 241 data[i] = rcar_i2c_raw_read(dev, chip, addr + i); 242 243 return 0; 244 } 245 246 static int rcar_i2c_write(struct i2c_adapter *adap, uint8_t chip, uint addr, 247 int alen, u8 *data, int len) 248 { 249 struct rcar_i2c *dev = (struct rcar_i2c *)i2c_dev[adap->hwadapnr]; 250 return rcar_i2c_raw_write(dev, chip, addr, data, len); 251 } 252 253 static int 254 rcar_i2c_probe(struct i2c_adapter *adap, u8 dev) 255 { 256 return rcar_i2c_read(adap, dev, 0, 0, NULL, 0); 257 } 258 259 static unsigned int rcar_i2c_set_bus_speed(struct i2c_adapter *adap, 260 unsigned int speed) 261 { 262 struct rcar_i2c *dev = (struct rcar_i2c *)i2c_dev[adap->hwadapnr]; 263 u32 icccr; 264 int ret = 0; 265 266 rcar_i2c_raw_rw_finish(dev); 267 268 icccr = rcar_clock_gen(adap->hwadapnr, speed); 269 if (icccr == 0) { 270 puts("I2C: Init failed\n"); 271 ret = -1; 272 } else { 273 writel(icccr, &dev->icccr); 274 } 275 return ret; 276 } 277 278 /* 279 * Register RCAR i2c adapters 280 */ 281 U_BOOT_I2C_ADAP_COMPLETE(rcar_0, rcar_i2c_init, rcar_i2c_probe, rcar_i2c_read, 282 rcar_i2c_write, rcar_i2c_set_bus_speed, 283 CONFIG_SYS_RCAR_I2C0_SPEED, 0, 0) 284 U_BOOT_I2C_ADAP_COMPLETE(rcar_1, rcar_i2c_init, rcar_i2c_probe, rcar_i2c_read, 285 rcar_i2c_write, rcar_i2c_set_bus_speed, 286 CONFIG_SYS_RCAR_I2C1_SPEED, 0, 1) 287 U_BOOT_I2C_ADAP_COMPLETE(rcar_2, rcar_i2c_init, rcar_i2c_probe, rcar_i2c_read, 288 rcar_i2c_write, rcar_i2c_set_bus_speed, 289 CONFIG_SYS_RCAR_I2C2_SPEED, 0, 2) 290 U_BOOT_I2C_ADAP_COMPLETE(rcar_3, rcar_i2c_init, rcar_i2c_probe, rcar_i2c_read, 291 rcar_i2c_write, rcar_i2c_set_bus_speed, 292 CONFIG_SYS_RCAR_I2C3_SPEED, 0, 3) 293