xref: /openbmc/u-boot/drivers/i2c/omap24xx_i2c.c (revision e5c5301f)
1 /*
2  * Basic I2C functions
3  *
4  * Copyright (c) 2004 Texas Instruments
5  *
6  * This package is free software;  you can redistribute it and/or
7  * modify it under the terms of the license found in the file
8  * named COPYING that should have accompanied this file.
9  *
10  * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR
11  * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED
12  * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE.
13  *
14  * Author: Jian Zhang jzhang@ti.com, Texas Instruments
15  *
16  * Copyright (c) 2003 Wolfgang Denk, wd@denx.de
17  * Rewritten to fit into the current U-Boot framework
18  *
19  * Adapted for OMAP2420 I2C, r-woodruff2@ti.com
20  *
21  * Copyright (c) 2013 Lubomir Popov <lpopov@mm-sol.com>, MM Solutions
22  * New i2c_read, i2c_write and i2c_probe functions, tested on OMAP4
23  * (4430/60/70), OMAP5 (5430) and AM335X (3359); should work on older
24  * OMAPs and derivatives as well. The only anticipated exception would
25  * be the OMAP2420, which shall require driver modification.
26  * - Rewritten i2c_read to operate correctly with all types of chips
27  *   (old function could not read consistent data from some I2C slaves).
28  * - Optimized i2c_write.
29  * - New i2c_probe, performs write access vs read. The old probe could
30  *   hang the system under certain conditions (e.g. unconfigured pads).
31  * - The read/write/probe functions try to identify unconfigured bus.
32  * - Status functions now read irqstatus_raw as per TRM guidelines
33  *   (except for OMAP243X and OMAP34XX).
34  * - Driver now supports up to I2C5 (OMAP5).
35  */
36 
37 #include <common.h>
38 #include <i2c.h>
39 
40 #include <asm/arch/i2c.h>
41 #include <asm/io.h>
42 
43 #include "omap24xx_i2c.h"
44 
45 DECLARE_GLOBAL_DATA_PTR;
46 
47 #define I2C_TIMEOUT	1000
48 
49 /* Absolutely safe for status update at 100 kHz I2C: */
50 #define I2C_WAIT	200
51 
52 static int wait_for_bb(struct i2c_adapter *adap);
53 static struct i2c *omap24_get_base(struct i2c_adapter *adap);
54 static u16 wait_for_event(struct i2c_adapter *adap);
55 static void flush_fifo(struct i2c_adapter *adap);
56 
57 static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd)
58 {
59 	struct i2c *i2c_base = omap24_get_base(adap);
60 	int psc, fsscll, fssclh;
61 	int hsscll = 0, hssclh = 0;
62 	u32 scll, sclh;
63 	int timeout = I2C_TIMEOUT;
64 
65 	/* Only handle standard, fast and high speeds */
66 	if ((speed != OMAP_I2C_STANDARD) &&
67 	    (speed != OMAP_I2C_FAST_MODE) &&
68 	    (speed != OMAP_I2C_HIGH_SPEED)) {
69 		printf("Error : I2C unsupported speed %d\n", speed);
70 		return;
71 	}
72 
73 	psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK;
74 	psc -= 1;
75 	if (psc < I2C_PSC_MIN) {
76 		printf("Error : I2C unsupported prescalar %d\n", psc);
77 		return;
78 	}
79 
80 	if (speed == OMAP_I2C_HIGH_SPEED) {
81 		/* High speed */
82 
83 		/* For first phase of HS mode */
84 		fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK /
85 			(2 * OMAP_I2C_FAST_MODE);
86 
87 		fsscll -= I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM;
88 		fssclh -= I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM;
89 		if (((fsscll < 0) || (fssclh < 0)) ||
90 		    ((fsscll > 255) || (fssclh > 255))) {
91 			puts("Error : I2C initializing first phase clock\n");
92 			return;
93 		}
94 
95 		/* For second phase of HS mode */
96 		hsscll = hssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
97 
98 		hsscll -= I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM;
99 		hssclh -= I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM;
100 		if (((fsscll < 0) || (fssclh < 0)) ||
101 		    ((fsscll > 255) || (fssclh > 255))) {
102 			puts("Error : I2C initializing second phase clock\n");
103 			return;
104 		}
105 
106 		scll = (unsigned int)hsscll << 8 | (unsigned int)fsscll;
107 		sclh = (unsigned int)hssclh << 8 | (unsigned int)fssclh;
108 
109 	} else {
110 		/* Standard and fast speed */
111 		fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed);
112 
113 		fsscll -= I2C_FASTSPEED_SCLL_TRIM;
114 		fssclh -= I2C_FASTSPEED_SCLH_TRIM;
115 		if (((fsscll < 0) || (fssclh < 0)) ||
116 		    ((fsscll > 255) || (fssclh > 255))) {
117 			puts("Error : I2C initializing clock\n");
118 			return;
119 		}
120 
121 		scll = (unsigned int)fsscll;
122 		sclh = (unsigned int)fssclh;
123 	}
124 
125 	if (readw(&i2c_base->con) & I2C_CON_EN) {
126 		writew(0, &i2c_base->con);
127 		udelay(50000);
128 	}
129 
130 	writew(0x2, &i2c_base->sysc); /* for ES2 after soft reset */
131 	udelay(1000);
132 
133 	writew(I2C_CON_EN, &i2c_base->con);
134 	while (!(readw(&i2c_base->syss) & I2C_SYSS_RDONE) && timeout--) {
135 		if (timeout <= 0) {
136 			puts("ERROR: Timeout in soft-reset\n");
137 			return;
138 		}
139 		udelay(1000);
140 	}
141 
142 	writew(0, &i2c_base->con);
143 	writew(psc, &i2c_base->psc);
144 	writew(scll, &i2c_base->scll);
145 	writew(sclh, &i2c_base->sclh);
146 
147 	/* own address */
148 	writew(slaveadd, &i2c_base->oa);
149 	writew(I2C_CON_EN, &i2c_base->con);
150 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
151 	/*
152 	 * Have to enable interrupts for OMAP2/3, these IPs don't have
153 	 * an 'irqstatus_raw' register and we shall have to poll 'stat'
154 	 */
155 	writew(I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE |
156 	       I2C_IE_NACK_IE | I2C_IE_AL_IE, &i2c_base->ie);
157 #endif
158 	udelay(1000);
159 	flush_fifo(adap);
160 	writew(0xFFFF, &i2c_base->stat);
161 	writew(0, &i2c_base->cnt);
162 }
163 
164 static void flush_fifo(struct i2c_adapter *adap)
165 {
166 	struct i2c *i2c_base = omap24_get_base(adap);
167 	u16 stat;
168 
169 	/* note: if you try and read data when its not there or ready
170 	 * you get a bus error
171 	 */
172 	while (1) {
173 		stat = readw(&i2c_base->stat);
174 		if (stat == I2C_STAT_RRDY) {
175 			readb(&i2c_base->data);
176 			writew(I2C_STAT_RRDY, &i2c_base->stat);
177 			udelay(1000);
178 		} else
179 			break;
180 	}
181 }
182 
183 /*
184  * i2c_probe: Use write access. Allows to identify addresses that are
185  *            write-only (like the config register of dual-port EEPROMs)
186  */
187 static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip)
188 {
189 	struct i2c *i2c_base = omap24_get_base(adap);
190 	u16 status;
191 	int res = 1; /* default = fail */
192 
193 	if (chip == readw(&i2c_base->oa))
194 		return res;
195 
196 	/* Wait until bus is free */
197 	if (wait_for_bb(adap))
198 		return res;
199 
200 	/* No data transfer, slave addr only */
201 	writew(0, &i2c_base->cnt);
202 	/* Set slave address */
203 	writew(chip, &i2c_base->sa);
204 	/* Stop bit needed here */
205 	writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
206 	       I2C_CON_STP, &i2c_base->con);
207 
208 	status = wait_for_event(adap);
209 
210 	if ((status & ~I2C_STAT_XRDY) == 0 || (status & I2C_STAT_AL)) {
211 		/*
212 		 * With current high-level command implementation, notifying
213 		 * the user shall flood the console with 127 messages. If
214 		 * silent exit is desired upon unconfigured bus, remove the
215 		 * following 'if' section:
216 		 */
217 		if (status == I2C_STAT_XRDY)
218 			printf("i2c_probe: pads on bus %d probably not configured (status=0x%x)\n",
219 			       adap->hwadapnr, status);
220 
221 		goto pr_exit;
222 	}
223 
224 	/* Check for ACK (!NAK) */
225 	if (!(status & I2C_STAT_NACK)) {
226 		res = 0;			/* Device found */
227 		udelay(I2C_WAIT);		/* Required by AM335X in SPL */
228 		/* Abort transfer (force idle state) */
229 		writew(I2C_CON_MST | I2C_CON_TRX, &i2c_base->con); /* Reset */
230 		udelay(1000);
231 		writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_TRX |
232 		       I2C_CON_STP, &i2c_base->con);		/* STP */
233 	}
234 pr_exit:
235 	flush_fifo(adap);
236 	writew(0xFFFF, &i2c_base->stat);
237 	writew(0, &i2c_base->cnt);
238 	return res;
239 }
240 
241 /*
242  * i2c_read: Function now uses a single I2C read transaction with bulk transfer
243  *           of the requested number of bytes (note that the 'i2c md' command
244  *           limits this to 16 bytes anyway). If CONFIG_I2C_REPEATED_START is
245  *           defined in the board config header, this transaction shall be with
246  *           Repeated Start (Sr) between the address and data phases; otherwise
247  *           Stop-Start (P-S) shall be used (some I2C chips do require a P-S).
248  *           The address (reg offset) may be 0, 1 or 2 bytes long.
249  *           Function now reads correctly from chips that return more than one
250  *           byte of data per addressed register (like TI temperature sensors),
251  *           or that do not need a register address at all (such as some clock
252  *           distributors).
253  */
254 static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr,
255 			   int alen, uchar *buffer, int len)
256 {
257 	struct i2c *i2c_base = omap24_get_base(adap);
258 	int i2c_error = 0;
259 	u16 status;
260 
261 	if (alen < 0) {
262 		puts("I2C read: addr len < 0\n");
263 		return 1;
264 	}
265 	if (len < 0) {
266 		puts("I2C read: data len < 0\n");
267 		return 1;
268 	}
269 	if (buffer == NULL) {
270 		puts("I2C read: NULL pointer passed\n");
271 		return 1;
272 	}
273 
274 	if (alen > 2) {
275 		printf("I2C read: addr len %d not supported\n", alen);
276 		return 1;
277 	}
278 
279 	if (addr + len > (1 << 16)) {
280 		puts("I2C read: address out of range\n");
281 		return 1;
282 	}
283 
284 	/* Wait until bus not busy */
285 	if (wait_for_bb(adap))
286 		return 1;
287 
288 	/* Zero, one or two bytes reg address (offset) */
289 	writew(alen, &i2c_base->cnt);
290 	/* Set slave address */
291 	writew(chip, &i2c_base->sa);
292 
293 	if (alen) {
294 		/* Must write reg offset first */
295 #ifdef CONFIG_I2C_REPEATED_START
296 		/* No stop bit, use Repeated Start (Sr) */
297 		writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT |
298 		       I2C_CON_TRX, &i2c_base->con);
299 #else
300 		/* Stop - Start (P-S) */
301 		writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP |
302 		       I2C_CON_TRX, &i2c_base->con);
303 #endif
304 		/* Send register offset */
305 		while (1) {
306 			status = wait_for_event(adap);
307 			/* Try to identify bus that is not padconf'd for I2C */
308 			if (status == I2C_STAT_XRDY) {
309 				i2c_error = 2;
310 				printf("i2c_read (addr phase): pads on bus %d probably not configured (status=0x%x)\n",
311 				       adap->hwadapnr, status);
312 				goto rd_exit;
313 			}
314 			if (status == 0 || status & I2C_STAT_NACK) {
315 				i2c_error = 1;
316 				printf("i2c_read: error waiting for addr ACK (status=0x%x)\n",
317 				       status);
318 				goto rd_exit;
319 			}
320 			if (alen) {
321 				if (status & I2C_STAT_XRDY) {
322 					alen--;
323 					/* Do we have to use byte access? */
324 					writeb((addr >> (8 * alen)) & 0xff,
325 					       &i2c_base->data);
326 					writew(I2C_STAT_XRDY, &i2c_base->stat);
327 				}
328 			}
329 			if (status & I2C_STAT_ARDY) {
330 				writew(I2C_STAT_ARDY, &i2c_base->stat);
331 				break;
332 			}
333 		}
334 	}
335 	/* Set slave address */
336 	writew(chip, &i2c_base->sa);
337 	/* Read len bytes from slave */
338 	writew(len, &i2c_base->cnt);
339 	/* Need stop bit here */
340 	writew(I2C_CON_EN | I2C_CON_MST |
341 	       I2C_CON_STT | I2C_CON_STP,
342 	       &i2c_base->con);
343 
344 	/* Receive data */
345 	while (1) {
346 		status = wait_for_event(adap);
347 		/*
348 		 * Try to identify bus that is not padconf'd for I2C. This
349 		 * state could be left over from previous transactions if
350 		 * the address phase is skipped due to alen=0.
351 		 */
352 		if (status == I2C_STAT_XRDY) {
353 			i2c_error = 2;
354 			printf("i2c_read (data phase): pads on bus %d probably not configured (status=0x%x)\n",
355 			       adap->hwadapnr, status);
356 			goto rd_exit;
357 		}
358 		if (status == 0 || status & I2C_STAT_NACK) {
359 			i2c_error = 1;
360 			goto rd_exit;
361 		}
362 		if (status & I2C_STAT_RRDY) {
363 			*buffer++ = readb(&i2c_base->data);
364 			writew(I2C_STAT_RRDY, &i2c_base->stat);
365 		}
366 		if (status & I2C_STAT_ARDY) {
367 			writew(I2C_STAT_ARDY, &i2c_base->stat);
368 			break;
369 		}
370 	}
371 
372 rd_exit:
373 	flush_fifo(adap);
374 	writew(0xFFFF, &i2c_base->stat);
375 	writew(0, &i2c_base->cnt);
376 	return i2c_error;
377 }
378 
379 /* i2c_write: Address (reg offset) may be 0, 1 or 2 bytes long. */
380 static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr,
381 			    int alen, uchar *buffer, int len)
382 {
383 	struct i2c *i2c_base = omap24_get_base(adap);
384 	int i;
385 	u16 status;
386 	int i2c_error = 0;
387 
388 	if (alen < 0) {
389 		puts("I2C write: addr len < 0\n");
390 		return 1;
391 	}
392 
393 	if (len < 0) {
394 		puts("I2C write: data len < 0\n");
395 		return 1;
396 	}
397 
398 	if (buffer == NULL) {
399 		puts("I2C write: NULL pointer passed\n");
400 		return 1;
401 	}
402 
403 	if (alen > 2) {
404 		printf("I2C write: addr len %d not supported\n", alen);
405 		return 1;
406 	}
407 
408 	if (addr + len > (1 << 16)) {
409 		printf("I2C write: address 0x%x + 0x%x out of range\n",
410 		       addr, len);
411 		return 1;
412 	}
413 
414 	/* Wait until bus not busy */
415 	if (wait_for_bb(adap))
416 		return 1;
417 
418 	/* Start address phase - will write regoffset + len bytes data */
419 	writew(alen + len, &i2c_base->cnt);
420 	/* Set slave address */
421 	writew(chip, &i2c_base->sa);
422 	/* Stop bit needed here */
423 	writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX |
424 	       I2C_CON_STP, &i2c_base->con);
425 
426 	while (alen) {
427 		/* Must write reg offset (one or two bytes) */
428 		status = wait_for_event(adap);
429 		/* Try to identify bus that is not padconf'd for I2C */
430 		if (status == I2C_STAT_XRDY) {
431 			i2c_error = 2;
432 			printf("i2c_write: pads on bus %d probably not configured (status=0x%x)\n",
433 			       adap->hwadapnr, status);
434 			goto wr_exit;
435 		}
436 		if (status == 0 || status & I2C_STAT_NACK) {
437 			i2c_error = 1;
438 			printf("i2c_write: error waiting for addr ACK (status=0x%x)\n",
439 			       status);
440 			goto wr_exit;
441 		}
442 		if (status & I2C_STAT_XRDY) {
443 			alen--;
444 			writeb((addr >> (8 * alen)) & 0xff, &i2c_base->data);
445 			writew(I2C_STAT_XRDY, &i2c_base->stat);
446 		} else {
447 			i2c_error = 1;
448 			printf("i2c_write: bus not ready for addr Tx (status=0x%x)\n",
449 			       status);
450 			goto wr_exit;
451 		}
452 	}
453 	/* Address phase is over, now write data */
454 	for (i = 0; i < len; i++) {
455 		status = wait_for_event(adap);
456 		if (status == 0 || status & I2C_STAT_NACK) {
457 			i2c_error = 1;
458 			printf("i2c_write: error waiting for data ACK (status=0x%x)\n",
459 			       status);
460 			goto wr_exit;
461 		}
462 		if (status & I2C_STAT_XRDY) {
463 			writeb(buffer[i], &i2c_base->data);
464 			writew(I2C_STAT_XRDY, &i2c_base->stat);
465 		} else {
466 			i2c_error = 1;
467 			printf("i2c_write: bus not ready for data Tx (i=%d)\n",
468 			       i);
469 			goto wr_exit;
470 		}
471 	}
472 
473 wr_exit:
474 	flush_fifo(adap);
475 	writew(0xFFFF, &i2c_base->stat);
476 	writew(0, &i2c_base->cnt);
477 	return i2c_error;
478 }
479 
480 /*
481  * Wait for the bus to be free by checking the Bus Busy (BB)
482  * bit to become clear
483  */
484 static int wait_for_bb(struct i2c_adapter *adap)
485 {
486 	struct i2c *i2c_base = omap24_get_base(adap);
487 	int timeout = I2C_TIMEOUT;
488 	u16 stat;
489 
490 	writew(0xFFFF, &i2c_base->stat);	/* clear current interrupts...*/
491 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
492 	while ((stat = readw(&i2c_base->stat) & I2C_STAT_BB) && timeout--) {
493 #else
494 	/* Read RAW status */
495 	while ((stat = readw(&i2c_base->irqstatus_raw) &
496 		I2C_STAT_BB) && timeout--) {
497 #endif
498 		writew(stat, &i2c_base->stat);
499 		udelay(I2C_WAIT);
500 	}
501 
502 	if (timeout <= 0) {
503 		printf("Timed out in wait_for_bb: status=%04x\n",
504 		       stat);
505 		return 1;
506 	}
507 	writew(0xFFFF, &i2c_base->stat);	 /* clear delayed stuff*/
508 	return 0;
509 }
510 
511 /*
512  * Wait for the I2C controller to complete current action
513  * and update status
514  */
515 static u16 wait_for_event(struct i2c_adapter *adap)
516 {
517 	struct i2c *i2c_base = omap24_get_base(adap);
518 	u16 status;
519 	int timeout = I2C_TIMEOUT;
520 
521 	do {
522 		udelay(I2C_WAIT);
523 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX)
524 		status = readw(&i2c_base->stat);
525 #else
526 		/* Read RAW status */
527 		status = readw(&i2c_base->irqstatus_raw);
528 #endif
529 	} while (!(status &
530 		   (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY |
531 		    I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK |
532 		    I2C_STAT_AL)) && timeout--);
533 
534 	if (timeout <= 0) {
535 		printf("Timed out in wait_for_event: status=%04x\n",
536 		       status);
537 		/*
538 		 * If status is still 0 here, probably the bus pads have
539 		 * not been configured for I2C, and/or pull-ups are missing.
540 		 */
541 		printf("Check if pads/pull-ups of bus %d are properly configured\n",
542 		       adap->hwadapnr);
543 		writew(0xFFFF, &i2c_base->stat);
544 		status = 0;
545 	}
546 
547 	return status;
548 }
549 
550 static struct i2c *omap24_get_base(struct i2c_adapter *adap)
551 {
552 	switch (adap->hwadapnr) {
553 	case 0:
554 		return (struct i2c *)I2C_BASE1;
555 		break;
556 	case 1:
557 		return (struct i2c *)I2C_BASE2;
558 		break;
559 #if (I2C_BUS_MAX > 2)
560 	case 2:
561 		return (struct i2c *)I2C_BASE3;
562 		break;
563 #if (I2C_BUS_MAX > 3)
564 	case 3:
565 		return (struct i2c *)I2C_BASE4;
566 		break;
567 #if (I2C_BUS_MAX > 4)
568 	case 4:
569 		return (struct i2c *)I2C_BASE5;
570 		break;
571 #endif
572 #endif
573 #endif
574 	default:
575 		printf("wrong hwadapnr: %d\n", adap->hwadapnr);
576 		break;
577 	}
578 	return NULL;
579 }
580 
581 #if !defined(CONFIG_SYS_OMAP24_I2C_SPEED1)
582 #define CONFIG_SYS_OMAP24_I2C_SPEED1 CONFIG_SYS_OMAP24_I2C_SPEED
583 #endif
584 #if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE1)
585 #define CONFIG_SYS_OMAP24_I2C_SLAVE1 CONFIG_SYS_OMAP24_I2C_SLAVE
586 #endif
587 
588 U_BOOT_I2C_ADAP_COMPLETE(omap24_0, omap24_i2c_init, omap24_i2c_probe,
589 			 omap24_i2c_read, omap24_i2c_write, NULL,
590 			 CONFIG_SYS_OMAP24_I2C_SPEED,
591 			 CONFIG_SYS_OMAP24_I2C_SLAVE,
592 			 0)
593 U_BOOT_I2C_ADAP_COMPLETE(omap24_1, omap24_i2c_init, omap24_i2c_probe,
594 			 omap24_i2c_read, omap24_i2c_write, NULL,
595 			 CONFIG_SYS_OMAP24_I2C_SPEED1,
596 			 CONFIG_SYS_OMAP24_I2C_SLAVE1,
597 			 1)
598 #if (I2C_BUS_MAX > 2)
599 #if !defined(CONFIG_SYS_OMAP24_I2C_SPEED2)
600 #define CONFIG_SYS_OMAP24_I2C_SPEED2 CONFIG_SYS_OMAP24_I2C_SPEED
601 #endif
602 #if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE2)
603 #define CONFIG_SYS_OMAP24_I2C_SLAVE2 CONFIG_SYS_OMAP24_I2C_SLAVE
604 #endif
605 
606 U_BOOT_I2C_ADAP_COMPLETE(omap24_2, omap24_i2c_init, omap24_i2c_probe,
607 			 omap24_i2c_read, omap24_i2c_write, NULL,
608 			 CONFIG_SYS_OMAP24_I2C_SPEED2,
609 			 CONFIG_SYS_OMAP24_I2C_SLAVE2,
610 			 2)
611 #if (I2C_BUS_MAX > 3)
612 #if !defined(CONFIG_SYS_OMAP24_I2C_SPEED3)
613 #define CONFIG_SYS_OMAP24_I2C_SPEED3 CONFIG_SYS_OMAP24_I2C_SPEED
614 #endif
615 #if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE3)
616 #define CONFIG_SYS_OMAP24_I2C_SLAVE3 CONFIG_SYS_OMAP24_I2C_SLAVE
617 #endif
618 
619 U_BOOT_I2C_ADAP_COMPLETE(omap24_3, omap24_i2c_init, omap24_i2c_probe,
620 			 omap24_i2c_read, omap24_i2c_write, NULL,
621 			 CONFIG_SYS_OMAP24_I2C_SPEED3,
622 			 CONFIG_SYS_OMAP24_I2C_SLAVE3,
623 			 3)
624 #if (I2C_BUS_MAX > 4)
625 #if !defined(CONFIG_SYS_OMAP24_I2C_SPEED4)
626 #define CONFIG_SYS_OMAP24_I2C_SPEED4 CONFIG_SYS_OMAP24_I2C_SPEED
627 #endif
628 #if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE4)
629 #define CONFIG_SYS_OMAP24_I2C_SLAVE4 CONFIG_SYS_OMAP24_I2C_SLAVE
630 #endif
631 
632 U_BOOT_I2C_ADAP_COMPLETE(omap24_4, omap24_i2c_init, omap24_i2c_probe,
633 			 omap24_i2c_read, omap24_i2c_write, NULL,
634 			 CONFIG_SYS_OMAP24_I2C_SPEED4,
635 			 CONFIG_SYS_OMAP24_I2C_SLAVE4,
636 			 4)
637 #endif
638 #endif
639 #endif
640