1 /* 2 * Basic I2C functions 3 * 4 * Copyright (c) 2004 Texas Instruments 5 * 6 * This package is free software; you can redistribute it and/or 7 * modify it under the terms of the license found in the file 8 * named COPYING that should have accompanied this file. 9 * 10 * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR 11 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED 12 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. 13 * 14 * Author: Jian Zhang jzhang@ti.com, Texas Instruments 15 * 16 * Copyright (c) 2003 Wolfgang Denk, wd@denx.de 17 * Rewritten to fit into the current U-Boot framework 18 * 19 * Adapted for OMAP2420 I2C, r-woodruff2@ti.com 20 * 21 */ 22 23 #include <common.h> 24 25 #include <asm/arch/i2c.h> 26 #include <asm/io.h> 27 28 #include "omap24xx_i2c.h" 29 30 #define I2C_TIMEOUT 10 31 32 static void wait_for_bb (void); 33 static u16 wait_for_pin (void); 34 static void flush_fifo(void); 35 36 static struct i2c *i2c_base = (struct i2c *)I2C_DEFAULT_BASE; 37 38 static unsigned int bus_initialized[I2C_BUS_MAX]; 39 static unsigned int current_bus; 40 41 void i2c_init (int speed, int slaveadd) 42 { 43 int psc, fsscll, fssclh; 44 int hsscll = 0, hssclh = 0; 45 u32 scll, sclh; 46 int timeout = I2C_TIMEOUT; 47 48 /* Only handle standard, fast and high speeds */ 49 if ((speed != OMAP_I2C_STANDARD) && 50 (speed != OMAP_I2C_FAST_MODE) && 51 (speed != OMAP_I2C_HIGH_SPEED)) { 52 printf("Error : I2C unsupported speed %d\n", speed); 53 return; 54 } 55 56 psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK; 57 psc -= 1; 58 if (psc < I2C_PSC_MIN) { 59 printf("Error : I2C unsupported prescalar %d\n", psc); 60 return; 61 } 62 63 if (speed == OMAP_I2C_HIGH_SPEED) { 64 /* High speed */ 65 66 /* For first phase of HS mode */ 67 fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK / 68 (2 * OMAP_I2C_FAST_MODE); 69 70 fsscll -= I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM; 71 fssclh -= I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM; 72 if (((fsscll < 0) || (fssclh < 0)) || 73 ((fsscll > 255) || (fssclh > 255))) { 74 printf("Error : I2C initializing first phase clock\n"); 75 return; 76 } 77 78 /* For second phase of HS mode */ 79 hsscll = hssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed); 80 81 hsscll -= I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM; 82 hssclh -= I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM; 83 if (((fsscll < 0) || (fssclh < 0)) || 84 ((fsscll > 255) || (fssclh > 255))) { 85 printf("Error : I2C initializing second phase clock\n"); 86 return; 87 } 88 89 scll = (unsigned int)hsscll << 8 | (unsigned int)fsscll; 90 sclh = (unsigned int)hssclh << 8 | (unsigned int)fssclh; 91 92 } else { 93 /* Standard and fast speed */ 94 fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed); 95 96 fsscll -= I2C_FASTSPEED_SCLL_TRIM; 97 fssclh -= I2C_FASTSPEED_SCLH_TRIM; 98 if (((fsscll < 0) || (fssclh < 0)) || 99 ((fsscll > 255) || (fssclh > 255))) { 100 printf("Error : I2C initializing clock\n"); 101 return; 102 } 103 104 scll = (unsigned int)fsscll; 105 sclh = (unsigned int)fssclh; 106 } 107 108 if (readw (&i2c_base->con) & I2C_CON_EN) { 109 writew (0, &i2c_base->con); 110 udelay (50000); 111 } 112 113 writew(0x2, &i2c_base->sysc); /* for ES2 after soft reset */ 114 udelay(1000); 115 116 writew(I2C_CON_EN, &i2c_base->con); 117 while (!(readw(&i2c_base->syss) & I2C_SYSS_RDONE) && timeout--) { 118 if (timeout <= 0) { 119 printf("ERROR: Timeout in soft-reset\n"); 120 return; 121 } 122 udelay(1000); 123 } 124 125 writew(0, &i2c_base->con); 126 writew(psc, &i2c_base->psc); 127 writew(scll, &i2c_base->scll); 128 writew(sclh, &i2c_base->sclh); 129 130 /* own address */ 131 writew (slaveadd, &i2c_base->oa); 132 writew (I2C_CON_EN, &i2c_base->con); 133 134 /* have to enable intrrupts or OMAP i2c module doesn't work */ 135 writew (I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | 136 I2C_IE_NACK_IE | I2C_IE_AL_IE, &i2c_base->ie); 137 udelay (1000); 138 flush_fifo(); 139 writew (0xFFFF, &i2c_base->stat); 140 writew (0, &i2c_base->cnt); 141 142 bus_initialized[current_bus] = 1; 143 } 144 145 static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value) 146 { 147 int i2c_error = 0; 148 u16 status; 149 150 /* wait until bus not busy */ 151 wait_for_bb (); 152 153 /* one byte only */ 154 writew (1, &i2c_base->cnt); 155 /* set slave address */ 156 writew (devaddr, &i2c_base->sa); 157 /* no stop bit needed here */ 158 writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX, &i2c_base->con); 159 160 status = wait_for_pin (); 161 162 if (status & I2C_STAT_XRDY) { 163 /* Important: have to use byte access */ 164 writeb (regoffset, &i2c_base->data); 165 udelay (20000); 166 if (readw (&i2c_base->stat) & I2C_STAT_NACK) { 167 i2c_error = 1; 168 } 169 } else { 170 i2c_error = 1; 171 } 172 173 if (!i2c_error) { 174 writew (I2C_CON_EN, &i2c_base->con); 175 while (readw(&i2c_base->stat) & 176 (I2C_STAT_XRDY | I2C_STAT_ARDY)) { 177 udelay (10000); 178 /* Have to clear pending interrupt to clear I2C_STAT */ 179 writew (0xFFFF, &i2c_base->stat); 180 } 181 182 /* set slave address */ 183 writew (devaddr, &i2c_base->sa); 184 /* read one byte from slave */ 185 writew (1, &i2c_base->cnt); 186 /* need stop bit here */ 187 writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, 188 &i2c_base->con); 189 190 status = wait_for_pin (); 191 if (status & I2C_STAT_RRDY) { 192 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \ 193 defined(CONFIG_OMAP44XX) 194 *value = readb (&i2c_base->data); 195 #else 196 *value = readw (&i2c_base->data); 197 #endif 198 udelay (20000); 199 } else { 200 i2c_error = 1; 201 } 202 203 if (!i2c_error) { 204 writew (I2C_CON_EN, &i2c_base->con); 205 while (readw (&i2c_base->stat) & 206 (I2C_STAT_RRDY | I2C_STAT_ARDY)) { 207 udelay (10000); 208 writew (0xFFFF, &i2c_base->stat); 209 } 210 } 211 } 212 flush_fifo(); 213 writew (0xFFFF, &i2c_base->stat); 214 writew (0, &i2c_base->cnt); 215 return i2c_error; 216 } 217 218 static int i2c_write_byte (u8 devaddr, u8 regoffset, u8 value) 219 { 220 int i2c_error = 0; 221 u16 status, stat; 222 223 /* wait until bus not busy */ 224 wait_for_bb (); 225 226 /* two bytes */ 227 writew (2, &i2c_base->cnt); 228 /* set slave address */ 229 writew (devaddr, &i2c_base->sa); 230 /* stop bit needed here */ 231 writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | 232 I2C_CON_STP, &i2c_base->con); 233 234 /* wait until state change */ 235 status = wait_for_pin (); 236 237 if (status & I2C_STAT_XRDY) { 238 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \ 239 defined(CONFIG_OMAP44XX) 240 /* send out 1 byte */ 241 writeb (regoffset, &i2c_base->data); 242 writew (I2C_STAT_XRDY, &i2c_base->stat); 243 244 status = wait_for_pin (); 245 if ((status & I2C_STAT_XRDY)) { 246 /* send out next 1 byte */ 247 writeb (value, &i2c_base->data); 248 writew (I2C_STAT_XRDY, &i2c_base->stat); 249 } else { 250 i2c_error = 1; 251 } 252 #else 253 /* send out two bytes */ 254 writew ((value << 8) + regoffset, &i2c_base->data); 255 #endif 256 /* must have enough delay to allow BB bit to go low */ 257 udelay (50000); 258 if (readw (&i2c_base->stat) & I2C_STAT_NACK) { 259 i2c_error = 1; 260 } 261 } else { 262 i2c_error = 1; 263 } 264 265 if (!i2c_error) { 266 int eout = 200; 267 268 writew (I2C_CON_EN, &i2c_base->con); 269 while ((stat = readw (&i2c_base->stat)) || (readw (&i2c_base->con) & I2C_CON_MST)) { 270 udelay (1000); 271 /* have to read to clear intrrupt */ 272 writew (0xFFFF, &i2c_base->stat); 273 if(--eout == 0) /* better leave with error than hang */ 274 break; 275 } 276 } 277 flush_fifo(); 278 writew (0xFFFF, &i2c_base->stat); 279 writew (0, &i2c_base->cnt); 280 return i2c_error; 281 } 282 283 static void flush_fifo(void) 284 { u16 stat; 285 286 /* note: if you try and read data when its not there or ready 287 * you get a bus error 288 */ 289 while(1){ 290 stat = readw(&i2c_base->stat); 291 if(stat == I2C_STAT_RRDY){ 292 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \ 293 defined(CONFIG_OMAP44XX) 294 readb(&i2c_base->data); 295 #else 296 readw(&i2c_base->data); 297 #endif 298 writew(I2C_STAT_RRDY,&i2c_base->stat); 299 udelay(1000); 300 }else 301 break; 302 } 303 } 304 305 int i2c_probe (uchar chip) 306 { 307 int res = 1; /* default = fail */ 308 309 if (chip == readw (&i2c_base->oa)) { 310 return res; 311 } 312 313 /* wait until bus not busy */ 314 wait_for_bb (); 315 316 /* try to read one byte */ 317 writew (1, &i2c_base->cnt); 318 /* set slave address */ 319 writew (chip, &i2c_base->sa); 320 /* stop bit needed here */ 321 writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, &i2c_base->con); 322 /* enough delay for the NACK bit set */ 323 udelay (50000); 324 325 if (!(readw (&i2c_base->stat) & I2C_STAT_NACK)) { 326 res = 0; /* success case */ 327 flush_fifo(); 328 writew(0xFFFF, &i2c_base->stat); 329 } else { 330 writew(0xFFFF, &i2c_base->stat); /* failue, clear sources*/ 331 writew (readw (&i2c_base->con) | I2C_CON_STP, &i2c_base->con); /* finish up xfer */ 332 udelay(20000); 333 wait_for_bb (); 334 } 335 flush_fifo(); 336 writew (0, &i2c_base->cnt); /* don't allow any more data in...we don't want it.*/ 337 writew(0xFFFF, &i2c_base->stat); 338 return res; 339 } 340 341 int i2c_read (uchar chip, uint addr, int alen, uchar * buffer, int len) 342 { 343 int i; 344 345 if (alen > 1) { 346 printf ("I2C read: addr len %d not supported\n", alen); 347 return 1; 348 } 349 350 if (addr + len > 256) { 351 printf ("I2C read: address out of range\n"); 352 return 1; 353 } 354 355 for (i = 0; i < len; i++) { 356 if (i2c_read_byte (chip, addr + i, &buffer[i])) { 357 printf ("I2C read: I/O error\n"); 358 i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 359 return 1; 360 } 361 } 362 363 return 0; 364 } 365 366 int i2c_write (uchar chip, uint addr, int alen, uchar * buffer, int len) 367 { 368 int i; 369 370 if (alen > 1) { 371 printf ("I2C read: addr len %d not supported\n", alen); 372 return 1; 373 } 374 375 if (addr + len > 256) { 376 printf ("I2C read: address out of range\n"); 377 return 1; 378 } 379 380 for (i = 0; i < len; i++) { 381 if (i2c_write_byte (chip, addr + i, buffer[i])) { 382 printf ("I2C read: I/O error\n"); 383 i2c_init (CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 384 return 1; 385 } 386 } 387 388 return 0; 389 } 390 391 static void wait_for_bb (void) 392 { 393 int timeout = 10; 394 u16 stat; 395 396 writew(0xFFFF, &i2c_base->stat); /* clear current interruts...*/ 397 while ((stat = readw (&i2c_base->stat) & I2C_STAT_BB) && timeout--) { 398 writew (stat, &i2c_base->stat); 399 udelay (50000); 400 } 401 402 if (timeout <= 0) { 403 printf ("timed out in wait_for_bb: I2C_STAT=%x\n", 404 readw (&i2c_base->stat)); 405 } 406 writew(0xFFFF, &i2c_base->stat); /* clear delayed stuff*/ 407 } 408 409 static u16 wait_for_pin (void) 410 { 411 u16 status; 412 int timeout = 10; 413 414 do { 415 udelay (1000); 416 status = readw (&i2c_base->stat); 417 } while ( !(status & 418 (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY | 419 I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK | 420 I2C_STAT_AL)) && timeout--); 421 422 if (timeout <= 0) { 423 printf ("timed out in wait_for_pin: I2C_STAT=%x\n", 424 readw (&i2c_base->stat)); 425 writew(0xFFFF, &i2c_base->stat); 426 } 427 return status; 428 } 429 430 int i2c_set_bus_num(unsigned int bus) 431 { 432 if ((bus < 0) || (bus >= I2C_BUS_MAX)) { 433 printf("Bad bus: %d\n", bus); 434 return -1; 435 } 436 437 #if I2C_BUS_MAX==3 438 if (bus == 2) 439 i2c_base = (struct i2c *)I2C_BASE3; 440 else 441 #endif 442 if (bus == 1) 443 i2c_base = (struct i2c *)I2C_BASE2; 444 else 445 i2c_base = (struct i2c *)I2C_BASE1; 446 447 current_bus = bus; 448 449 if(!bus_initialized[current_bus]) 450 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 451 452 return 0; 453 } 454 455 int i2c_get_bus_num(void) 456 { 457 return (int) current_bus; 458 } 459 460