1 /* 2 * Basic I2C functions 3 * 4 * Copyright (c) 2004 Texas Instruments 5 * 6 * This package is free software; you can redistribute it and/or 7 * modify it under the terms of the license found in the file 8 * named COPYING that should have accompanied this file. 9 * 10 * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR 11 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED 12 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. 13 * 14 * Author: Jian Zhang jzhang@ti.com, Texas Instruments 15 * 16 * Copyright (c) 2003 Wolfgang Denk, wd@denx.de 17 * Rewritten to fit into the current U-Boot framework 18 * 19 * Adapted for OMAP2420 I2C, r-woodruff2@ti.com 20 * 21 * Copyright (c) 2013 Lubomir Popov <lpopov@mm-sol.com>, MM Solutions 22 * New i2c_read, i2c_write and i2c_probe functions, tested on OMAP4 23 * (4430/60/70), OMAP5 (5430) and AM335X (3359); should work on older 24 * OMAPs and derivatives as well. The only anticipated exception would 25 * be the OMAP2420, which shall require driver modification. 26 * - Rewritten i2c_read to operate correctly with all types of chips 27 * (old function could not read consistent data from some I2C slaves). 28 * - Optimized i2c_write. 29 * - New i2c_probe, performs write access vs read. The old probe could 30 * hang the system under certain conditions (e.g. unconfigured pads). 31 * - The read/write/probe functions try to identify unconfigured bus. 32 * - Status functions now read irqstatus_raw as per TRM guidelines 33 * (except for OMAP243X and OMAP34XX). 34 * - Driver now supports up to I2C5 (OMAP5). 35 * 36 * Copyright (c) 2014 Hannes Schmelzer <oe5hpm@oevsv.at>, B&R 37 * - Added support for set_speed 38 * 39 */ 40 41 #include <common.h> 42 #include <dm.h> 43 #include <i2c.h> 44 45 #include <asm/io.h> 46 #include <asm/omap_i2c.h> 47 48 /* 49 * Provide access to architecture-specific I2C header files for platforms 50 * that are NOT yet solely relying on CONFIG_DM_I2C, CONFIG_OF_CONTROL, and 51 * the defaults provided in 'omap24xx_i2c.h' for all U-Boot stages where I2C 52 * access is desired. 53 */ 54 #ifndef CONFIG_ARCH_K3 55 #include <asm/arch/i2c.h> 56 #endif 57 58 #include "omap24xx_i2c.h" 59 60 #define I2C_TIMEOUT 1000 61 62 /* Absolutely safe for status update at 100 kHz I2C: */ 63 #define I2C_WAIT 200 64 65 enum { 66 OMAP_I2C_REV_REG = 0, /* Only on IP V1 (OMAP34XX) */ 67 OMAP_I2C_IE_REG, /* Only on IP V1 (OMAP34XX) */ 68 OMAP_I2C_STAT_REG, 69 OMAP_I2C_WE_REG, 70 OMAP_I2C_SYSS_REG, 71 OMAP_I2C_BUF_REG, 72 OMAP_I2C_CNT_REG, 73 OMAP_I2C_DATA_REG, 74 OMAP_I2C_SYSC_REG, 75 OMAP_I2C_CON_REG, 76 OMAP_I2C_OA_REG, 77 OMAP_I2C_SA_REG, 78 OMAP_I2C_PSC_REG, 79 OMAP_I2C_SCLL_REG, 80 OMAP_I2C_SCLH_REG, 81 OMAP_I2C_SYSTEST_REG, 82 OMAP_I2C_BUFSTAT_REG, 83 /* Only on IP V2 (OMAP4430, etc.) */ 84 OMAP_I2C_IP_V2_REVNB_LO, 85 OMAP_I2C_IP_V2_REVNB_HI, 86 OMAP_I2C_IP_V2_IRQSTATUS_RAW, 87 OMAP_I2C_IP_V2_IRQENABLE_SET, 88 OMAP_I2C_IP_V2_IRQENABLE_CLR, 89 }; 90 91 static const u8 __maybe_unused reg_map_ip_v1[] = { 92 [OMAP_I2C_REV_REG] = 0x00, 93 [OMAP_I2C_IE_REG] = 0x04, 94 [OMAP_I2C_STAT_REG] = 0x08, 95 [OMAP_I2C_WE_REG] = 0x0c, 96 [OMAP_I2C_SYSS_REG] = 0x10, 97 [OMAP_I2C_BUF_REG] = 0x14, 98 [OMAP_I2C_CNT_REG] = 0x18, 99 [OMAP_I2C_DATA_REG] = 0x1c, 100 [OMAP_I2C_SYSC_REG] = 0x20, 101 [OMAP_I2C_CON_REG] = 0x24, 102 [OMAP_I2C_OA_REG] = 0x28, 103 [OMAP_I2C_SA_REG] = 0x2c, 104 [OMAP_I2C_PSC_REG] = 0x30, 105 [OMAP_I2C_SCLL_REG] = 0x34, 106 [OMAP_I2C_SCLH_REG] = 0x38, 107 [OMAP_I2C_SYSTEST_REG] = 0x3c, 108 [OMAP_I2C_BUFSTAT_REG] = 0x40, 109 }; 110 111 static const u8 __maybe_unused reg_map_ip_v2[] = { 112 [OMAP_I2C_STAT_REG] = 0x28, 113 [OMAP_I2C_WE_REG] = 0x34, 114 [OMAP_I2C_SYSS_REG] = 0x90, 115 [OMAP_I2C_BUF_REG] = 0x94, 116 [OMAP_I2C_CNT_REG] = 0x98, 117 [OMAP_I2C_DATA_REG] = 0x9c, 118 [OMAP_I2C_SYSC_REG] = 0x10, 119 [OMAP_I2C_CON_REG] = 0xa4, 120 [OMAP_I2C_OA_REG] = 0xa8, 121 [OMAP_I2C_SA_REG] = 0xac, 122 [OMAP_I2C_PSC_REG] = 0xb0, 123 [OMAP_I2C_SCLL_REG] = 0xb4, 124 [OMAP_I2C_SCLH_REG] = 0xb8, 125 [OMAP_I2C_SYSTEST_REG] = 0xbc, 126 [OMAP_I2C_BUFSTAT_REG] = 0xc0, 127 [OMAP_I2C_IP_V2_REVNB_LO] = 0x00, 128 [OMAP_I2C_IP_V2_REVNB_HI] = 0x04, 129 [OMAP_I2C_IP_V2_IRQSTATUS_RAW] = 0x24, 130 [OMAP_I2C_IP_V2_IRQENABLE_SET] = 0x2c, 131 [OMAP_I2C_IP_V2_IRQENABLE_CLR] = 0x30, 132 }; 133 134 struct omap_i2c { 135 struct udevice *clk; 136 int ip_rev; 137 struct i2c *regs; 138 unsigned int speed; 139 int waitdelay; 140 int clk_id; 141 }; 142 143 static inline const u8 *omap_i2c_get_ip_reg_map(int ip_rev) 144 { 145 switch (ip_rev) { 146 case OMAP_I2C_REV_V1: 147 return reg_map_ip_v1; 148 case OMAP_I2C_REV_V2: 149 /* Fall through... */ 150 default: 151 return reg_map_ip_v2; 152 } 153 } 154 155 static inline void omap_i2c_write_reg(void __iomem *base, int ip_rev, 156 u16 val, int reg) 157 { 158 writew(val, base + omap_i2c_get_ip_reg_map(ip_rev)[reg]); 159 } 160 161 static inline u16 omap_i2c_read_reg(void __iomem *base, int ip_rev, int reg) 162 { 163 return readw(base + omap_i2c_get_ip_reg_map(ip_rev)[reg]); 164 } 165 166 static int omap24_i2c_findpsc(u32 *pscl, u32 *psch, uint speed) 167 { 168 unsigned long internal_clk = 0, fclk; 169 unsigned int prescaler; 170 171 /* 172 * This method is only called for Standard and Fast Mode speeds 173 * 174 * For some TI SoCs it is explicitly written in TRM (e,g, SPRUHZ6G, 175 * page 5685, Table 24-7) 176 * that the internal I2C clock (after prescaler) should be between 177 * 7-12 MHz (at least for Fast Mode (FS)). 178 * 179 * Such approach is used in v4.9 Linux kernel in: 180 * ./drivers/i2c/busses/i2c-omap.c (omap_i2c_init function). 181 */ 182 183 speed /= 1000; /* convert speed to kHz */ 184 185 if (speed > 100) 186 internal_clk = 9600; 187 else 188 internal_clk = 4000; 189 190 fclk = I2C_IP_CLK / 1000; 191 prescaler = fclk / internal_clk; 192 prescaler = prescaler - 1; 193 194 if (speed > 100) { 195 unsigned long scl; 196 197 /* Fast mode */ 198 scl = internal_clk / speed; 199 *pscl = scl - (scl / 3) - I2C_FASTSPEED_SCLL_TRIM; 200 *psch = (scl / 3) - I2C_FASTSPEED_SCLH_TRIM; 201 } else { 202 /* Standard mode */ 203 *pscl = internal_clk / (speed * 2) - I2C_FASTSPEED_SCLL_TRIM; 204 *psch = internal_clk / (speed * 2) - I2C_FASTSPEED_SCLH_TRIM; 205 } 206 207 debug("%s: speed [kHz]: %d psc: 0x%x sscl: 0x%x ssch: 0x%x\n", 208 __func__, speed, prescaler, *pscl, *psch); 209 210 if (*pscl <= 0 || *psch <= 0 || prescaler <= 0) 211 return -EINVAL; 212 213 return prescaler; 214 } 215 216 /* 217 * Wait for the bus to be free by checking the Bus Busy (BB) 218 * bit to become clear 219 */ 220 static int wait_for_bb(void __iomem *i2c_base, int ip_rev, int waitdelay) 221 { 222 int timeout = I2C_TIMEOUT; 223 int irq_stat_reg; 224 u16 stat; 225 226 irq_stat_reg = (ip_rev == OMAP_I2C_REV_V1) ? 227 OMAP_I2C_STAT_REG : OMAP_I2C_IP_V2_IRQSTATUS_RAW; 228 229 /* clear current interrupts */ 230 omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG); 231 232 while ((stat = omap_i2c_read_reg(i2c_base, ip_rev, irq_stat_reg) & 233 I2C_STAT_BB) && timeout--) { 234 omap_i2c_write_reg(i2c_base, ip_rev, stat, OMAP_I2C_STAT_REG); 235 udelay(waitdelay); 236 } 237 238 if (timeout <= 0) { 239 printf("Timed out in %s: status=%04x\n", __func__, stat); 240 return 1; 241 } 242 243 /* clear delayed stuff */ 244 omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG); 245 return 0; 246 } 247 248 /* 249 * Wait for the I2C controller to complete current action 250 * and update status 251 */ 252 static u16 wait_for_event(void __iomem *i2c_base, int ip_rev, int waitdelay) 253 { 254 u16 status; 255 int timeout = I2C_TIMEOUT; 256 int irq_stat_reg; 257 258 irq_stat_reg = (ip_rev == OMAP_I2C_REV_V1) ? 259 OMAP_I2C_STAT_REG : OMAP_I2C_IP_V2_IRQSTATUS_RAW; 260 do { 261 udelay(waitdelay); 262 status = omap_i2c_read_reg(i2c_base, ip_rev, irq_stat_reg); 263 } while (!(status & 264 (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY | 265 I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK | 266 I2C_STAT_AL)) && timeout--); 267 268 if (timeout <= 0) { 269 printf("Timed out in %s: status=%04x\n", __func__, status); 270 /* 271 * If status is still 0 here, probably the bus pads have 272 * not been configured for I2C, and/or pull-ups are missing. 273 */ 274 printf("Check if pads/pull-ups of bus are properly configured\n"); 275 omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG); 276 status = 0; 277 } 278 279 return status; 280 } 281 282 static void flush_fifo(void __iomem *i2c_base, int ip_rev) 283 { 284 u16 stat; 285 286 /* 287 * note: if you try and read data when its not there or ready 288 * you get a bus error 289 */ 290 while (1) { 291 stat = omap_i2c_read_reg(i2c_base, ip_rev, OMAP_I2C_STAT_REG); 292 if (stat == I2C_STAT_RRDY) { 293 omap_i2c_read_reg(i2c_base, ip_rev, OMAP_I2C_DATA_REG); 294 omap_i2c_write_reg(i2c_base, ip_rev, 295 I2C_STAT_RRDY, OMAP_I2C_STAT_REG); 296 udelay(1000); 297 } else 298 break; 299 } 300 } 301 302 static int __omap24_i2c_setspeed(void __iomem *i2c_base, int ip_rev, uint speed, 303 int *waitdelay) 304 { 305 int psc, fsscll = 0, fssclh = 0; 306 int hsscll = 0, hssclh = 0; 307 u32 scll = 0, sclh = 0; 308 309 if (speed >= OMAP_I2C_HIGH_SPEED) { 310 /* High speed */ 311 psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK; 312 psc -= 1; 313 if (psc < I2C_PSC_MIN) { 314 printf("Error : I2C unsupported prescaler %d\n", psc); 315 return -1; 316 } 317 318 /* For first phase of HS mode */ 319 fsscll = I2C_INTERNAL_SAMPLING_CLK / (2 * speed); 320 321 fssclh = fsscll; 322 323 fsscll -= I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM; 324 fssclh -= I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM; 325 if (((fsscll < 0) || (fssclh < 0)) || 326 ((fsscll > 255) || (fssclh > 255))) { 327 puts("Error : I2C initializing first phase clock\n"); 328 return -1; 329 } 330 331 /* For second phase of HS mode */ 332 hsscll = hssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed); 333 334 hsscll -= I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM; 335 hssclh -= I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM; 336 if (((fsscll < 0) || (fssclh < 0)) || 337 ((fsscll > 255) || (fssclh > 255))) { 338 puts("Error : I2C initializing second phase clock\n"); 339 return -1; 340 } 341 342 scll = (unsigned int)hsscll << 8 | (unsigned int)fsscll; 343 sclh = (unsigned int)hssclh << 8 | (unsigned int)fssclh; 344 345 } else { 346 /* Standard and fast speed */ 347 psc = omap24_i2c_findpsc(&scll, &sclh, speed); 348 if (0 > psc) { 349 puts("Error : I2C initializing clock\n"); 350 return -1; 351 } 352 } 353 354 /* wait for 20 clkperiods */ 355 *waitdelay = (10000000 / speed) * 2; 356 357 omap_i2c_write_reg(i2c_base, ip_rev, 0, OMAP_I2C_CON_REG); 358 omap_i2c_write_reg(i2c_base, ip_rev, psc, OMAP_I2C_PSC_REG); 359 omap_i2c_write_reg(i2c_base, ip_rev, scll, OMAP_I2C_SCLL_REG); 360 omap_i2c_write_reg(i2c_base, ip_rev, sclh, OMAP_I2C_SCLH_REG); 361 omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_EN, OMAP_I2C_CON_REG); 362 363 /* clear all pending status */ 364 omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG); 365 366 return 0; 367 } 368 369 static void omap24_i2c_deblock(void __iomem *i2c_base, int ip_rev) 370 { 371 int i; 372 u16 systest; 373 u16 orgsystest; 374 375 /* set test mode ST_EN = 1 */ 376 orgsystest = omap_i2c_read_reg(i2c_base, ip_rev, OMAP_I2C_SYSTEST_REG); 377 systest = orgsystest; 378 379 /* enable testmode */ 380 systest |= I2C_SYSTEST_ST_EN; 381 omap_i2c_write_reg(i2c_base, ip_rev, systest, OMAP_I2C_SYSTEST_REG); 382 systest &= ~I2C_SYSTEST_TMODE_MASK; 383 systest |= 3 << I2C_SYSTEST_TMODE_SHIFT; 384 omap_i2c_write_reg(i2c_base, ip_rev, systest, OMAP_I2C_SYSTEST_REG); 385 386 /* set SCL, SDA = 1 */ 387 systest |= I2C_SYSTEST_SCL_O | I2C_SYSTEST_SDA_O; 388 omap_i2c_write_reg(i2c_base, ip_rev, systest, OMAP_I2C_SYSTEST_REG); 389 udelay(10); 390 391 /* toggle scl 9 clocks */ 392 for (i = 0; i < 9; i++) { 393 /* SCL = 0 */ 394 systest &= ~I2C_SYSTEST_SCL_O; 395 omap_i2c_write_reg(i2c_base, ip_rev, 396 systest, OMAP_I2C_SYSTEST_REG); 397 udelay(10); 398 /* SCL = 1 */ 399 systest |= I2C_SYSTEST_SCL_O; 400 omap_i2c_write_reg(i2c_base, ip_rev, 401 systest, OMAP_I2C_SYSTEST_REG); 402 udelay(10); 403 } 404 405 /* send stop */ 406 systest &= ~I2C_SYSTEST_SDA_O; 407 omap_i2c_write_reg(i2c_base, ip_rev, systest, OMAP_I2C_SYSTEST_REG); 408 udelay(10); 409 systest |= I2C_SYSTEST_SCL_O | I2C_SYSTEST_SDA_O; 410 omap_i2c_write_reg(i2c_base, ip_rev, systest, OMAP_I2C_SYSTEST_REG); 411 udelay(10); 412 413 /* restore original mode */ 414 omap_i2c_write_reg(i2c_base, ip_rev, orgsystest, OMAP_I2C_SYSTEST_REG); 415 } 416 417 static void __omap24_i2c_init(void __iomem *i2c_base, int ip_rev, int speed, 418 int slaveadd, int *waitdelay) 419 { 420 int timeout = I2C_TIMEOUT; 421 int deblock = 1; 422 423 retry: 424 if (omap_i2c_read_reg(i2c_base, ip_rev, OMAP_I2C_CON_REG) & 425 I2C_CON_EN) { 426 omap_i2c_write_reg(i2c_base, ip_rev, 0, OMAP_I2C_CON_REG); 427 udelay(50000); 428 } 429 430 /* for ES2 after soft reset */ 431 omap_i2c_write_reg(i2c_base, ip_rev, 0x2, OMAP_I2C_SYSC_REG); 432 udelay(1000); 433 434 omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_EN, OMAP_I2C_CON_REG); 435 while (!(omap_i2c_read_reg(i2c_base, ip_rev, OMAP_I2C_SYSS_REG) & 436 I2C_SYSS_RDONE) && timeout--) { 437 if (timeout <= 0) { 438 puts("ERROR: Timeout in soft-reset\n"); 439 return; 440 } 441 udelay(1000); 442 } 443 444 if (__omap24_i2c_setspeed(i2c_base, ip_rev, speed, waitdelay)) { 445 printf("ERROR: failed to setup I2C bus-speed!\n"); 446 return; 447 } 448 449 /* own address */ 450 omap_i2c_write_reg(i2c_base, ip_rev, slaveadd, OMAP_I2C_OA_REG); 451 452 if (ip_rev == OMAP_I2C_REV_V1) { 453 /* 454 * Have to enable interrupts for OMAP2/3, these IPs don't have 455 * an 'irqstatus_raw' register and we shall have to poll 'stat' 456 */ 457 omap_i2c_write_reg(i2c_base, ip_rev, I2C_IE_XRDY_IE | 458 I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | 459 I2C_IE_NACK_IE | I2C_IE_AL_IE, 460 OMAP_I2C_IE_REG); 461 } 462 463 udelay(1000); 464 flush_fifo(i2c_base, ip_rev); 465 omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG); 466 467 /* Handle possible failed I2C state */ 468 if (wait_for_bb(i2c_base, ip_rev, *waitdelay)) 469 if (deblock == 1) { 470 omap24_i2c_deblock(i2c_base, ip_rev); 471 deblock = 0; 472 goto retry; 473 } 474 } 475 476 /* 477 * i2c_probe: Use write access. Allows to identify addresses that are 478 * write-only (like the config register of dual-port EEPROMs) 479 */ 480 static int __omap24_i2c_probe(void __iomem *i2c_base, int ip_rev, int waitdelay, 481 uchar chip) 482 { 483 u16 status; 484 int res = 1; /* default = fail */ 485 486 if (chip == omap_i2c_read_reg(i2c_base, ip_rev, OMAP_I2C_OA_REG)) 487 return res; 488 489 /* Wait until bus is free */ 490 if (wait_for_bb(i2c_base, ip_rev, waitdelay)) 491 return res; 492 493 /* No data transfer, slave addr only */ 494 omap_i2c_write_reg(i2c_base, ip_rev, chip, OMAP_I2C_SA_REG); 495 496 /* Stop bit needed here */ 497 omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_EN | I2C_CON_MST | 498 I2C_CON_STT | I2C_CON_TRX | I2C_CON_STP, 499 OMAP_I2C_CON_REG); 500 501 status = wait_for_event(i2c_base, ip_rev, waitdelay); 502 503 if ((status & ~I2C_STAT_XRDY) == 0 || (status & I2C_STAT_AL)) { 504 /* 505 * With current high-level command implementation, notifying 506 * the user shall flood the console with 127 messages. If 507 * silent exit is desired upon unconfigured bus, remove the 508 * following 'if' section: 509 */ 510 if (status == I2C_STAT_XRDY) 511 printf("i2c_probe: pads on bus probably not configured (status=0x%x)\n", 512 status); 513 514 goto pr_exit; 515 } 516 517 /* Check for ACK (!NAK) */ 518 if (!(status & I2C_STAT_NACK)) { 519 res = 0; /* Device found */ 520 udelay(waitdelay);/* Required by AM335X in SPL */ 521 /* Abort transfer (force idle state) */ 522 omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_MST | I2C_CON_TRX, 523 OMAP_I2C_CON_REG); /* Reset */ 524 udelay(1000); 525 omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_EN | I2C_CON_MST | 526 I2C_CON_TRX | I2C_CON_STP, 527 OMAP_I2C_CON_REG); /* STP */ 528 } 529 530 pr_exit: 531 flush_fifo(i2c_base, ip_rev); 532 omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG); 533 return res; 534 } 535 536 /* 537 * i2c_read: Function now uses a single I2C read transaction with bulk transfer 538 * of the requested number of bytes (note that the 'i2c md' command 539 * limits this to 16 bytes anyway). If CONFIG_I2C_REPEATED_START is 540 * defined in the board config header, this transaction shall be with 541 * Repeated Start (Sr) between the address and data phases; otherwise 542 * Stop-Start (P-S) shall be used (some I2C chips do require a P-S). 543 * The address (reg offset) may be 0, 1 or 2 bytes long. 544 * Function now reads correctly from chips that return more than one 545 * byte of data per addressed register (like TI temperature sensors), 546 * or that do not need a register address at all (such as some clock 547 * distributors). 548 */ 549 static int __omap24_i2c_read(void __iomem *i2c_base, int ip_rev, int waitdelay, 550 uchar chip, uint addr, int alen, uchar *buffer, 551 int len) 552 { 553 int i2c_error = 0; 554 u16 status; 555 556 if (alen < 0) { 557 puts("I2C read: addr len < 0\n"); 558 return 1; 559 } 560 561 if (len < 0) { 562 puts("I2C read: data len < 0\n"); 563 return 1; 564 } 565 566 if (buffer == NULL) { 567 puts("I2C read: NULL pointer passed\n"); 568 return 1; 569 } 570 571 if (alen > 2) { 572 printf("I2C read: addr len %d not supported\n", alen); 573 return 1; 574 } 575 576 if (addr + len > (1 << 16)) { 577 puts("I2C read: address out of range\n"); 578 return 1; 579 } 580 581 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 582 /* 583 * EEPROM chips that implement "address overflow" are ones 584 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of 585 * address and the extra bits end up in the "chip address" 586 * bit slots. This makes a 24WC08 (1Kbyte) chip look like 587 * four 256 byte chips. 588 * 589 * Note that we consider the length of the address field to 590 * still be one byte because the extra address bits are 591 * hidden in the chip address. 592 */ 593 if (alen > 0) 594 chip |= ((addr >> (alen * 8)) & 595 CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); 596 #endif 597 598 /* Wait until bus not busy */ 599 if (wait_for_bb(i2c_base, ip_rev, waitdelay)) 600 return 1; 601 602 /* Zero, one or two bytes reg address (offset) */ 603 omap_i2c_write_reg(i2c_base, ip_rev, alen, OMAP_I2C_CNT_REG); 604 /* Set slave address */ 605 omap_i2c_write_reg(i2c_base, ip_rev, chip, OMAP_I2C_SA_REG); 606 607 if (alen) { 608 /* Must write reg offset first */ 609 #ifdef CONFIG_I2C_REPEATED_START 610 /* No stop bit, use Repeated Start (Sr) */ 611 omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_EN | I2C_CON_MST | 612 I2C_CON_STT | I2C_CON_TRX, OMAP_I2C_CON_REG); 613 #else 614 /* Stop - Start (P-S) */ 615 omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_EN | I2C_CON_MST | 616 I2C_CON_STT | I2C_CON_STP | I2C_CON_TRX, 617 OMAP_I2C_CON_REG); 618 #endif 619 /* Send register offset */ 620 while (1) { 621 status = wait_for_event(i2c_base, ip_rev, waitdelay); 622 /* Try to identify bus that is not padconf'd for I2C */ 623 if (status == I2C_STAT_XRDY) { 624 i2c_error = 2; 625 printf("i2c_read (addr phase): pads on bus probably not configured (status=0x%x)\n", 626 status); 627 goto rd_exit; 628 } 629 if (status == 0 || (status & I2C_STAT_NACK)) { 630 i2c_error = 1; 631 printf("i2c_read: error waiting for addr ACK (status=0x%x)\n", 632 status); 633 goto rd_exit; 634 } 635 if (alen) { 636 if (status & I2C_STAT_XRDY) { 637 u8 addr_byte; 638 alen--; 639 addr_byte = (addr >> (8 * alen)) & 0xff; 640 omap_i2c_write_reg(i2c_base, ip_rev, 641 addr_byte, 642 OMAP_I2C_DATA_REG); 643 omap_i2c_write_reg(i2c_base, ip_rev, 644 I2C_STAT_XRDY, 645 OMAP_I2C_STAT_REG); 646 } 647 } 648 if (status & I2C_STAT_ARDY) { 649 omap_i2c_write_reg(i2c_base, ip_rev, 650 I2C_STAT_ARDY, 651 OMAP_I2C_STAT_REG); 652 break; 653 } 654 } 655 } 656 657 /* Set slave address */ 658 omap_i2c_write_reg(i2c_base, ip_rev, chip, OMAP_I2C_SA_REG); 659 /* Read len bytes from slave */ 660 omap_i2c_write_reg(i2c_base, ip_rev, len, OMAP_I2C_CNT_REG); 661 /* Need stop bit here */ 662 omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_EN | I2C_CON_MST | 663 I2C_CON_STT | I2C_CON_STP, OMAP_I2C_CON_REG); 664 665 /* Receive data */ 666 while (1) { 667 status = wait_for_event(i2c_base, ip_rev, waitdelay); 668 /* 669 * Try to identify bus that is not padconf'd for I2C. This 670 * state could be left over from previous transactions if 671 * the address phase is skipped due to alen=0. 672 */ 673 if (status == I2C_STAT_XRDY) { 674 i2c_error = 2; 675 printf("i2c_read (data phase): pads on bus probably not configured (status=0x%x)\n", 676 status); 677 goto rd_exit; 678 } 679 if (status == 0 || (status & I2C_STAT_NACK)) { 680 i2c_error = 1; 681 goto rd_exit; 682 } 683 if (status & I2C_STAT_RRDY) { 684 *buffer++ = omap_i2c_read_reg(i2c_base, ip_rev, 685 OMAP_I2C_DATA_REG); 686 omap_i2c_write_reg(i2c_base, ip_rev, 687 I2C_STAT_RRDY, OMAP_I2C_STAT_REG); 688 } 689 if (status & I2C_STAT_ARDY) { 690 omap_i2c_write_reg(i2c_base, ip_rev, 691 I2C_STAT_ARDY, OMAP_I2C_STAT_REG); 692 break; 693 } 694 } 695 696 rd_exit: 697 flush_fifo(i2c_base, ip_rev); 698 omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG); 699 return i2c_error; 700 } 701 702 /* i2c_write: Address (reg offset) may be 0, 1 or 2 bytes long. */ 703 static int __omap24_i2c_write(void __iomem *i2c_base, int ip_rev, int waitdelay, 704 uchar chip, uint addr, int alen, uchar *buffer, 705 int len) 706 { 707 int i; 708 u16 status; 709 int i2c_error = 0; 710 int timeout = I2C_TIMEOUT; 711 712 if (alen < 0) { 713 puts("I2C write: addr len < 0\n"); 714 return 1; 715 } 716 717 if (len < 0) { 718 puts("I2C write: data len < 0\n"); 719 return 1; 720 } 721 722 if (buffer == NULL) { 723 puts("I2C write: NULL pointer passed\n"); 724 return 1; 725 } 726 727 if (alen > 2) { 728 printf("I2C write: addr len %d not supported\n", alen); 729 return 1; 730 } 731 732 if (addr + len > (1 << 16)) { 733 printf("I2C write: address 0x%x + 0x%x out of range\n", 734 addr, len); 735 return 1; 736 } 737 738 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 739 /* 740 * EEPROM chips that implement "address overflow" are ones 741 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of 742 * address and the extra bits end up in the "chip address" 743 * bit slots. This makes a 24WC08 (1Kbyte) chip look like 744 * four 256 byte chips. 745 * 746 * Note that we consider the length of the address field to 747 * still be one byte because the extra address bits are 748 * hidden in the chip address. 749 */ 750 if (alen > 0) 751 chip |= ((addr >> (alen * 8)) & 752 CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); 753 #endif 754 755 /* Wait until bus not busy */ 756 if (wait_for_bb(i2c_base, ip_rev, waitdelay)) 757 return 1; 758 759 /* Start address phase - will write regoffset + len bytes data */ 760 omap_i2c_write_reg(i2c_base, ip_rev, alen + len, OMAP_I2C_CNT_REG); 761 /* Set slave address */ 762 omap_i2c_write_reg(i2c_base, ip_rev, chip, OMAP_I2C_SA_REG); 763 /* Stop bit needed here */ 764 omap_i2c_write_reg(i2c_base, ip_rev, I2C_CON_EN | I2C_CON_MST | 765 I2C_CON_STT | I2C_CON_TRX | I2C_CON_STP, 766 OMAP_I2C_CON_REG); 767 768 while (alen) { 769 /* Must write reg offset (one or two bytes) */ 770 status = wait_for_event(i2c_base, ip_rev, waitdelay); 771 /* Try to identify bus that is not padconf'd for I2C */ 772 if (status == I2C_STAT_XRDY) { 773 i2c_error = 2; 774 printf("i2c_write: pads on bus probably not configured (status=0x%x)\n", 775 status); 776 goto wr_exit; 777 } 778 if (status == 0 || (status & I2C_STAT_NACK)) { 779 i2c_error = 1; 780 printf("i2c_write: error waiting for addr ACK (status=0x%x)\n", 781 status); 782 goto wr_exit; 783 } 784 if (status & I2C_STAT_XRDY) { 785 alen--; 786 omap_i2c_write_reg(i2c_base, ip_rev, 787 (addr >> (8 * alen)) & 0xff, 788 OMAP_I2C_DATA_REG); 789 omap_i2c_write_reg(i2c_base, ip_rev, 790 I2C_STAT_XRDY, OMAP_I2C_STAT_REG); 791 } else { 792 i2c_error = 1; 793 printf("i2c_write: bus not ready for addr Tx (status=0x%x)\n", 794 status); 795 goto wr_exit; 796 } 797 } 798 799 /* Address phase is over, now write data */ 800 for (i = 0; i < len; i++) { 801 status = wait_for_event(i2c_base, ip_rev, waitdelay); 802 if (status == 0 || (status & I2C_STAT_NACK)) { 803 i2c_error = 1; 804 printf("i2c_write: error waiting for data ACK (status=0x%x)\n", 805 status); 806 goto wr_exit; 807 } 808 if (status & I2C_STAT_XRDY) { 809 omap_i2c_write_reg(i2c_base, ip_rev, 810 buffer[i], OMAP_I2C_DATA_REG); 811 omap_i2c_write_reg(i2c_base, ip_rev, 812 I2C_STAT_XRDY, OMAP_I2C_STAT_REG); 813 } else { 814 i2c_error = 1; 815 printf("i2c_write: bus not ready for data Tx (i=%d)\n", 816 i); 817 goto wr_exit; 818 } 819 } 820 821 /* 822 * poll ARDY bit for making sure that last byte really has been 823 * transferred on the bus. 824 */ 825 do { 826 status = wait_for_event(i2c_base, ip_rev, waitdelay); 827 } while (!(status & I2C_STAT_ARDY) && timeout--); 828 if (timeout <= 0) 829 printf("i2c_write: timed out writig last byte!\n"); 830 831 wr_exit: 832 flush_fifo(i2c_base, ip_rev); 833 omap_i2c_write_reg(i2c_base, ip_rev, 0xFFFF, OMAP_I2C_STAT_REG); 834 return i2c_error; 835 } 836 837 #ifndef CONFIG_DM_I2C 838 /* 839 * The legacy I2C functions. These need to get removed once 840 * all users of this driver are converted to DM. 841 */ 842 static void __iomem *omap24_get_base(struct i2c_adapter *adap) 843 { 844 switch (adap->hwadapnr) { 845 case 0: 846 return (void __iomem *)I2C_BASE1; 847 break; 848 case 1: 849 return (void __iomem *)I2C_BASE2; 850 break; 851 #if (CONFIG_SYS_I2C_BUS_MAX > 2) 852 case 2: 853 return (void __iomem *)I2C_BASE3; 854 break; 855 #if (CONFIG_SYS_I2C_BUS_MAX > 3) 856 case 3: 857 return (void __iomem *)I2C_BASE4; 858 break; 859 #if (CONFIG_SYS_I2C_BUS_MAX > 4) 860 case 4: 861 return (void __iomem *)I2C_BASE5; 862 break; 863 #endif 864 #endif 865 #endif 866 default: 867 printf("wrong hwadapnr: %d\n", adap->hwadapnr); 868 break; 869 } 870 871 return NULL; 872 } 873 874 static int omap24_get_ip_rev(void) 875 { 876 #ifdef CONFIG_OMAP34XX 877 return OMAP_I2C_REV_V1; 878 #else 879 return OMAP_I2C_REV_V2; 880 #endif 881 } 882 883 static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, 884 int alen, uchar *buffer, int len) 885 { 886 void __iomem *i2c_base = omap24_get_base(adap); 887 int ip_rev = omap24_get_ip_rev(); 888 889 return __omap24_i2c_read(i2c_base, ip_rev, adap->waitdelay, chip, addr, 890 alen, buffer, len); 891 } 892 893 static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, 894 int alen, uchar *buffer, int len) 895 { 896 void __iomem *i2c_base = omap24_get_base(adap); 897 int ip_rev = omap24_get_ip_rev(); 898 899 return __omap24_i2c_write(i2c_base, ip_rev, adap->waitdelay, chip, addr, 900 alen, buffer, len); 901 } 902 903 static uint omap24_i2c_setspeed(struct i2c_adapter *adap, uint speed) 904 { 905 void __iomem *i2c_base = omap24_get_base(adap); 906 int ip_rev = omap24_get_ip_rev(); 907 int ret; 908 909 ret = __omap24_i2c_setspeed(i2c_base, ip_rev, speed, &adap->waitdelay); 910 if (ret) { 911 pr_err("%s: set i2c speed failed\n", __func__); 912 return ret; 913 } 914 915 adap->speed = speed; 916 917 return 0; 918 } 919 920 static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd) 921 { 922 void __iomem *i2c_base = omap24_get_base(adap); 923 int ip_rev = omap24_get_ip_rev(); 924 925 return __omap24_i2c_init(i2c_base, ip_rev, speed, slaveadd, 926 &adap->waitdelay); 927 } 928 929 static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip) 930 { 931 void __iomem *i2c_base = omap24_get_base(adap); 932 int ip_rev = omap24_get_ip_rev(); 933 934 return __omap24_i2c_probe(i2c_base, ip_rev, adap->waitdelay, chip); 935 } 936 937 #if !defined(CONFIG_SYS_OMAP24_I2C_SPEED1) 938 #define CONFIG_SYS_OMAP24_I2C_SPEED1 CONFIG_SYS_OMAP24_I2C_SPEED 939 #endif 940 #if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE1) 941 #define CONFIG_SYS_OMAP24_I2C_SLAVE1 CONFIG_SYS_OMAP24_I2C_SLAVE 942 #endif 943 944 U_BOOT_I2C_ADAP_COMPLETE(omap24_0, omap24_i2c_init, omap24_i2c_probe, 945 omap24_i2c_read, omap24_i2c_write, omap24_i2c_setspeed, 946 CONFIG_SYS_OMAP24_I2C_SPEED, 947 CONFIG_SYS_OMAP24_I2C_SLAVE, 948 0) 949 U_BOOT_I2C_ADAP_COMPLETE(omap24_1, omap24_i2c_init, omap24_i2c_probe, 950 omap24_i2c_read, omap24_i2c_write, omap24_i2c_setspeed, 951 CONFIG_SYS_OMAP24_I2C_SPEED1, 952 CONFIG_SYS_OMAP24_I2C_SLAVE1, 953 1) 954 955 #if (CONFIG_SYS_I2C_BUS_MAX > 2) 956 #if !defined(CONFIG_SYS_OMAP24_I2C_SPEED2) 957 #define CONFIG_SYS_OMAP24_I2C_SPEED2 CONFIG_SYS_OMAP24_I2C_SPEED 958 #endif 959 #if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE2) 960 #define CONFIG_SYS_OMAP24_I2C_SLAVE2 CONFIG_SYS_OMAP24_I2C_SLAVE 961 #endif 962 963 U_BOOT_I2C_ADAP_COMPLETE(omap24_2, omap24_i2c_init, omap24_i2c_probe, 964 omap24_i2c_read, omap24_i2c_write, NULL, 965 CONFIG_SYS_OMAP24_I2C_SPEED2, 966 CONFIG_SYS_OMAP24_I2C_SLAVE2, 967 2) 968 #if (CONFIG_SYS_I2C_BUS_MAX > 3) 969 #if !defined(CONFIG_SYS_OMAP24_I2C_SPEED3) 970 #define CONFIG_SYS_OMAP24_I2C_SPEED3 CONFIG_SYS_OMAP24_I2C_SPEED 971 #endif 972 #if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE3) 973 #define CONFIG_SYS_OMAP24_I2C_SLAVE3 CONFIG_SYS_OMAP24_I2C_SLAVE 974 #endif 975 976 U_BOOT_I2C_ADAP_COMPLETE(omap24_3, omap24_i2c_init, omap24_i2c_probe, 977 omap24_i2c_read, omap24_i2c_write, NULL, 978 CONFIG_SYS_OMAP24_I2C_SPEED3, 979 CONFIG_SYS_OMAP24_I2C_SLAVE3, 980 3) 981 #if (CONFIG_SYS_I2C_BUS_MAX > 4) 982 #if !defined(CONFIG_SYS_OMAP24_I2C_SPEED4) 983 #define CONFIG_SYS_OMAP24_I2C_SPEED4 CONFIG_SYS_OMAP24_I2C_SPEED 984 #endif 985 #if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE4) 986 #define CONFIG_SYS_OMAP24_I2C_SLAVE4 CONFIG_SYS_OMAP24_I2C_SLAVE 987 #endif 988 989 U_BOOT_I2C_ADAP_COMPLETE(omap24_4, omap24_i2c_init, omap24_i2c_probe, 990 omap24_i2c_read, omap24_i2c_write, NULL, 991 CONFIG_SYS_OMAP24_I2C_SPEED4, 992 CONFIG_SYS_OMAP24_I2C_SLAVE4, 993 4) 994 #endif 995 #endif 996 #endif 997 998 #else /* CONFIG_DM_I2C */ 999 1000 static int omap_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs) 1001 { 1002 struct omap_i2c *priv = dev_get_priv(bus); 1003 int ret; 1004 1005 debug("i2c_xfer: %d messages\n", nmsgs); 1006 for (; nmsgs > 0; nmsgs--, msg++) { 1007 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len); 1008 if (msg->flags & I2C_M_RD) { 1009 ret = __omap24_i2c_read(priv->regs, priv->ip_rev, 1010 priv->waitdelay, 1011 msg->addr, 0, 0, msg->buf, 1012 msg->len); 1013 } else { 1014 ret = __omap24_i2c_write(priv->regs, priv->ip_rev, 1015 priv->waitdelay, 1016 msg->addr, 0, 0, msg->buf, 1017 msg->len); 1018 } 1019 if (ret) { 1020 debug("i2c_write: error sending\n"); 1021 return -EREMOTEIO; 1022 } 1023 } 1024 1025 return 0; 1026 } 1027 1028 static int omap_i2c_set_bus_speed(struct udevice *bus, unsigned int speed) 1029 { 1030 struct omap_i2c *priv = dev_get_priv(bus); 1031 1032 priv->speed = speed; 1033 1034 return __omap24_i2c_setspeed(priv->regs, priv->ip_rev, speed, 1035 &priv->waitdelay); 1036 } 1037 1038 static int omap_i2c_probe_chip(struct udevice *bus, uint chip_addr, 1039 uint chip_flags) 1040 { 1041 struct omap_i2c *priv = dev_get_priv(bus); 1042 1043 return __omap24_i2c_probe(priv->regs, priv->ip_rev, priv->waitdelay, 1044 chip_addr); 1045 } 1046 1047 static int omap_i2c_probe(struct udevice *bus) 1048 { 1049 struct omap_i2c *priv = dev_get_priv(bus); 1050 struct omap_i2c_platdata *plat = dev_get_platdata(bus); 1051 1052 priv->speed = plat->speed; 1053 priv->regs = map_physmem(plat->base, sizeof(void *), 1054 MAP_NOCACHE); 1055 priv->ip_rev = plat->ip_rev; 1056 1057 __omap24_i2c_init(priv->regs, priv->ip_rev, priv->speed, 0, 1058 &priv->waitdelay); 1059 1060 return 0; 1061 } 1062 1063 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) 1064 static int omap_i2c_ofdata_to_platdata(struct udevice *bus) 1065 { 1066 struct omap_i2c_platdata *plat = dev_get_platdata(bus); 1067 1068 plat->base = devfdt_get_addr(bus); 1069 plat->speed = dev_read_u32_default(bus, "clock-frequency", 100000); 1070 plat->ip_rev = dev_get_driver_data(bus); 1071 1072 return 0; 1073 } 1074 1075 static const struct udevice_id omap_i2c_ids[] = { 1076 { .compatible = "ti,omap3-i2c", .data = OMAP_I2C_REV_V1 }, 1077 { .compatible = "ti,omap4-i2c", .data = OMAP_I2C_REV_V2 }, 1078 { } 1079 }; 1080 #endif 1081 1082 static const struct dm_i2c_ops omap_i2c_ops = { 1083 .xfer = omap_i2c_xfer, 1084 .probe_chip = omap_i2c_probe_chip, 1085 .set_bus_speed = omap_i2c_set_bus_speed, 1086 }; 1087 1088 U_BOOT_DRIVER(i2c_omap) = { 1089 .name = "i2c_omap", 1090 .id = UCLASS_I2C, 1091 #if CONFIG_IS_ENABLED(OF_CONTROL) && !CONFIG_IS_ENABLED(OF_PLATDATA) 1092 .of_match = omap_i2c_ids, 1093 .ofdata_to_platdata = omap_i2c_ofdata_to_platdata, 1094 .platdata_auto_alloc_size = sizeof(struct omap_i2c_platdata), 1095 #endif 1096 .probe = omap_i2c_probe, 1097 .priv_auto_alloc_size = sizeof(struct omap_i2c), 1098 .ops = &omap_i2c_ops, 1099 #if !CONFIG_IS_ENABLED(OF_CONTROL) 1100 .flags = DM_FLAG_PRE_RELOC, 1101 #endif 1102 }; 1103 1104 #endif /* CONFIG_DM_I2C */ 1105