1 /* 2 * Basic I2C functions 3 * 4 * Copyright (c) 2004 Texas Instruments 5 * 6 * This package is free software; you can redistribute it and/or 7 * modify it under the terms of the license found in the file 8 * named COPYING that should have accompanied this file. 9 * 10 * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR 11 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED 12 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. 13 * 14 * Author: Jian Zhang jzhang@ti.com, Texas Instruments 15 * 16 * Copyright (c) 2003 Wolfgang Denk, wd@denx.de 17 * Rewritten to fit into the current U-Boot framework 18 * 19 * Adapted for OMAP2420 I2C, r-woodruff2@ti.com 20 * 21 */ 22 23 #include <common.h> 24 25 #include <asm/arch/i2c.h> 26 #include <asm/io.h> 27 28 #include "omap24xx_i2c.h" 29 30 DECLARE_GLOBAL_DATA_PTR; 31 32 #define I2C_TIMEOUT 1000 33 34 static void wait_for_bb(void); 35 static u16 wait_for_pin(void); 36 static void flush_fifo(void); 37 38 /* 39 * For SPL boot some boards need i2c before SDRAM is initialised so force 40 * variables to live in SRAM 41 */ 42 static struct i2c __attribute__((section (".data"))) *i2c_base = 43 (struct i2c *)I2C_DEFAULT_BASE; 44 static unsigned int __attribute__((section (".data"))) bus_initialized[I2C_BUS_MAX] = 45 { [0 ... (I2C_BUS_MAX-1)] = 0 }; 46 static unsigned int __attribute__((section (".data"))) current_bus = 0; 47 48 void i2c_init(int speed, int slaveadd) 49 { 50 int psc, fsscll, fssclh; 51 int hsscll = 0, hssclh = 0; 52 u32 scll, sclh; 53 int timeout = I2C_TIMEOUT; 54 55 /* Only handle standard, fast and high speeds */ 56 if ((speed != OMAP_I2C_STANDARD) && 57 (speed != OMAP_I2C_FAST_MODE) && 58 (speed != OMAP_I2C_HIGH_SPEED)) { 59 printf("Error : I2C unsupported speed %d\n", speed); 60 return; 61 } 62 63 psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK; 64 psc -= 1; 65 if (psc < I2C_PSC_MIN) { 66 printf("Error : I2C unsupported prescalar %d\n", psc); 67 return; 68 } 69 70 if (speed == OMAP_I2C_HIGH_SPEED) { 71 /* High speed */ 72 73 /* For first phase of HS mode */ 74 fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK / 75 (2 * OMAP_I2C_FAST_MODE); 76 77 fsscll -= I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM; 78 fssclh -= I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM; 79 if (((fsscll < 0) || (fssclh < 0)) || 80 ((fsscll > 255) || (fssclh > 255))) { 81 puts("Error : I2C initializing first phase clock\n"); 82 return; 83 } 84 85 /* For second phase of HS mode */ 86 hsscll = hssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed); 87 88 hsscll -= I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM; 89 hssclh -= I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM; 90 if (((fsscll < 0) || (fssclh < 0)) || 91 ((fsscll > 255) || (fssclh > 255))) { 92 puts("Error : I2C initializing second phase clock\n"); 93 return; 94 } 95 96 scll = (unsigned int)hsscll << 8 | (unsigned int)fsscll; 97 sclh = (unsigned int)hssclh << 8 | (unsigned int)fssclh; 98 99 } else { 100 /* Standard and fast speed */ 101 fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed); 102 103 fsscll -= I2C_FASTSPEED_SCLL_TRIM; 104 fssclh -= I2C_FASTSPEED_SCLH_TRIM; 105 if (((fsscll < 0) || (fssclh < 0)) || 106 ((fsscll > 255) || (fssclh > 255))) { 107 puts("Error : I2C initializing clock\n"); 108 return; 109 } 110 111 scll = (unsigned int)fsscll; 112 sclh = (unsigned int)fssclh; 113 } 114 115 if (readw(&i2c_base->con) & I2C_CON_EN) { 116 writew(0, &i2c_base->con); 117 udelay(50000); 118 } 119 120 writew(0x2, &i2c_base->sysc); /* for ES2 after soft reset */ 121 udelay(1000); 122 123 writew(I2C_CON_EN, &i2c_base->con); 124 while (!(readw(&i2c_base->syss) & I2C_SYSS_RDONE) && timeout--) { 125 if (timeout <= 0) { 126 puts("ERROR: Timeout in soft-reset\n"); 127 return; 128 } 129 udelay(1000); 130 } 131 132 writew(0, &i2c_base->con); 133 writew(psc, &i2c_base->psc); 134 writew(scll, &i2c_base->scll); 135 writew(sclh, &i2c_base->sclh); 136 137 /* own address */ 138 writew(slaveadd, &i2c_base->oa); 139 writew(I2C_CON_EN, &i2c_base->con); 140 141 /* have to enable intrrupts or OMAP i2c module doesn't work */ 142 writew(I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | 143 I2C_IE_NACK_IE | I2C_IE_AL_IE, &i2c_base->ie); 144 udelay(1000); 145 flush_fifo(); 146 writew(0xFFFF, &i2c_base->stat); 147 writew(0, &i2c_base->cnt); 148 149 if (gd->flags & GD_FLG_RELOC) 150 bus_initialized[current_bus] = 1; 151 } 152 153 static int i2c_read_byte(u8 devaddr, u8 regoffset, u8 *value) 154 { 155 int i2c_error = 0; 156 u16 status; 157 158 /* wait until bus not busy */ 159 wait_for_bb(); 160 161 /* one byte only */ 162 writew(1, &i2c_base->cnt); 163 /* set slave address */ 164 writew(devaddr, &i2c_base->sa); 165 /* no stop bit needed here */ 166 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | 167 I2C_CON_TRX, &i2c_base->con); 168 169 /* send register offset */ 170 while (1) { 171 status = wait_for_pin(); 172 if (status == 0 || status & I2C_STAT_NACK) { 173 i2c_error = 1; 174 goto read_exit; 175 } 176 if (status & I2C_STAT_XRDY) { 177 /* Important: have to use byte access */ 178 writeb(regoffset, &i2c_base->data); 179 writew(I2C_STAT_XRDY, &i2c_base->stat); 180 } 181 if (status & I2C_STAT_ARDY) { 182 writew(I2C_STAT_ARDY, &i2c_base->stat); 183 break; 184 } 185 } 186 187 /* set slave address */ 188 writew(devaddr, &i2c_base->sa); 189 /* read one byte from slave */ 190 writew(1, &i2c_base->cnt); 191 /* need stop bit here */ 192 writew(I2C_CON_EN | I2C_CON_MST | 193 I2C_CON_STT | I2C_CON_STP, 194 &i2c_base->con); 195 196 /* receive data */ 197 while (1) { 198 status = wait_for_pin(); 199 if (status == 0 || status & I2C_STAT_NACK) { 200 i2c_error = 1; 201 goto read_exit; 202 } 203 if (status & I2C_STAT_RRDY) { 204 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \ 205 defined(CONFIG_OMAP44XX) 206 *value = readb(&i2c_base->data); 207 #else 208 *value = readw(&i2c_base->data); 209 #endif 210 writew(I2C_STAT_RRDY, &i2c_base->stat); 211 } 212 if (status & I2C_STAT_ARDY) { 213 writew(I2C_STAT_ARDY, &i2c_base->stat); 214 break; 215 } 216 } 217 218 read_exit: 219 flush_fifo(); 220 writew(0xFFFF, &i2c_base->stat); 221 writew(0, &i2c_base->cnt); 222 return i2c_error; 223 } 224 225 static void flush_fifo(void) 226 { u16 stat; 227 228 /* note: if you try and read data when its not there or ready 229 * you get a bus error 230 */ 231 while (1) { 232 stat = readw(&i2c_base->stat); 233 if (stat == I2C_STAT_RRDY) { 234 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \ 235 defined(CONFIG_OMAP44XX) 236 readb(&i2c_base->data); 237 #else 238 readw(&i2c_base->data); 239 #endif 240 writew(I2C_STAT_RRDY, &i2c_base->stat); 241 udelay(1000); 242 } else 243 break; 244 } 245 } 246 247 int i2c_probe(uchar chip) 248 { 249 u16 status; 250 int res = 1; /* default = fail */ 251 252 if (chip == readw(&i2c_base->oa)) 253 return res; 254 255 /* wait until bus not busy */ 256 wait_for_bb(); 257 258 /* try to write one byte */ 259 writew(1, &i2c_base->cnt); 260 /* set slave address */ 261 writew(chip, &i2c_base->sa); 262 /* stop bit needed here */ 263 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | 264 I2C_CON_STP, &i2c_base->con); 265 266 status = wait_for_pin(); 267 268 /* check for ACK (!NAK) */ 269 if (!(status & I2C_STAT_NACK)) 270 res = 0; 271 272 /* abort transfer (force idle state) */ 273 writew(0, &i2c_base->con); 274 275 flush_fifo(); 276 /* don't allow any more data in... we don't want it. */ 277 writew(0, &i2c_base->cnt); 278 writew(0xFFFF, &i2c_base->stat); 279 return res; 280 } 281 282 int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) 283 { 284 int i; 285 286 if (alen > 1) { 287 printf("I2C read: addr len %d not supported\n", alen); 288 return 1; 289 } 290 291 if (addr + len > 256) { 292 puts("I2C read: address out of range\n"); 293 return 1; 294 } 295 296 for (i = 0; i < len; i++) { 297 if (i2c_read_byte(chip, addr + i, &buffer[i])) { 298 puts("I2C read: I/O error\n"); 299 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 300 return 1; 301 } 302 } 303 304 return 0; 305 } 306 307 int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) 308 { 309 int i; 310 u16 status; 311 int i2c_error = 0; 312 313 if (alen > 1) { 314 printf("I2C write: addr len %d not supported\n", alen); 315 return 1; 316 } 317 318 if (addr + len > 256) { 319 printf("I2C write: address 0x%x + 0x%x out of range\n", 320 addr, len); 321 return 1; 322 } 323 324 /* wait until bus not busy */ 325 wait_for_bb(); 326 327 /* start address phase - will write regoffset + len bytes data */ 328 /* TODO consider case when !CONFIG_OMAP243X/34XX/44XX */ 329 writew(alen + len, &i2c_base->cnt); 330 /* set slave address */ 331 writew(chip, &i2c_base->sa); 332 /* stop bit needed here */ 333 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | 334 I2C_CON_STP, &i2c_base->con); 335 336 /* Send address byte */ 337 status = wait_for_pin(); 338 339 if (status == 0 || status & I2C_STAT_NACK) { 340 i2c_error = 1; 341 printf("error waiting for i2c address ACK (status=0x%x)\n", 342 status); 343 goto write_exit; 344 } 345 346 if (status & I2C_STAT_XRDY) { 347 writeb(addr & 0xFF, &i2c_base->data); 348 writew(I2C_STAT_XRDY, &i2c_base->stat); 349 } else { 350 i2c_error = 1; 351 printf("i2c bus not ready for transmit (status=0x%x)\n", 352 status); 353 goto write_exit; 354 } 355 356 /* address phase is over, now write data */ 357 for (i = 0; i < len; i++) { 358 status = wait_for_pin(); 359 360 if (status == 0 || status & I2C_STAT_NACK) { 361 i2c_error = 1; 362 printf("i2c error waiting for data ACK (status=0x%x)\n", 363 status); 364 goto write_exit; 365 } 366 367 if (status & I2C_STAT_XRDY) { 368 writeb(buffer[i], &i2c_base->data); 369 writew(I2C_STAT_XRDY, &i2c_base->stat); 370 } else { 371 i2c_error = 1; 372 printf("i2c bus not ready for Tx (i=%d)\n", i); 373 goto write_exit; 374 } 375 } 376 377 write_exit: 378 flush_fifo(); 379 writew(0xFFFF, &i2c_base->stat); 380 return i2c_error; 381 } 382 383 static void wait_for_bb(void) 384 { 385 int timeout = I2C_TIMEOUT; 386 u16 stat; 387 388 writew(0xFFFF, &i2c_base->stat); /* clear current interrupts...*/ 389 while ((stat = readw(&i2c_base->stat) & I2C_STAT_BB) && timeout--) { 390 writew(stat, &i2c_base->stat); 391 udelay(1000); 392 } 393 394 if (timeout <= 0) { 395 printf("timed out in wait_for_bb: I2C_STAT=%x\n", 396 readw(&i2c_base->stat)); 397 } 398 writew(0xFFFF, &i2c_base->stat); /* clear delayed stuff*/ 399 } 400 401 static u16 wait_for_pin(void) 402 { 403 u16 status; 404 int timeout = I2C_TIMEOUT; 405 406 do { 407 udelay(1000); 408 status = readw(&i2c_base->stat); 409 } while (!(status & 410 (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY | 411 I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK | 412 I2C_STAT_AL)) && timeout--); 413 414 if (timeout <= 0) { 415 printf("timed out in wait_for_pin: I2C_STAT=%x\n", 416 readw(&i2c_base->stat)); 417 writew(0xFFFF, &i2c_base->stat); 418 status = 0; 419 } 420 421 return status; 422 } 423 424 int i2c_set_bus_num(unsigned int bus) 425 { 426 if ((bus < 0) || (bus >= I2C_BUS_MAX)) { 427 printf("Bad bus: %d\n", bus); 428 return -1; 429 } 430 431 #if I2C_BUS_MAX == 3 432 if (bus == 2) 433 i2c_base = (struct i2c *)I2C_BASE3; 434 else 435 #endif 436 if (bus == 1) 437 i2c_base = (struct i2c *)I2C_BASE2; 438 else 439 i2c_base = (struct i2c *)I2C_BASE1; 440 441 current_bus = bus; 442 443 if (!bus_initialized[current_bus]) 444 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 445 446 return 0; 447 } 448 449 int i2c_get_bus_num(void) 450 { 451 return (int) current_bus; 452 } 453