1 /* 2 * Basic I2C functions 3 * 4 * Copyright (c) 2004 Texas Instruments 5 * 6 * This package is free software; you can redistribute it and/or 7 * modify it under the terms of the license found in the file 8 * named COPYING that should have accompanied this file. 9 * 10 * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR 11 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED 12 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. 13 * 14 * Author: Jian Zhang jzhang@ti.com, Texas Instruments 15 * 16 * Copyright (c) 2003 Wolfgang Denk, wd@denx.de 17 * Rewritten to fit into the current U-Boot framework 18 * 19 * Adapted for OMAP2420 I2C, r-woodruff2@ti.com 20 * 21 * Copyright (c) 2013 Lubomir Popov <lpopov@mm-sol.com>, MM Solutions 22 * New i2c_read, i2c_write and i2c_probe functions, tested on OMAP4 23 * (4430/60/70), OMAP5 (5430) and AM335X (3359); should work on older 24 * OMAPs and derivatives as well. The only anticipated exception would 25 * be the OMAP2420, which shall require driver modification. 26 * - Rewritten i2c_read to operate correctly with all types of chips 27 * (old function could not read consistent data from some I2C slaves). 28 * - Optimized i2c_write. 29 * - New i2c_probe, performs write access vs read. The old probe could 30 * hang the system under certain conditions (e.g. unconfigured pads). 31 * - The read/write/probe functions try to identify unconfigured bus. 32 * - Status functions now read irqstatus_raw as per TRM guidelines 33 * (except for OMAP243X and OMAP34XX). 34 * - Driver now supports up to I2C5 (OMAP5). 35 * 36 * Copyright (c) 2014 Hannes Petermaier <oe5hpm@oevsv.at>, B&R 37 * - Added support for set_speed 38 * 39 */ 40 41 #include <common.h> 42 #include <i2c.h> 43 44 #include <asm/arch/i2c.h> 45 #include <asm/io.h> 46 47 #include "omap24xx_i2c.h" 48 49 DECLARE_GLOBAL_DATA_PTR; 50 51 #define I2C_TIMEOUT 1000 52 53 /* Absolutely safe for status update at 100 kHz I2C: */ 54 #define I2C_WAIT 200 55 56 static int wait_for_bb(struct i2c_adapter *adap); 57 static struct i2c *omap24_get_base(struct i2c_adapter *adap); 58 static u16 wait_for_event(struct i2c_adapter *adap); 59 static void flush_fifo(struct i2c_adapter *adap); 60 static int omap24_i2c_findpsc(u32 *pscl, u32 *psch, uint speed) 61 { 62 unsigned int sampleclk, prescaler; 63 int fsscll, fssclh; 64 65 speed <<= 1; 66 prescaler = 0; 67 /* 68 * some divisors may cause a precission loss, but shouldn't 69 * be a big thing, because i2c_clk is then allready very slow. 70 */ 71 while (prescaler <= 0xFF) { 72 sampleclk = I2C_IP_CLK / (prescaler+1); 73 74 fsscll = sampleclk / speed; 75 fssclh = fsscll; 76 fsscll -= I2C_FASTSPEED_SCLL_TRIM; 77 fssclh -= I2C_FASTSPEED_SCLH_TRIM; 78 79 if (((fsscll > 0) && (fssclh > 0)) && 80 ((fsscll <= (255-I2C_FASTSPEED_SCLL_TRIM)) && 81 (fssclh <= (255-I2C_FASTSPEED_SCLH_TRIM)))) { 82 if (pscl) 83 *pscl = fsscll; 84 if (psch) 85 *psch = fssclh; 86 87 return prescaler; 88 } 89 prescaler++; 90 } 91 return -1; 92 } 93 static uint omap24_i2c_setspeed(struct i2c_adapter *adap, uint speed) 94 { 95 struct i2c *i2c_base = omap24_get_base(adap); 96 int psc, fsscll = 0, fssclh = 0; 97 int hsscll = 0, hssclh = 0; 98 u32 scll = 0, sclh = 0; 99 100 if (speed >= OMAP_I2C_HIGH_SPEED) { 101 /* High speed */ 102 psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK; 103 psc -= 1; 104 if (psc < I2C_PSC_MIN) { 105 printf("Error : I2C unsupported prescaler %d\n", psc); 106 return -1; 107 } 108 109 /* For first phase of HS mode */ 110 fsscll = I2C_INTERNAL_SAMPLING_CLK / (2 * speed); 111 112 fssclh = fsscll; 113 114 fsscll -= I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM; 115 fssclh -= I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM; 116 if (((fsscll < 0) || (fssclh < 0)) || 117 ((fsscll > 255) || (fssclh > 255))) { 118 puts("Error : I2C initializing first phase clock\n"); 119 return -1; 120 } 121 122 /* For second phase of HS mode */ 123 hsscll = hssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed); 124 125 hsscll -= I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM; 126 hssclh -= I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM; 127 if (((fsscll < 0) || (fssclh < 0)) || 128 ((fsscll > 255) || (fssclh > 255))) { 129 puts("Error : I2C initializing second phase clock\n"); 130 return -1; 131 } 132 133 scll = (unsigned int)hsscll << 8 | (unsigned int)fsscll; 134 sclh = (unsigned int)hssclh << 8 | (unsigned int)fssclh; 135 136 } else { 137 /* Standard and fast speed */ 138 psc = omap24_i2c_findpsc(&scll, &sclh, speed); 139 if (0 > psc) { 140 puts("Error : I2C initializing clock\n"); 141 return -1; 142 } 143 } 144 145 adap->speed = speed; 146 adap->waitdelay = (10000000 / speed) * 2; /* wait for 20 clkperiods */ 147 writew(0, &i2c_base->con); 148 writew(psc, &i2c_base->psc); 149 writew(scll, &i2c_base->scll); 150 writew(sclh, &i2c_base->sclh); 151 writew(I2C_CON_EN, &i2c_base->con); 152 writew(0xFFFF, &i2c_base->stat); /* clear all pending status */ 153 154 return 0; 155 } 156 static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd) 157 { 158 struct i2c *i2c_base = omap24_get_base(adap); 159 int timeout = I2C_TIMEOUT; 160 161 if (readw(&i2c_base->con) & I2C_CON_EN) { 162 writew(0, &i2c_base->con); 163 udelay(50000); 164 } 165 166 writew(0x2, &i2c_base->sysc); /* for ES2 after soft reset */ 167 udelay(1000); 168 169 writew(I2C_CON_EN, &i2c_base->con); 170 while (!(readw(&i2c_base->syss) & I2C_SYSS_RDONE) && timeout--) { 171 if (timeout <= 0) { 172 puts("ERROR: Timeout in soft-reset\n"); 173 return; 174 } 175 udelay(1000); 176 } 177 178 if (0 != omap24_i2c_setspeed(adap, speed)) { 179 printf("ERROR: failed to setup I2C bus-speed!\n"); 180 return; 181 } 182 183 /* own address */ 184 writew(slaveadd, &i2c_base->oa); 185 186 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) 187 /* 188 * Have to enable interrupts for OMAP2/3, these IPs don't have 189 * an 'irqstatus_raw' register and we shall have to poll 'stat' 190 */ 191 writew(I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | 192 I2C_IE_NACK_IE | I2C_IE_AL_IE, &i2c_base->ie); 193 #endif 194 udelay(1000); 195 flush_fifo(adap); 196 writew(0xFFFF, &i2c_base->stat); 197 } 198 199 static void flush_fifo(struct i2c_adapter *adap) 200 { 201 struct i2c *i2c_base = omap24_get_base(adap); 202 u16 stat; 203 204 /* 205 * note: if you try and read data when its not there or ready 206 * you get a bus error 207 */ 208 while (1) { 209 stat = readw(&i2c_base->stat); 210 if (stat == I2C_STAT_RRDY) { 211 readb(&i2c_base->data); 212 writew(I2C_STAT_RRDY, &i2c_base->stat); 213 udelay(1000); 214 } else 215 break; 216 } 217 } 218 219 /* 220 * i2c_probe: Use write access. Allows to identify addresses that are 221 * write-only (like the config register of dual-port EEPROMs) 222 */ 223 static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip) 224 { 225 struct i2c *i2c_base = omap24_get_base(adap); 226 u16 status; 227 int res = 1; /* default = fail */ 228 229 if (chip == readw(&i2c_base->oa)) 230 return res; 231 232 /* Wait until bus is free */ 233 if (wait_for_bb(adap)) 234 return res; 235 236 /* No data transfer, slave addr only */ 237 writew(chip, &i2c_base->sa); 238 /* Stop bit needed here */ 239 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | 240 I2C_CON_STP, &i2c_base->con); 241 242 status = wait_for_event(adap); 243 244 if ((status & ~I2C_STAT_XRDY) == 0 || (status & I2C_STAT_AL)) { 245 /* 246 * With current high-level command implementation, notifying 247 * the user shall flood the console with 127 messages. If 248 * silent exit is desired upon unconfigured bus, remove the 249 * following 'if' section: 250 */ 251 if (status == I2C_STAT_XRDY) 252 printf("i2c_probe: pads on bus %d probably not configured (status=0x%x)\n", 253 adap->hwadapnr, status); 254 255 goto pr_exit; 256 } 257 258 /* Check for ACK (!NAK) */ 259 if (!(status & I2C_STAT_NACK)) { 260 res = 0; /* Device found */ 261 udelay(adap->waitdelay);/* Required by AM335X in SPL */ 262 /* Abort transfer (force idle state) */ 263 writew(I2C_CON_MST | I2C_CON_TRX, &i2c_base->con); /* Reset */ 264 udelay(1000); 265 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_TRX | 266 I2C_CON_STP, &i2c_base->con); /* STP */ 267 } 268 pr_exit: 269 flush_fifo(adap); 270 writew(0xFFFF, &i2c_base->stat); 271 return res; 272 } 273 274 /* 275 * i2c_read: Function now uses a single I2C read transaction with bulk transfer 276 * of the requested number of bytes (note that the 'i2c md' command 277 * limits this to 16 bytes anyway). If CONFIG_I2C_REPEATED_START is 278 * defined in the board config header, this transaction shall be with 279 * Repeated Start (Sr) between the address and data phases; otherwise 280 * Stop-Start (P-S) shall be used (some I2C chips do require a P-S). 281 * The address (reg offset) may be 0, 1 or 2 bytes long. 282 * Function now reads correctly from chips that return more than one 283 * byte of data per addressed register (like TI temperature sensors), 284 * or that do not need a register address at all (such as some clock 285 * distributors). 286 */ 287 static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, 288 int alen, uchar *buffer, int len) 289 { 290 struct i2c *i2c_base = omap24_get_base(adap); 291 int i2c_error = 0; 292 u16 status; 293 294 if (alen < 0) { 295 puts("I2C read: addr len < 0\n"); 296 return 1; 297 } 298 if (len < 0) { 299 puts("I2C read: data len < 0\n"); 300 return 1; 301 } 302 if (buffer == NULL) { 303 puts("I2C read: NULL pointer passed\n"); 304 return 1; 305 } 306 307 if (alen > 2) { 308 printf("I2C read: addr len %d not supported\n", alen); 309 return 1; 310 } 311 312 if (addr + len > (1 << 16)) { 313 puts("I2C read: address out of range\n"); 314 return 1; 315 } 316 317 /* Wait until bus not busy */ 318 if (wait_for_bb(adap)) 319 return 1; 320 321 /* Zero, one or two bytes reg address (offset) */ 322 writew(alen, &i2c_base->cnt); 323 /* Set slave address */ 324 writew(chip, &i2c_base->sa); 325 326 if (alen) { 327 /* Must write reg offset first */ 328 #ifdef CONFIG_I2C_REPEATED_START 329 /* No stop bit, use Repeated Start (Sr) */ 330 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | 331 I2C_CON_TRX, &i2c_base->con); 332 #else 333 /* Stop - Start (P-S) */ 334 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP | 335 I2C_CON_TRX, &i2c_base->con); 336 #endif 337 /* Send register offset */ 338 while (1) { 339 status = wait_for_event(adap); 340 /* Try to identify bus that is not padconf'd for I2C */ 341 if (status == I2C_STAT_XRDY) { 342 i2c_error = 2; 343 printf("i2c_read (addr phase): pads on bus %d probably not configured (status=0x%x)\n", 344 adap->hwadapnr, status); 345 goto rd_exit; 346 } 347 if (status == 0 || (status & I2C_STAT_NACK)) { 348 i2c_error = 1; 349 printf("i2c_read: error waiting for addr ACK (status=0x%x)\n", 350 status); 351 goto rd_exit; 352 } 353 if (alen) { 354 if (status & I2C_STAT_XRDY) { 355 alen--; 356 /* Do we have to use byte access? */ 357 writeb((addr >> (8 * alen)) & 0xff, 358 &i2c_base->data); 359 writew(I2C_STAT_XRDY, &i2c_base->stat); 360 } 361 } 362 if (status & I2C_STAT_ARDY) { 363 writew(I2C_STAT_ARDY, &i2c_base->stat); 364 break; 365 } 366 } 367 } 368 /* Set slave address */ 369 writew(chip, &i2c_base->sa); 370 /* Read len bytes from slave */ 371 writew(len, &i2c_base->cnt); 372 /* Need stop bit here */ 373 writew(I2C_CON_EN | I2C_CON_MST | 374 I2C_CON_STT | I2C_CON_STP, 375 &i2c_base->con); 376 377 /* Receive data */ 378 while (1) { 379 status = wait_for_event(adap); 380 /* 381 * Try to identify bus that is not padconf'd for I2C. This 382 * state could be left over from previous transactions if 383 * the address phase is skipped due to alen=0. 384 */ 385 if (status == I2C_STAT_XRDY) { 386 i2c_error = 2; 387 printf("i2c_read (data phase): pads on bus %d probably not configured (status=0x%x)\n", 388 adap->hwadapnr, status); 389 goto rd_exit; 390 } 391 if (status == 0 || (status & I2C_STAT_NACK)) { 392 i2c_error = 1; 393 goto rd_exit; 394 } 395 if (status & I2C_STAT_RRDY) { 396 *buffer++ = readb(&i2c_base->data); 397 writew(I2C_STAT_RRDY, &i2c_base->stat); 398 } 399 if (status & I2C_STAT_ARDY) { 400 writew(I2C_STAT_ARDY, &i2c_base->stat); 401 break; 402 } 403 } 404 405 rd_exit: 406 flush_fifo(adap); 407 writew(0xFFFF, &i2c_base->stat); 408 return i2c_error; 409 } 410 411 /* i2c_write: Address (reg offset) may be 0, 1 or 2 bytes long. */ 412 static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, 413 int alen, uchar *buffer, int len) 414 { 415 struct i2c *i2c_base = omap24_get_base(adap); 416 int i; 417 u16 status; 418 int i2c_error = 0; 419 int timeout = I2C_TIMEOUT; 420 421 if (alen < 0) { 422 puts("I2C write: addr len < 0\n"); 423 return 1; 424 } 425 426 if (len < 0) { 427 puts("I2C write: data len < 0\n"); 428 return 1; 429 } 430 431 if (buffer == NULL) { 432 puts("I2C write: NULL pointer passed\n"); 433 return 1; 434 } 435 436 if (alen > 2) { 437 printf("I2C write: addr len %d not supported\n", alen); 438 return 1; 439 } 440 441 if (addr + len > (1 << 16)) { 442 printf("I2C write: address 0x%x + 0x%x out of range\n", 443 addr, len); 444 return 1; 445 } 446 447 /* Wait until bus not busy */ 448 if (wait_for_bb(adap)) 449 return 1; 450 451 /* Start address phase - will write regoffset + len bytes data */ 452 writew(alen + len, &i2c_base->cnt); 453 /* Set slave address */ 454 writew(chip, &i2c_base->sa); 455 /* Stop bit needed here */ 456 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | 457 I2C_CON_STP, &i2c_base->con); 458 459 while (alen) { 460 /* Must write reg offset (one or two bytes) */ 461 status = wait_for_event(adap); 462 /* Try to identify bus that is not padconf'd for I2C */ 463 if (status == I2C_STAT_XRDY) { 464 i2c_error = 2; 465 printf("i2c_write: pads on bus %d probably not configured (status=0x%x)\n", 466 adap->hwadapnr, status); 467 goto wr_exit; 468 } 469 if (status == 0 || (status & I2C_STAT_NACK)) { 470 i2c_error = 1; 471 printf("i2c_write: error waiting for addr ACK (status=0x%x)\n", 472 status); 473 goto wr_exit; 474 } 475 if (status & I2C_STAT_XRDY) { 476 alen--; 477 writeb((addr >> (8 * alen)) & 0xff, &i2c_base->data); 478 writew(I2C_STAT_XRDY, &i2c_base->stat); 479 } else { 480 i2c_error = 1; 481 printf("i2c_write: bus not ready for addr Tx (status=0x%x)\n", 482 status); 483 goto wr_exit; 484 } 485 } 486 /* Address phase is over, now write data */ 487 for (i = 0; i < len; i++) { 488 status = wait_for_event(adap); 489 if (status == 0 || (status & I2C_STAT_NACK)) { 490 i2c_error = 1; 491 printf("i2c_write: error waiting for data ACK (status=0x%x)\n", 492 status); 493 goto wr_exit; 494 } 495 if (status & I2C_STAT_XRDY) { 496 writeb(buffer[i], &i2c_base->data); 497 writew(I2C_STAT_XRDY, &i2c_base->stat); 498 } else { 499 i2c_error = 1; 500 printf("i2c_write: bus not ready for data Tx (i=%d)\n", 501 i); 502 goto wr_exit; 503 } 504 } 505 /* 506 * poll ARDY bit for making sure that last byte really has been 507 * transferred on the bus. 508 */ 509 do { 510 status = wait_for_event(adap); 511 } while (!(status & I2C_STAT_ARDY) && timeout--); 512 if (timeout <= 0) 513 printf("i2c_write: timed out writig last byte!\n"); 514 515 wr_exit: 516 flush_fifo(adap); 517 writew(0xFFFF, &i2c_base->stat); 518 return i2c_error; 519 } 520 521 /* 522 * Wait for the bus to be free by checking the Bus Busy (BB) 523 * bit to become clear 524 */ 525 static int wait_for_bb(struct i2c_adapter *adap) 526 { 527 struct i2c *i2c_base = omap24_get_base(adap); 528 int timeout = I2C_TIMEOUT; 529 u16 stat; 530 531 writew(0xFFFF, &i2c_base->stat); /* clear current interrupts...*/ 532 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) 533 while ((stat = readw(&i2c_base->stat) & I2C_STAT_BB) && timeout--) { 534 #else 535 /* Read RAW status */ 536 while ((stat = readw(&i2c_base->irqstatus_raw) & 537 I2C_STAT_BB) && timeout--) { 538 #endif 539 writew(stat, &i2c_base->stat); 540 udelay(adap->waitdelay); 541 } 542 543 if (timeout <= 0) { 544 printf("Timed out in wait_for_bb: status=%04x\n", 545 stat); 546 return 1; 547 } 548 writew(0xFFFF, &i2c_base->stat); /* clear delayed stuff*/ 549 return 0; 550 } 551 552 /* 553 * Wait for the I2C controller to complete current action 554 * and update status 555 */ 556 static u16 wait_for_event(struct i2c_adapter *adap) 557 { 558 struct i2c *i2c_base = omap24_get_base(adap); 559 u16 status; 560 int timeout = I2C_TIMEOUT; 561 562 do { 563 udelay(adap->waitdelay); 564 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) 565 status = readw(&i2c_base->stat); 566 #else 567 /* Read RAW status */ 568 status = readw(&i2c_base->irqstatus_raw); 569 #endif 570 } while (!(status & 571 (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY | 572 I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK | 573 I2C_STAT_AL)) && timeout--); 574 575 if (timeout <= 0) { 576 printf("Timed out in wait_for_event: status=%04x\n", 577 status); 578 /* 579 * If status is still 0 here, probably the bus pads have 580 * not been configured for I2C, and/or pull-ups are missing. 581 */ 582 printf("Check if pads/pull-ups of bus %d are properly configured\n", 583 adap->hwadapnr); 584 writew(0xFFFF, &i2c_base->stat); 585 status = 0; 586 } 587 588 return status; 589 } 590 591 static struct i2c *omap24_get_base(struct i2c_adapter *adap) 592 { 593 switch (adap->hwadapnr) { 594 case 0: 595 return (struct i2c *)I2C_BASE1; 596 break; 597 case 1: 598 return (struct i2c *)I2C_BASE2; 599 break; 600 #if (I2C_BUS_MAX > 2) 601 case 2: 602 return (struct i2c *)I2C_BASE3; 603 break; 604 #if (I2C_BUS_MAX > 3) 605 case 3: 606 return (struct i2c *)I2C_BASE4; 607 break; 608 #if (I2C_BUS_MAX > 4) 609 case 4: 610 return (struct i2c *)I2C_BASE5; 611 break; 612 #endif 613 #endif 614 #endif 615 default: 616 printf("wrong hwadapnr: %d\n", adap->hwadapnr); 617 break; 618 } 619 return NULL; 620 } 621 622 #if !defined(CONFIG_SYS_OMAP24_I2C_SPEED1) 623 #define CONFIG_SYS_OMAP24_I2C_SPEED1 CONFIG_SYS_OMAP24_I2C_SPEED 624 #endif 625 #if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE1) 626 #define CONFIG_SYS_OMAP24_I2C_SLAVE1 CONFIG_SYS_OMAP24_I2C_SLAVE 627 #endif 628 629 U_BOOT_I2C_ADAP_COMPLETE(omap24_0, omap24_i2c_init, omap24_i2c_probe, 630 omap24_i2c_read, omap24_i2c_write, omap24_i2c_setspeed, 631 CONFIG_SYS_OMAP24_I2C_SPEED, 632 CONFIG_SYS_OMAP24_I2C_SLAVE, 633 0) 634 U_BOOT_I2C_ADAP_COMPLETE(omap24_1, omap24_i2c_init, omap24_i2c_probe, 635 omap24_i2c_read, omap24_i2c_write, omap24_i2c_setspeed, 636 CONFIG_SYS_OMAP24_I2C_SPEED1, 637 CONFIG_SYS_OMAP24_I2C_SLAVE1, 638 1) 639 #if (I2C_BUS_MAX > 2) 640 #if !defined(CONFIG_SYS_OMAP24_I2C_SPEED2) 641 #define CONFIG_SYS_OMAP24_I2C_SPEED2 CONFIG_SYS_OMAP24_I2C_SPEED 642 #endif 643 #if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE2) 644 #define CONFIG_SYS_OMAP24_I2C_SLAVE2 CONFIG_SYS_OMAP24_I2C_SLAVE 645 #endif 646 647 U_BOOT_I2C_ADAP_COMPLETE(omap24_2, omap24_i2c_init, omap24_i2c_probe, 648 omap24_i2c_read, omap24_i2c_write, NULL, 649 CONFIG_SYS_OMAP24_I2C_SPEED2, 650 CONFIG_SYS_OMAP24_I2C_SLAVE2, 651 2) 652 #if (I2C_BUS_MAX > 3) 653 #if !defined(CONFIG_SYS_OMAP24_I2C_SPEED3) 654 #define CONFIG_SYS_OMAP24_I2C_SPEED3 CONFIG_SYS_OMAP24_I2C_SPEED 655 #endif 656 #if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE3) 657 #define CONFIG_SYS_OMAP24_I2C_SLAVE3 CONFIG_SYS_OMAP24_I2C_SLAVE 658 #endif 659 660 U_BOOT_I2C_ADAP_COMPLETE(omap24_3, omap24_i2c_init, omap24_i2c_probe, 661 omap24_i2c_read, omap24_i2c_write, NULL, 662 CONFIG_SYS_OMAP24_I2C_SPEED3, 663 CONFIG_SYS_OMAP24_I2C_SLAVE3, 664 3) 665 #if (I2C_BUS_MAX > 4) 666 #if !defined(CONFIG_SYS_OMAP24_I2C_SPEED4) 667 #define CONFIG_SYS_OMAP24_I2C_SPEED4 CONFIG_SYS_OMAP24_I2C_SPEED 668 #endif 669 #if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE4) 670 #define CONFIG_SYS_OMAP24_I2C_SLAVE4 CONFIG_SYS_OMAP24_I2C_SLAVE 671 #endif 672 673 U_BOOT_I2C_ADAP_COMPLETE(omap24_4, omap24_i2c_init, omap24_i2c_probe, 674 omap24_i2c_read, omap24_i2c_write, NULL, 675 CONFIG_SYS_OMAP24_I2C_SPEED4, 676 CONFIG_SYS_OMAP24_I2C_SLAVE4, 677 4) 678 #endif 679 #endif 680 #endif 681