1 /* 2 * Basic I2C functions 3 * 4 * Copyright (c) 2004 Texas Instruments 5 * 6 * This package is free software; you can redistribute it and/or 7 * modify it under the terms of the license found in the file 8 * named COPYING that should have accompanied this file. 9 * 10 * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR 11 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED 12 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. 13 * 14 * Author: Jian Zhang jzhang@ti.com, Texas Instruments 15 * 16 * Copyright (c) 2003 Wolfgang Denk, wd@denx.de 17 * Rewritten to fit into the current U-Boot framework 18 * 19 * Adapted for OMAP2420 I2C, r-woodruff2@ti.com 20 * 21 */ 22 23 #include <common.h> 24 25 #include <asm/arch/i2c.h> 26 #include <asm/io.h> 27 28 #include "omap24xx_i2c.h" 29 30 DECLARE_GLOBAL_DATA_PTR; 31 32 #define I2C_TIMEOUT 1000 33 34 static void wait_for_bb(void); 35 static u16 wait_for_pin(void); 36 static void flush_fifo(void); 37 38 /* 39 * For SPL boot some boards need i2c before SDRAM is initialised so force 40 * variables to live in SRAM 41 */ 42 static struct i2c __attribute__((section (".data"))) *i2c_base = 43 (struct i2c *)I2C_DEFAULT_BASE; 44 static unsigned int __attribute__((section (".data"))) bus_initialized[I2C_BUS_MAX] = 45 { [0 ... (I2C_BUS_MAX-1)] = 0 }; 46 static unsigned int __attribute__((section (".data"))) current_bus = 0; 47 48 void i2c_init(int speed, int slaveadd) 49 { 50 int psc, fsscll, fssclh; 51 int hsscll = 0, hssclh = 0; 52 u32 scll, sclh; 53 int timeout = I2C_TIMEOUT; 54 55 /* Only handle standard, fast and high speeds */ 56 if ((speed != OMAP_I2C_STANDARD) && 57 (speed != OMAP_I2C_FAST_MODE) && 58 (speed != OMAP_I2C_HIGH_SPEED)) { 59 printf("Error : I2C unsupported speed %d\n", speed); 60 return; 61 } 62 63 psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK; 64 psc -= 1; 65 if (psc < I2C_PSC_MIN) { 66 printf("Error : I2C unsupported prescalar %d\n", psc); 67 return; 68 } 69 70 if (speed == OMAP_I2C_HIGH_SPEED) { 71 /* High speed */ 72 73 /* For first phase of HS mode */ 74 fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK / 75 (2 * OMAP_I2C_FAST_MODE); 76 77 fsscll -= I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM; 78 fssclh -= I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM; 79 if (((fsscll < 0) || (fssclh < 0)) || 80 ((fsscll > 255) || (fssclh > 255))) { 81 puts("Error : I2C initializing first phase clock\n"); 82 return; 83 } 84 85 /* For second phase of HS mode */ 86 hsscll = hssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed); 87 88 hsscll -= I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM; 89 hssclh -= I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM; 90 if (((fsscll < 0) || (fssclh < 0)) || 91 ((fsscll > 255) || (fssclh > 255))) { 92 puts("Error : I2C initializing second phase clock\n"); 93 return; 94 } 95 96 scll = (unsigned int)hsscll << 8 | (unsigned int)fsscll; 97 sclh = (unsigned int)hssclh << 8 | (unsigned int)fssclh; 98 99 } else { 100 /* Standard and fast speed */ 101 fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed); 102 103 fsscll -= I2C_FASTSPEED_SCLL_TRIM; 104 fssclh -= I2C_FASTSPEED_SCLH_TRIM; 105 if (((fsscll < 0) || (fssclh < 0)) || 106 ((fsscll > 255) || (fssclh > 255))) { 107 puts("Error : I2C initializing clock\n"); 108 return; 109 } 110 111 scll = (unsigned int)fsscll; 112 sclh = (unsigned int)fssclh; 113 } 114 115 if (readw(&i2c_base->con) & I2C_CON_EN) { 116 writew(0, &i2c_base->con); 117 udelay(50000); 118 } 119 120 writew(0x2, &i2c_base->sysc); /* for ES2 after soft reset */ 121 udelay(1000); 122 123 writew(I2C_CON_EN, &i2c_base->con); 124 while (!(readw(&i2c_base->syss) & I2C_SYSS_RDONE) && timeout--) { 125 if (timeout <= 0) { 126 puts("ERROR: Timeout in soft-reset\n"); 127 return; 128 } 129 udelay(1000); 130 } 131 132 writew(0, &i2c_base->con); 133 writew(psc, &i2c_base->psc); 134 writew(scll, &i2c_base->scll); 135 writew(sclh, &i2c_base->sclh); 136 137 /* own address */ 138 writew(slaveadd, &i2c_base->oa); 139 writew(I2C_CON_EN, &i2c_base->con); 140 141 /* have to enable intrrupts or OMAP i2c module doesn't work */ 142 writew(I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | 143 I2C_IE_NACK_IE | I2C_IE_AL_IE, &i2c_base->ie); 144 udelay(1000); 145 flush_fifo(); 146 writew(0xFFFF, &i2c_base->stat); 147 writew(0, &i2c_base->cnt); 148 149 if (gd->flags & GD_FLG_RELOC) 150 bus_initialized[current_bus] = 1; 151 } 152 153 static int i2c_read_byte(u8 devaddr, u8 regoffset, u8 *value) 154 { 155 int i2c_error = 0; 156 u16 status; 157 158 /* wait until bus not busy */ 159 wait_for_bb(); 160 161 /* one byte only */ 162 writew(1, &i2c_base->cnt); 163 /* set slave address */ 164 writew(devaddr, &i2c_base->sa); 165 /* no stop bit needed here */ 166 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | 167 I2C_CON_TRX, &i2c_base->con); 168 169 /* send register offset */ 170 while (1) { 171 status = wait_for_pin(); 172 if (status == 0 || status & I2C_STAT_NACK) { 173 i2c_error = 1; 174 goto read_exit; 175 } 176 if (status & I2C_STAT_XRDY) { 177 /* Important: have to use byte access */ 178 writeb(regoffset, &i2c_base->data); 179 writew(I2C_STAT_XRDY, &i2c_base->stat); 180 } 181 if (status & I2C_STAT_ARDY) { 182 writew(I2C_STAT_ARDY, &i2c_base->stat); 183 break; 184 } 185 } 186 187 /* set slave address */ 188 writew(devaddr, &i2c_base->sa); 189 /* read one byte from slave */ 190 writew(1, &i2c_base->cnt); 191 /* need stop bit here */ 192 writew(I2C_CON_EN | I2C_CON_MST | 193 I2C_CON_STT | I2C_CON_STP, 194 &i2c_base->con); 195 196 /* receive data */ 197 while (1) { 198 status = wait_for_pin(); 199 if (status == 0 || status & I2C_STAT_NACK) { 200 i2c_error = 1; 201 goto read_exit; 202 } 203 if (status & I2C_STAT_RRDY) { 204 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \ 205 defined(CONFIG_OMAP44XX) || defined(CONFIG_AM33XX) 206 *value = readb(&i2c_base->data); 207 #else 208 *value = readw(&i2c_base->data); 209 #endif 210 writew(I2C_STAT_RRDY, &i2c_base->stat); 211 } 212 if (status & I2C_STAT_ARDY) { 213 writew(I2C_STAT_ARDY, &i2c_base->stat); 214 break; 215 } 216 } 217 218 read_exit: 219 flush_fifo(); 220 writew(0xFFFF, &i2c_base->stat); 221 writew(0, &i2c_base->cnt); 222 return i2c_error; 223 } 224 225 static void flush_fifo(void) 226 { u16 stat; 227 228 /* note: if you try and read data when its not there or ready 229 * you get a bus error 230 */ 231 while (1) { 232 stat = readw(&i2c_base->stat); 233 if (stat == I2C_STAT_RRDY) { 234 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \ 235 defined(CONFIG_OMAP44XX) || defined(CONFIG_AM33XX) 236 readb(&i2c_base->data); 237 #else 238 readw(&i2c_base->data); 239 #endif 240 writew(I2C_STAT_RRDY, &i2c_base->stat); 241 udelay(1000); 242 } else 243 break; 244 } 245 } 246 247 int i2c_probe(uchar chip) 248 { 249 u16 status; 250 int res = 1; /* default = fail */ 251 252 if (chip == readw(&i2c_base->oa)) 253 return res; 254 255 /* wait until bus not busy */ 256 wait_for_bb(); 257 258 /* try to read one byte */ 259 writew(1, &i2c_base->cnt); 260 /* set slave address */ 261 writew(chip, &i2c_base->sa); 262 /* stop bit needed here */ 263 writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, &i2c_base->con); 264 265 while (1) { 266 status = wait_for_pin(); 267 if (status == 0 || status & I2C_STAT_AL) { 268 res = 1; 269 goto probe_exit; 270 } 271 if (status & I2C_STAT_NACK) { 272 res = 1; 273 writew(0xff, &i2c_base->stat); 274 writew (readw (&i2c_base->con) | I2C_CON_STP, &i2c_base->con); 275 wait_for_bb (); 276 break; 277 } 278 if (status & I2C_STAT_ARDY) { 279 writew(I2C_STAT_ARDY, &i2c_base->stat); 280 break; 281 } 282 if (status & I2C_STAT_RRDY) { 283 res = 0; 284 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \ 285 defined(CONFIG_OMAP44XX) || defined(CONFIG_AM33XX) 286 readb(&i2c_base->data); 287 #else 288 readw(&i2c_base->data); 289 #endif 290 writew(I2C_STAT_RRDY, &i2c_base->stat); 291 } 292 } 293 294 probe_exit: 295 flush_fifo(); 296 /* don't allow any more data in... we don't want it. */ 297 writew(0, &i2c_base->cnt); 298 writew(0xFFFF, &i2c_base->stat); 299 return res; 300 } 301 302 int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) 303 { 304 int i; 305 306 if (alen > 1) { 307 printf("I2C read: addr len %d not supported\n", alen); 308 return 1; 309 } 310 311 if (addr + len > 256) { 312 puts("I2C read: address out of range\n"); 313 return 1; 314 } 315 316 for (i = 0; i < len; i++) { 317 if (i2c_read_byte(chip, addr + i, &buffer[i])) { 318 puts("I2C read: I/O error\n"); 319 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 320 return 1; 321 } 322 } 323 324 return 0; 325 } 326 327 int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) 328 { 329 int i; 330 u16 status; 331 int i2c_error = 0; 332 333 if (alen > 1) { 334 printf("I2C write: addr len %d not supported\n", alen); 335 return 1; 336 } 337 338 if (addr + len > 256) { 339 printf("I2C write: address 0x%x + 0x%x out of range\n", 340 addr, len); 341 return 1; 342 } 343 344 /* wait until bus not busy */ 345 wait_for_bb(); 346 347 /* start address phase - will write regoffset + len bytes data */ 348 /* TODO consider case when !CONFIG_OMAP243X/34XX/44XX */ 349 writew(alen + len, &i2c_base->cnt); 350 /* set slave address */ 351 writew(chip, &i2c_base->sa); 352 /* stop bit needed here */ 353 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | 354 I2C_CON_STP, &i2c_base->con); 355 356 /* Send address byte */ 357 status = wait_for_pin(); 358 359 if (status == 0 || status & I2C_STAT_NACK) { 360 i2c_error = 1; 361 printf("error waiting for i2c address ACK (status=0x%x)\n", 362 status); 363 goto write_exit; 364 } 365 366 if (status & I2C_STAT_XRDY) { 367 writeb(addr & 0xFF, &i2c_base->data); 368 writew(I2C_STAT_XRDY, &i2c_base->stat); 369 } else { 370 i2c_error = 1; 371 printf("i2c bus not ready for transmit (status=0x%x)\n", 372 status); 373 goto write_exit; 374 } 375 376 /* address phase is over, now write data */ 377 for (i = 0; i < len; i++) { 378 status = wait_for_pin(); 379 380 if (status == 0 || status & I2C_STAT_NACK) { 381 i2c_error = 1; 382 printf("i2c error waiting for data ACK (status=0x%x)\n", 383 status); 384 goto write_exit; 385 } 386 387 if (status & I2C_STAT_XRDY) { 388 writeb(buffer[i], &i2c_base->data); 389 writew(I2C_STAT_XRDY, &i2c_base->stat); 390 } else { 391 i2c_error = 1; 392 printf("i2c bus not ready for Tx (i=%d)\n", i); 393 goto write_exit; 394 } 395 } 396 397 write_exit: 398 flush_fifo(); 399 writew(0xFFFF, &i2c_base->stat); 400 return i2c_error; 401 } 402 403 static void wait_for_bb(void) 404 { 405 int timeout = I2C_TIMEOUT; 406 u16 stat; 407 408 writew(0xFFFF, &i2c_base->stat); /* clear current interrupts...*/ 409 while ((stat = readw(&i2c_base->stat) & I2C_STAT_BB) && timeout--) { 410 writew(stat, &i2c_base->stat); 411 udelay(1000); 412 } 413 414 if (timeout <= 0) { 415 printf("timed out in wait_for_bb: I2C_STAT=%x\n", 416 readw(&i2c_base->stat)); 417 } 418 writew(0xFFFF, &i2c_base->stat); /* clear delayed stuff*/ 419 } 420 421 static u16 wait_for_pin(void) 422 { 423 u16 status; 424 int timeout = I2C_TIMEOUT; 425 426 do { 427 udelay(1000); 428 status = readw(&i2c_base->stat); 429 } while (!(status & 430 (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY | 431 I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK | 432 I2C_STAT_AL)) && timeout--); 433 434 if (timeout <= 0) { 435 printf("timed out in wait_for_pin: I2C_STAT=%x\n", 436 readw(&i2c_base->stat)); 437 writew(0xFFFF, &i2c_base->stat); 438 status = 0; 439 } 440 441 return status; 442 } 443 444 int i2c_set_bus_num(unsigned int bus) 445 { 446 if ((bus < 0) || (bus >= I2C_BUS_MAX)) { 447 printf("Bad bus: %d\n", bus); 448 return -1; 449 } 450 451 #if I2C_BUS_MAX == 3 452 if (bus == 2) 453 i2c_base = (struct i2c *)I2C_BASE3; 454 else 455 #endif 456 if (bus == 1) 457 i2c_base = (struct i2c *)I2C_BASE2; 458 else 459 i2c_base = (struct i2c *)I2C_BASE1; 460 461 current_bus = bus; 462 463 if (!bus_initialized[current_bus]) 464 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 465 466 return 0; 467 } 468 469 int i2c_get_bus_num(void) 470 { 471 return (int) current_bus; 472 } 473