1 /* 2 * Basic I2C functions 3 * 4 * Copyright (c) 2004 Texas Instruments 5 * 6 * This package is free software; you can redistribute it and/or 7 * modify it under the terms of the license found in the file 8 * named COPYING that should have accompanied this file. 9 * 10 * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR 11 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED 12 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. 13 * 14 * Author: Jian Zhang jzhang@ti.com, Texas Instruments 15 * 16 * Copyright (c) 2003 Wolfgang Denk, wd@denx.de 17 * Rewritten to fit into the current U-Boot framework 18 * 19 * Adapted for OMAP2420 I2C, r-woodruff2@ti.com 20 * 21 * Copyright (c) 2013 Lubomir Popov <lpopov@mm-sol.com>, MM Solutions 22 * New i2c_read, i2c_write and i2c_probe functions, tested on OMAP4 23 * (4430/60/70), OMAP5 (5430) and AM335X (3359); should work on older 24 * OMAPs and derivatives as well. The only anticipated exception would 25 * be the OMAP2420, which shall require driver modification. 26 * - Rewritten i2c_read to operate correctly with all types of chips 27 * (old function could not read consistent data from some I2C slaves). 28 * - Optimized i2c_write. 29 * - New i2c_probe, performs write access vs read. The old probe could 30 * hang the system under certain conditions (e.g. unconfigured pads). 31 * - The read/write/probe functions try to identify unconfigured bus. 32 * - Status functions now read irqstatus_raw as per TRM guidelines 33 * (except for OMAP243X and OMAP34XX). 34 * - Driver now supports up to I2C5 (OMAP5). 35 * 36 * Copyright (c) 2014 Hannes Schmelzer <oe5hpm@oevsv.at>, B&R 37 * - Added support for set_speed 38 * 39 */ 40 41 #include <common.h> 42 #include <dm.h> 43 #include <i2c.h> 44 45 #include <asm/arch/i2c.h> 46 #include <asm/io.h> 47 48 #include "omap24xx_i2c.h" 49 50 #define I2C_TIMEOUT 1000 51 52 /* Absolutely safe for status update at 100 kHz I2C: */ 53 #define I2C_WAIT 200 54 55 struct omap_i2c { 56 struct udevice *clk; 57 struct i2c *regs; 58 unsigned int speed; 59 int waitdelay; 60 int clk_id; 61 }; 62 63 static int omap24_i2c_findpsc(u32 *pscl, u32 *psch, uint speed) 64 { 65 unsigned long internal_clk = 0, fclk; 66 unsigned int prescaler; 67 68 /* 69 * This method is only called for Standard and Fast Mode speeds 70 * 71 * For some TI SoCs it is explicitly written in TRM (e,g, SPRUHZ6G, 72 * page 5685, Table 24-7) 73 * that the internal I2C clock (after prescaler) should be between 74 * 7-12 MHz (at least for Fast Mode (FS)). 75 * 76 * Such approach is used in v4.9 Linux kernel in: 77 * ./drivers/i2c/busses/i2c-omap.c (omap_i2c_init function). 78 */ 79 80 speed /= 1000; /* convert speed to kHz */ 81 82 if (speed > 100) 83 internal_clk = 9600; 84 else 85 internal_clk = 4000; 86 87 fclk = I2C_IP_CLK / 1000; 88 prescaler = fclk / internal_clk; 89 prescaler = prescaler - 1; 90 91 if (speed > 100) { 92 unsigned long scl; 93 94 /* Fast mode */ 95 scl = internal_clk / speed; 96 *pscl = scl - (scl / 3) - I2C_FASTSPEED_SCLL_TRIM; 97 *psch = (scl / 3) - I2C_FASTSPEED_SCLH_TRIM; 98 } else { 99 /* Standard mode */ 100 *pscl = internal_clk / (speed * 2) - I2C_FASTSPEED_SCLL_TRIM; 101 *psch = internal_clk / (speed * 2) - I2C_FASTSPEED_SCLH_TRIM; 102 } 103 104 debug("%s: speed [kHz]: %d psc: 0x%x sscl: 0x%x ssch: 0x%x\n", 105 __func__, speed, prescaler, *pscl, *psch); 106 107 if (*pscl <= 0 || *psch <= 0 || prescaler <= 0) 108 return -EINVAL; 109 110 return prescaler; 111 } 112 113 /* 114 * Wait for the bus to be free by checking the Bus Busy (BB) 115 * bit to become clear 116 */ 117 static int wait_for_bb(struct i2c *i2c_base, int waitdelay) 118 { 119 int timeout = I2C_TIMEOUT; 120 u16 stat; 121 122 writew(0xFFFF, &i2c_base->stat); /* clear current interrupts...*/ 123 #if defined(CONFIG_OMAP34XX) 124 while ((stat = readw(&i2c_base->stat) & I2C_STAT_BB) && timeout--) { 125 #else 126 /* Read RAW status */ 127 while ((stat = readw(&i2c_base->irqstatus_raw) & 128 I2C_STAT_BB) && timeout--) { 129 #endif 130 writew(stat, &i2c_base->stat); 131 udelay(waitdelay); 132 } 133 134 if (timeout <= 0) { 135 printf("Timed out in wait_for_bb: status=%04x\n", 136 stat); 137 return 1; 138 } 139 writew(0xFFFF, &i2c_base->stat); /* clear delayed stuff*/ 140 return 0; 141 } 142 143 /* 144 * Wait for the I2C controller to complete current action 145 * and update status 146 */ 147 static u16 wait_for_event(struct i2c *i2c_base, int waitdelay) 148 { 149 u16 status; 150 int timeout = I2C_TIMEOUT; 151 152 do { 153 udelay(waitdelay); 154 #if defined(CONFIG_OMAP34XX) 155 status = readw(&i2c_base->stat); 156 #else 157 /* Read RAW status */ 158 status = readw(&i2c_base->irqstatus_raw); 159 #endif 160 } while (!(status & 161 (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY | 162 I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK | 163 I2C_STAT_AL)) && timeout--); 164 165 if (timeout <= 0) { 166 printf("Timed out in wait_for_event: status=%04x\n", 167 status); 168 /* 169 * If status is still 0 here, probably the bus pads have 170 * not been configured for I2C, and/or pull-ups are missing. 171 */ 172 printf("Check if pads/pull-ups of bus are properly configured\n"); 173 writew(0xFFFF, &i2c_base->stat); 174 status = 0; 175 } 176 177 return status; 178 } 179 180 static void flush_fifo(struct i2c *i2c_base) 181 { 182 u16 stat; 183 184 /* 185 * note: if you try and read data when its not there or ready 186 * you get a bus error 187 */ 188 while (1) { 189 stat = readw(&i2c_base->stat); 190 if (stat == I2C_STAT_RRDY) { 191 readb(&i2c_base->data); 192 writew(I2C_STAT_RRDY, &i2c_base->stat); 193 udelay(1000); 194 } else 195 break; 196 } 197 } 198 199 static int __omap24_i2c_setspeed(struct i2c *i2c_base, uint speed, 200 int *waitdelay) 201 { 202 int psc, fsscll = 0, fssclh = 0; 203 int hsscll = 0, hssclh = 0; 204 u32 scll = 0, sclh = 0; 205 206 if (speed >= OMAP_I2C_HIGH_SPEED) { 207 /* High speed */ 208 psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK; 209 psc -= 1; 210 if (psc < I2C_PSC_MIN) { 211 printf("Error : I2C unsupported prescaler %d\n", psc); 212 return -1; 213 } 214 215 /* For first phase of HS mode */ 216 fsscll = I2C_INTERNAL_SAMPLING_CLK / (2 * speed); 217 218 fssclh = fsscll; 219 220 fsscll -= I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM; 221 fssclh -= I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM; 222 if (((fsscll < 0) || (fssclh < 0)) || 223 ((fsscll > 255) || (fssclh > 255))) { 224 puts("Error : I2C initializing first phase clock\n"); 225 return -1; 226 } 227 228 /* For second phase of HS mode */ 229 hsscll = hssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed); 230 231 hsscll -= I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM; 232 hssclh -= I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM; 233 if (((fsscll < 0) || (fssclh < 0)) || 234 ((fsscll > 255) || (fssclh > 255))) { 235 puts("Error : I2C initializing second phase clock\n"); 236 return -1; 237 } 238 239 scll = (unsigned int)hsscll << 8 | (unsigned int)fsscll; 240 sclh = (unsigned int)hssclh << 8 | (unsigned int)fssclh; 241 242 } else { 243 /* Standard and fast speed */ 244 psc = omap24_i2c_findpsc(&scll, &sclh, speed); 245 if (0 > psc) { 246 puts("Error : I2C initializing clock\n"); 247 return -1; 248 } 249 } 250 251 *waitdelay = (10000000 / speed) * 2; /* wait for 20 clkperiods */ 252 writew(0, &i2c_base->con); 253 writew(psc, &i2c_base->psc); 254 writew(scll, &i2c_base->scll); 255 writew(sclh, &i2c_base->sclh); 256 writew(I2C_CON_EN, &i2c_base->con); 257 writew(0xFFFF, &i2c_base->stat); /* clear all pending status */ 258 259 return 0; 260 } 261 262 static void omap24_i2c_deblock(struct i2c *i2c_base) 263 { 264 int i; 265 u16 systest; 266 u16 orgsystest; 267 268 /* set test mode ST_EN = 1 */ 269 orgsystest = readw(&i2c_base->systest); 270 systest = orgsystest; 271 /* enable testmode */ 272 systest |= I2C_SYSTEST_ST_EN; 273 writew(systest, &i2c_base->systest); 274 systest &= ~I2C_SYSTEST_TMODE_MASK; 275 systest |= 3 << I2C_SYSTEST_TMODE_SHIFT; 276 writew(systest, &i2c_base->systest); 277 278 /* set SCL, SDA = 1 */ 279 systest |= I2C_SYSTEST_SCL_O | I2C_SYSTEST_SDA_O; 280 writew(systest, &i2c_base->systest); 281 udelay(10); 282 283 /* toggle scl 9 clocks */ 284 for (i = 0; i < 9; i++) { 285 /* SCL = 0 */ 286 systest &= ~I2C_SYSTEST_SCL_O; 287 writew(systest, &i2c_base->systest); 288 udelay(10); 289 /* SCL = 1 */ 290 systest |= I2C_SYSTEST_SCL_O; 291 writew(systest, &i2c_base->systest); 292 udelay(10); 293 } 294 295 /* send stop */ 296 systest &= ~I2C_SYSTEST_SDA_O; 297 writew(systest, &i2c_base->systest); 298 udelay(10); 299 systest |= I2C_SYSTEST_SCL_O | I2C_SYSTEST_SDA_O; 300 writew(systest, &i2c_base->systest); 301 udelay(10); 302 303 /* restore original mode */ 304 writew(orgsystest, &i2c_base->systest); 305 } 306 307 static void __omap24_i2c_init(struct i2c *i2c_base, int speed, int slaveadd, 308 int *waitdelay) 309 { 310 int timeout = I2C_TIMEOUT; 311 int deblock = 1; 312 313 retry: 314 if (readw(&i2c_base->con) & I2C_CON_EN) { 315 writew(0, &i2c_base->con); 316 udelay(50000); 317 } 318 319 writew(0x2, &i2c_base->sysc); /* for ES2 after soft reset */ 320 udelay(1000); 321 322 writew(I2C_CON_EN, &i2c_base->con); 323 while (!(readw(&i2c_base->syss) & I2C_SYSS_RDONE) && timeout--) { 324 if (timeout <= 0) { 325 puts("ERROR: Timeout in soft-reset\n"); 326 return; 327 } 328 udelay(1000); 329 } 330 331 if (0 != __omap24_i2c_setspeed(i2c_base, speed, waitdelay)) { 332 printf("ERROR: failed to setup I2C bus-speed!\n"); 333 return; 334 } 335 336 /* own address */ 337 writew(slaveadd, &i2c_base->oa); 338 339 #if defined(CONFIG_OMAP34XX) 340 /* 341 * Have to enable interrupts for OMAP2/3, these IPs don't have 342 * an 'irqstatus_raw' register and we shall have to poll 'stat' 343 */ 344 writew(I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | 345 I2C_IE_NACK_IE | I2C_IE_AL_IE, &i2c_base->ie); 346 #endif 347 udelay(1000); 348 flush_fifo(i2c_base); 349 writew(0xFFFF, &i2c_base->stat); 350 351 /* Handle possible failed I2C state */ 352 if (wait_for_bb(i2c_base, *waitdelay)) 353 if (deblock == 1) { 354 omap24_i2c_deblock(i2c_base); 355 deblock = 0; 356 goto retry; 357 } 358 } 359 360 /* 361 * i2c_probe: Use write access. Allows to identify addresses that are 362 * write-only (like the config register of dual-port EEPROMs) 363 */ 364 static int __omap24_i2c_probe(struct i2c *i2c_base, int waitdelay, uchar chip) 365 { 366 u16 status; 367 int res = 1; /* default = fail */ 368 369 if (chip == readw(&i2c_base->oa)) 370 return res; 371 372 /* Wait until bus is free */ 373 if (wait_for_bb(i2c_base, waitdelay)) 374 return res; 375 376 /* No data transfer, slave addr only */ 377 writew(chip, &i2c_base->sa); 378 /* Stop bit needed here */ 379 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | 380 I2C_CON_STP, &i2c_base->con); 381 382 status = wait_for_event(i2c_base, waitdelay); 383 384 if ((status & ~I2C_STAT_XRDY) == 0 || (status & I2C_STAT_AL)) { 385 /* 386 * With current high-level command implementation, notifying 387 * the user shall flood the console with 127 messages. If 388 * silent exit is desired upon unconfigured bus, remove the 389 * following 'if' section: 390 */ 391 if (status == I2C_STAT_XRDY) 392 printf("i2c_probe: pads on bus probably not configured (status=0x%x)\n", 393 status); 394 395 goto pr_exit; 396 } 397 398 /* Check for ACK (!NAK) */ 399 if (!(status & I2C_STAT_NACK)) { 400 res = 0; /* Device found */ 401 udelay(waitdelay);/* Required by AM335X in SPL */ 402 /* Abort transfer (force idle state) */ 403 writew(I2C_CON_MST | I2C_CON_TRX, &i2c_base->con); /* Reset */ 404 udelay(1000); 405 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_TRX | 406 I2C_CON_STP, &i2c_base->con); /* STP */ 407 } 408 pr_exit: 409 flush_fifo(i2c_base); 410 writew(0xFFFF, &i2c_base->stat); 411 return res; 412 } 413 414 /* 415 * i2c_read: Function now uses a single I2C read transaction with bulk transfer 416 * of the requested number of bytes (note that the 'i2c md' command 417 * limits this to 16 bytes anyway). If CONFIG_I2C_REPEATED_START is 418 * defined in the board config header, this transaction shall be with 419 * Repeated Start (Sr) between the address and data phases; otherwise 420 * Stop-Start (P-S) shall be used (some I2C chips do require a P-S). 421 * The address (reg offset) may be 0, 1 or 2 bytes long. 422 * Function now reads correctly from chips that return more than one 423 * byte of data per addressed register (like TI temperature sensors), 424 * or that do not need a register address at all (such as some clock 425 * distributors). 426 */ 427 static int __omap24_i2c_read(struct i2c *i2c_base, int waitdelay, uchar chip, 428 uint addr, int alen, uchar *buffer, int len) 429 { 430 int i2c_error = 0; 431 u16 status; 432 433 if (alen < 0) { 434 puts("I2C read: addr len < 0\n"); 435 return 1; 436 } 437 if (len < 0) { 438 puts("I2C read: data len < 0\n"); 439 return 1; 440 } 441 if (buffer == NULL) { 442 puts("I2C read: NULL pointer passed\n"); 443 return 1; 444 } 445 446 if (alen > 2) { 447 printf("I2C read: addr len %d not supported\n", alen); 448 return 1; 449 } 450 451 if (addr + len > (1 << 16)) { 452 puts("I2C read: address out of range\n"); 453 return 1; 454 } 455 456 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 457 /* 458 * EEPROM chips that implement "address overflow" are ones 459 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of 460 * address and the extra bits end up in the "chip address" 461 * bit slots. This makes a 24WC08 (1Kbyte) chip look like 462 * four 256 byte chips. 463 * 464 * Note that we consider the length of the address field to 465 * still be one byte because the extra address bits are 466 * hidden in the chip address. 467 */ 468 if (alen > 0) 469 chip |= ((addr >> (alen * 8)) & 470 CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); 471 #endif 472 473 /* Wait until bus not busy */ 474 if (wait_for_bb(i2c_base, waitdelay)) 475 return 1; 476 477 /* Zero, one or two bytes reg address (offset) */ 478 writew(alen, &i2c_base->cnt); 479 /* Set slave address */ 480 writew(chip, &i2c_base->sa); 481 482 if (alen) { 483 /* Must write reg offset first */ 484 #ifdef CONFIG_I2C_REPEATED_START 485 /* No stop bit, use Repeated Start (Sr) */ 486 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | 487 I2C_CON_TRX, &i2c_base->con); 488 #else 489 /* Stop - Start (P-S) */ 490 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP | 491 I2C_CON_TRX, &i2c_base->con); 492 #endif 493 /* Send register offset */ 494 while (1) { 495 status = wait_for_event(i2c_base, waitdelay); 496 /* Try to identify bus that is not padconf'd for I2C */ 497 if (status == I2C_STAT_XRDY) { 498 i2c_error = 2; 499 printf("i2c_read (addr phase): pads on bus probably not configured (status=0x%x)\n", 500 status); 501 goto rd_exit; 502 } 503 if (status == 0 || (status & I2C_STAT_NACK)) { 504 i2c_error = 1; 505 printf("i2c_read: error waiting for addr ACK (status=0x%x)\n", 506 status); 507 goto rd_exit; 508 } 509 if (alen) { 510 if (status & I2C_STAT_XRDY) { 511 alen--; 512 /* Do we have to use byte access? */ 513 writeb((addr >> (8 * alen)) & 0xff, 514 &i2c_base->data); 515 writew(I2C_STAT_XRDY, &i2c_base->stat); 516 } 517 } 518 if (status & I2C_STAT_ARDY) { 519 writew(I2C_STAT_ARDY, &i2c_base->stat); 520 break; 521 } 522 } 523 } 524 /* Set slave address */ 525 writew(chip, &i2c_base->sa); 526 /* Read len bytes from slave */ 527 writew(len, &i2c_base->cnt); 528 /* Need stop bit here */ 529 writew(I2C_CON_EN | I2C_CON_MST | 530 I2C_CON_STT | I2C_CON_STP, 531 &i2c_base->con); 532 533 /* Receive data */ 534 while (1) { 535 status = wait_for_event(i2c_base, waitdelay); 536 /* 537 * Try to identify bus that is not padconf'd for I2C. This 538 * state could be left over from previous transactions if 539 * the address phase is skipped due to alen=0. 540 */ 541 if (status == I2C_STAT_XRDY) { 542 i2c_error = 2; 543 printf("i2c_read (data phase): pads on bus probably not configured (status=0x%x)\n", 544 status); 545 goto rd_exit; 546 } 547 if (status == 0 || (status & I2C_STAT_NACK)) { 548 i2c_error = 1; 549 goto rd_exit; 550 } 551 if (status & I2C_STAT_RRDY) { 552 *buffer++ = readb(&i2c_base->data); 553 writew(I2C_STAT_RRDY, &i2c_base->stat); 554 } 555 if (status & I2C_STAT_ARDY) { 556 writew(I2C_STAT_ARDY, &i2c_base->stat); 557 break; 558 } 559 } 560 561 rd_exit: 562 flush_fifo(i2c_base); 563 writew(0xFFFF, &i2c_base->stat); 564 return i2c_error; 565 } 566 567 /* i2c_write: Address (reg offset) may be 0, 1 or 2 bytes long. */ 568 static int __omap24_i2c_write(struct i2c *i2c_base, int waitdelay, uchar chip, 569 uint addr, int alen, uchar *buffer, int len) 570 { 571 int i; 572 u16 status; 573 int i2c_error = 0; 574 int timeout = I2C_TIMEOUT; 575 576 if (alen < 0) { 577 puts("I2C write: addr len < 0\n"); 578 return 1; 579 } 580 581 if (len < 0) { 582 puts("I2C write: data len < 0\n"); 583 return 1; 584 } 585 586 if (buffer == NULL) { 587 puts("I2C write: NULL pointer passed\n"); 588 return 1; 589 } 590 591 if (alen > 2) { 592 printf("I2C write: addr len %d not supported\n", alen); 593 return 1; 594 } 595 596 if (addr + len > (1 << 16)) { 597 printf("I2C write: address 0x%x + 0x%x out of range\n", 598 addr, len); 599 return 1; 600 } 601 602 #ifdef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW 603 /* 604 * EEPROM chips that implement "address overflow" are ones 605 * like Catalyst 24WC04/08/16 which has 9/10/11 bits of 606 * address and the extra bits end up in the "chip address" 607 * bit slots. This makes a 24WC08 (1Kbyte) chip look like 608 * four 256 byte chips. 609 * 610 * Note that we consider the length of the address field to 611 * still be one byte because the extra address bits are 612 * hidden in the chip address. 613 */ 614 if (alen > 0) 615 chip |= ((addr >> (alen * 8)) & 616 CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW); 617 #endif 618 619 /* Wait until bus not busy */ 620 if (wait_for_bb(i2c_base, waitdelay)) 621 return 1; 622 623 /* Start address phase - will write regoffset + len bytes data */ 624 writew(alen + len, &i2c_base->cnt); 625 /* Set slave address */ 626 writew(chip, &i2c_base->sa); 627 /* Stop bit needed here */ 628 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | 629 I2C_CON_STP, &i2c_base->con); 630 631 while (alen) { 632 /* Must write reg offset (one or two bytes) */ 633 status = wait_for_event(i2c_base, waitdelay); 634 /* Try to identify bus that is not padconf'd for I2C */ 635 if (status == I2C_STAT_XRDY) { 636 i2c_error = 2; 637 printf("i2c_write: pads on bus probably not configured (status=0x%x)\n", 638 status); 639 goto wr_exit; 640 } 641 if (status == 0 || (status & I2C_STAT_NACK)) { 642 i2c_error = 1; 643 printf("i2c_write: error waiting for addr ACK (status=0x%x)\n", 644 status); 645 goto wr_exit; 646 } 647 if (status & I2C_STAT_XRDY) { 648 alen--; 649 writeb((addr >> (8 * alen)) & 0xff, &i2c_base->data); 650 writew(I2C_STAT_XRDY, &i2c_base->stat); 651 } else { 652 i2c_error = 1; 653 printf("i2c_write: bus not ready for addr Tx (status=0x%x)\n", 654 status); 655 goto wr_exit; 656 } 657 } 658 /* Address phase is over, now write data */ 659 for (i = 0; i < len; i++) { 660 status = wait_for_event(i2c_base, waitdelay); 661 if (status == 0 || (status & I2C_STAT_NACK)) { 662 i2c_error = 1; 663 printf("i2c_write: error waiting for data ACK (status=0x%x)\n", 664 status); 665 goto wr_exit; 666 } 667 if (status & I2C_STAT_XRDY) { 668 writeb(buffer[i], &i2c_base->data); 669 writew(I2C_STAT_XRDY, &i2c_base->stat); 670 } else { 671 i2c_error = 1; 672 printf("i2c_write: bus not ready for data Tx (i=%d)\n", 673 i); 674 goto wr_exit; 675 } 676 } 677 /* 678 * poll ARDY bit for making sure that last byte really has been 679 * transferred on the bus. 680 */ 681 do { 682 status = wait_for_event(i2c_base, waitdelay); 683 } while (!(status & I2C_STAT_ARDY) && timeout--); 684 if (timeout <= 0) 685 printf("i2c_write: timed out writig last byte!\n"); 686 687 wr_exit: 688 flush_fifo(i2c_base); 689 writew(0xFFFF, &i2c_base->stat); 690 return i2c_error; 691 } 692 693 #ifndef CONFIG_DM_I2C 694 /* 695 * The legacy I2C functions. These need to get removed once 696 * all users of this driver are converted to DM. 697 */ 698 static struct i2c *omap24_get_base(struct i2c_adapter *adap) 699 { 700 switch (adap->hwadapnr) { 701 case 0: 702 return (struct i2c *)I2C_BASE1; 703 break; 704 case 1: 705 return (struct i2c *)I2C_BASE2; 706 break; 707 #if (CONFIG_SYS_I2C_BUS_MAX > 2) 708 case 2: 709 return (struct i2c *)I2C_BASE3; 710 break; 711 #if (CONFIG_SYS_I2C_BUS_MAX > 3) 712 case 3: 713 return (struct i2c *)I2C_BASE4; 714 break; 715 #if (CONFIG_SYS_I2C_BUS_MAX > 4) 716 case 4: 717 return (struct i2c *)I2C_BASE5; 718 break; 719 #endif 720 #endif 721 #endif 722 default: 723 printf("wrong hwadapnr: %d\n", adap->hwadapnr); 724 break; 725 } 726 return NULL; 727 } 728 729 730 static int omap24_i2c_read(struct i2c_adapter *adap, uchar chip, uint addr, 731 int alen, uchar *buffer, int len) 732 { 733 struct i2c *i2c_base = omap24_get_base(adap); 734 735 return __omap24_i2c_read(i2c_base, adap->waitdelay, chip, addr, 736 alen, buffer, len); 737 } 738 739 740 static int omap24_i2c_write(struct i2c_adapter *adap, uchar chip, uint addr, 741 int alen, uchar *buffer, int len) 742 { 743 struct i2c *i2c_base = omap24_get_base(adap); 744 745 return __omap24_i2c_write(i2c_base, adap->waitdelay, chip, addr, 746 alen, buffer, len); 747 } 748 749 static uint omap24_i2c_setspeed(struct i2c_adapter *adap, uint speed) 750 { 751 struct i2c *i2c_base = omap24_get_base(adap); 752 int ret; 753 754 ret = __omap24_i2c_setspeed(i2c_base, speed, &adap->waitdelay); 755 if (ret) { 756 pr_err("%s: set i2c speed failed\n", __func__); 757 return ret; 758 } 759 760 adap->speed = speed; 761 762 return 0; 763 } 764 765 static void omap24_i2c_init(struct i2c_adapter *adap, int speed, int slaveadd) 766 { 767 struct i2c *i2c_base = omap24_get_base(adap); 768 769 return __omap24_i2c_init(i2c_base, speed, slaveadd, &adap->waitdelay); 770 } 771 772 static int omap24_i2c_probe(struct i2c_adapter *adap, uchar chip) 773 { 774 struct i2c *i2c_base = omap24_get_base(adap); 775 776 return __omap24_i2c_probe(i2c_base, adap->waitdelay, chip); 777 } 778 779 #if !defined(CONFIG_SYS_OMAP24_I2C_SPEED1) 780 #define CONFIG_SYS_OMAP24_I2C_SPEED1 CONFIG_SYS_OMAP24_I2C_SPEED 781 #endif 782 #if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE1) 783 #define CONFIG_SYS_OMAP24_I2C_SLAVE1 CONFIG_SYS_OMAP24_I2C_SLAVE 784 #endif 785 786 U_BOOT_I2C_ADAP_COMPLETE(omap24_0, omap24_i2c_init, omap24_i2c_probe, 787 omap24_i2c_read, omap24_i2c_write, omap24_i2c_setspeed, 788 CONFIG_SYS_OMAP24_I2C_SPEED, 789 CONFIG_SYS_OMAP24_I2C_SLAVE, 790 0) 791 U_BOOT_I2C_ADAP_COMPLETE(omap24_1, omap24_i2c_init, omap24_i2c_probe, 792 omap24_i2c_read, omap24_i2c_write, omap24_i2c_setspeed, 793 CONFIG_SYS_OMAP24_I2C_SPEED1, 794 CONFIG_SYS_OMAP24_I2C_SLAVE1, 795 1) 796 #if (CONFIG_SYS_I2C_BUS_MAX > 2) 797 #if !defined(CONFIG_SYS_OMAP24_I2C_SPEED2) 798 #define CONFIG_SYS_OMAP24_I2C_SPEED2 CONFIG_SYS_OMAP24_I2C_SPEED 799 #endif 800 #if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE2) 801 #define CONFIG_SYS_OMAP24_I2C_SLAVE2 CONFIG_SYS_OMAP24_I2C_SLAVE 802 #endif 803 804 U_BOOT_I2C_ADAP_COMPLETE(omap24_2, omap24_i2c_init, omap24_i2c_probe, 805 omap24_i2c_read, omap24_i2c_write, NULL, 806 CONFIG_SYS_OMAP24_I2C_SPEED2, 807 CONFIG_SYS_OMAP24_I2C_SLAVE2, 808 2) 809 #if (CONFIG_SYS_I2C_BUS_MAX > 3) 810 #if !defined(CONFIG_SYS_OMAP24_I2C_SPEED3) 811 #define CONFIG_SYS_OMAP24_I2C_SPEED3 CONFIG_SYS_OMAP24_I2C_SPEED 812 #endif 813 #if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE3) 814 #define CONFIG_SYS_OMAP24_I2C_SLAVE3 CONFIG_SYS_OMAP24_I2C_SLAVE 815 #endif 816 817 U_BOOT_I2C_ADAP_COMPLETE(omap24_3, omap24_i2c_init, omap24_i2c_probe, 818 omap24_i2c_read, omap24_i2c_write, NULL, 819 CONFIG_SYS_OMAP24_I2C_SPEED3, 820 CONFIG_SYS_OMAP24_I2C_SLAVE3, 821 3) 822 #if (CONFIG_SYS_I2C_BUS_MAX > 4) 823 #if !defined(CONFIG_SYS_OMAP24_I2C_SPEED4) 824 #define CONFIG_SYS_OMAP24_I2C_SPEED4 CONFIG_SYS_OMAP24_I2C_SPEED 825 #endif 826 #if !defined(CONFIG_SYS_OMAP24_I2C_SLAVE4) 827 #define CONFIG_SYS_OMAP24_I2C_SLAVE4 CONFIG_SYS_OMAP24_I2C_SLAVE 828 #endif 829 830 U_BOOT_I2C_ADAP_COMPLETE(omap24_4, omap24_i2c_init, omap24_i2c_probe, 831 omap24_i2c_read, omap24_i2c_write, NULL, 832 CONFIG_SYS_OMAP24_I2C_SPEED4, 833 CONFIG_SYS_OMAP24_I2C_SLAVE4, 834 4) 835 #endif 836 #endif 837 #endif 838 839 #else /* CONFIG_DM_I2C */ 840 841 static int omap_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs) 842 { 843 struct omap_i2c *priv = dev_get_priv(bus); 844 int ret; 845 846 debug("i2c_xfer: %d messages\n", nmsgs); 847 for (; nmsgs > 0; nmsgs--, msg++) { 848 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len); 849 if (msg->flags & I2C_M_RD) { 850 ret = __omap24_i2c_read(priv->regs, priv->waitdelay, 851 msg->addr, 0, 0, msg->buf, 852 msg->len); 853 } else { 854 ret = __omap24_i2c_write(priv->regs, priv->waitdelay, 855 msg->addr, 0, 0, msg->buf, 856 msg->len); 857 } 858 if (ret) { 859 debug("i2c_write: error sending\n"); 860 return -EREMOTEIO; 861 } 862 } 863 864 return 0; 865 } 866 867 static int omap_i2c_set_bus_speed(struct udevice *bus, unsigned int speed) 868 { 869 struct omap_i2c *priv = dev_get_priv(bus); 870 871 priv->speed = speed; 872 873 return __omap24_i2c_setspeed(priv->regs, speed, &priv->waitdelay); 874 } 875 876 static int omap_i2c_probe_chip(struct udevice *bus, uint chip_addr, 877 uint chip_flags) 878 { 879 struct omap_i2c *priv = dev_get_priv(bus); 880 881 return __omap24_i2c_probe(priv->regs, priv->waitdelay, chip_addr); 882 } 883 884 static int omap_i2c_probe(struct udevice *bus) 885 { 886 struct omap_i2c *priv = dev_get_priv(bus); 887 888 __omap24_i2c_init(priv->regs, priv->speed, 0, &priv->waitdelay); 889 890 return 0; 891 } 892 893 static int omap_i2c_ofdata_to_platdata(struct udevice *bus) 894 { 895 struct omap_i2c *priv = dev_get_priv(bus); 896 897 priv->regs = map_physmem(devfdt_get_addr(bus), sizeof(void *), 898 MAP_NOCACHE); 899 priv->speed = CONFIG_SYS_OMAP24_I2C_SPEED; 900 901 return 0; 902 } 903 904 static const struct dm_i2c_ops omap_i2c_ops = { 905 .xfer = omap_i2c_xfer, 906 .probe_chip = omap_i2c_probe_chip, 907 .set_bus_speed = omap_i2c_set_bus_speed, 908 }; 909 910 static const struct udevice_id omap_i2c_ids[] = { 911 { .compatible = "ti,omap3-i2c" }, 912 { .compatible = "ti,omap4-i2c" }, 913 { } 914 }; 915 916 U_BOOT_DRIVER(i2c_omap) = { 917 .name = "i2c_omap", 918 .id = UCLASS_I2C, 919 .of_match = omap_i2c_ids, 920 .ofdata_to_platdata = omap_i2c_ofdata_to_platdata, 921 .probe = omap_i2c_probe, 922 .priv_auto_alloc_size = sizeof(struct omap_i2c), 923 .ops = &omap_i2c_ops, 924 .flags = DM_FLAG_PRE_RELOC, 925 }; 926 927 #endif /* CONFIG_DM_I2C */ 928