1 /* 2 * Basic I2C functions 3 * 4 * Copyright (c) 2004 Texas Instruments 5 * 6 * This package is free software; you can redistribute it and/or 7 * modify it under the terms of the license found in the file 8 * named COPYING that should have accompanied this file. 9 * 10 * THIS PACKAGE IS PROVIDED ``AS IS'' AND WITHOUT ANY EXPRESS OR 11 * IMPLIED WARRANTIES, INCLUDING, WITHOUT LIMITATION, THE IMPLIED 12 * WARRANTIES OF MERCHANTIBILITY AND FITNESS FOR A PARTICULAR PURPOSE. 13 * 14 * Author: Jian Zhang jzhang@ti.com, Texas Instruments 15 * 16 * Copyright (c) 2003 Wolfgang Denk, wd@denx.de 17 * Rewritten to fit into the current U-Boot framework 18 * 19 * Adapted for OMAP2420 I2C, r-woodruff2@ti.com 20 * 21 */ 22 23 #include <common.h> 24 25 #include <asm/arch/i2c.h> 26 #include <asm/io.h> 27 28 #include "omap24xx_i2c.h" 29 30 DECLARE_GLOBAL_DATA_PTR; 31 32 #define I2C_TIMEOUT 1000 33 34 static void wait_for_bb(void); 35 static u16 wait_for_pin(void); 36 static void flush_fifo(void); 37 38 /* 39 * For SPL boot some boards need i2c before SDRAM is initialised so force 40 * variables to live in SRAM 41 */ 42 static struct i2c __attribute__((section (".data"))) *i2c_base = 43 (struct i2c *)I2C_DEFAULT_BASE; 44 static unsigned int __attribute__((section (".data"))) bus_initialized[I2C_BUS_MAX] = 45 { [0 ... (I2C_BUS_MAX-1)] = 0 }; 46 static unsigned int __attribute__((section (".data"))) current_bus = 0; 47 48 void i2c_init(int speed, int slaveadd) 49 { 50 int psc, fsscll, fssclh; 51 int hsscll = 0, hssclh = 0; 52 u32 scll, sclh; 53 int timeout = I2C_TIMEOUT; 54 55 /* Only handle standard, fast and high speeds */ 56 if ((speed != OMAP_I2C_STANDARD) && 57 (speed != OMAP_I2C_FAST_MODE) && 58 (speed != OMAP_I2C_HIGH_SPEED)) { 59 printf("Error : I2C unsupported speed %d\n", speed); 60 return; 61 } 62 63 psc = I2C_IP_CLK / I2C_INTERNAL_SAMPLING_CLK; 64 psc -= 1; 65 if (psc < I2C_PSC_MIN) { 66 printf("Error : I2C unsupported prescalar %d\n", psc); 67 return; 68 } 69 70 if (speed == OMAP_I2C_HIGH_SPEED) { 71 /* High speed */ 72 73 /* For first phase of HS mode */ 74 fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK / 75 (2 * OMAP_I2C_FAST_MODE); 76 77 fsscll -= I2C_HIGHSPEED_PHASE_ONE_SCLL_TRIM; 78 fssclh -= I2C_HIGHSPEED_PHASE_ONE_SCLH_TRIM; 79 if (((fsscll < 0) || (fssclh < 0)) || 80 ((fsscll > 255) || (fssclh > 255))) { 81 puts("Error : I2C initializing first phase clock\n"); 82 return; 83 } 84 85 /* For second phase of HS mode */ 86 hsscll = hssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed); 87 88 hsscll -= I2C_HIGHSPEED_PHASE_TWO_SCLL_TRIM; 89 hssclh -= I2C_HIGHSPEED_PHASE_TWO_SCLH_TRIM; 90 if (((fsscll < 0) || (fssclh < 0)) || 91 ((fsscll > 255) || (fssclh > 255))) { 92 puts("Error : I2C initializing second phase clock\n"); 93 return; 94 } 95 96 scll = (unsigned int)hsscll << 8 | (unsigned int)fsscll; 97 sclh = (unsigned int)hssclh << 8 | (unsigned int)fssclh; 98 99 } else { 100 /* Standard and fast speed */ 101 fsscll = fssclh = I2C_INTERNAL_SAMPLING_CLK / (2 * speed); 102 103 fsscll -= I2C_FASTSPEED_SCLL_TRIM; 104 fssclh -= I2C_FASTSPEED_SCLH_TRIM; 105 if (((fsscll < 0) || (fssclh < 0)) || 106 ((fsscll > 255) || (fssclh > 255))) { 107 puts("Error : I2C initializing clock\n"); 108 return; 109 } 110 111 scll = (unsigned int)fsscll; 112 sclh = (unsigned int)fssclh; 113 } 114 115 if (readw(&i2c_base->con) & I2C_CON_EN) { 116 writew(0, &i2c_base->con); 117 udelay(50000); 118 } 119 120 writew(0x2, &i2c_base->sysc); /* for ES2 after soft reset */ 121 udelay(1000); 122 123 writew(I2C_CON_EN, &i2c_base->con); 124 while (!(readw(&i2c_base->syss) & I2C_SYSS_RDONE) && timeout--) { 125 if (timeout <= 0) { 126 puts("ERROR: Timeout in soft-reset\n"); 127 return; 128 } 129 udelay(1000); 130 } 131 132 writew(0, &i2c_base->con); 133 writew(psc, &i2c_base->psc); 134 writew(scll, &i2c_base->scll); 135 writew(sclh, &i2c_base->sclh); 136 137 /* own address */ 138 writew(slaveadd, &i2c_base->oa); 139 writew(I2C_CON_EN, &i2c_base->con); 140 141 /* have to enable intrrupts or OMAP i2c module doesn't work */ 142 writew(I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | 143 I2C_IE_NACK_IE | I2C_IE_AL_IE, &i2c_base->ie); 144 udelay(1000); 145 flush_fifo(); 146 writew(0xFFFF, &i2c_base->stat); 147 writew(0, &i2c_base->cnt); 148 149 if (gd->flags & GD_FLG_RELOC) 150 bus_initialized[current_bus] = 1; 151 } 152 153 static int i2c_read_byte(u8 devaddr, u16 regoffset, u8 alen, u8 *value) 154 { 155 int i2c_error = 0; 156 u16 status; 157 int i = 2 - alen; 158 u8 tmpbuf[2] = {(regoffset) >> 8, regoffset & 0xff}; 159 u16 w; 160 161 /* wait until bus not busy */ 162 wait_for_bb(); 163 164 /* one byte only */ 165 writew(alen, &i2c_base->cnt); 166 /* set slave address */ 167 writew(devaddr, &i2c_base->sa); 168 /* no stop bit needed here */ 169 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | 170 I2C_CON_TRX, &i2c_base->con); 171 172 /* send register offset */ 173 while (1) { 174 status = wait_for_pin(); 175 if (status == 0 || status & I2C_STAT_NACK) { 176 i2c_error = 1; 177 goto read_exit; 178 } 179 if (status & I2C_STAT_XRDY) { 180 w = tmpbuf[i++]; 181 #if !(defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \ 182 defined(CONFIG_OMAP44XX) || defined(CONFIG_AM33XX)) 183 w |= tmpbuf[i++] << 8; 184 #endif 185 writew(w, &i2c_base->data); 186 writew(I2C_STAT_XRDY, &i2c_base->stat); 187 } 188 if (status & I2C_STAT_ARDY) { 189 writew(I2C_STAT_ARDY, &i2c_base->stat); 190 break; 191 } 192 } 193 194 /* set slave address */ 195 writew(devaddr, &i2c_base->sa); 196 /* read one byte from slave */ 197 writew(1, &i2c_base->cnt); 198 /* need stop bit here */ 199 writew(I2C_CON_EN | I2C_CON_MST | 200 I2C_CON_STT | I2C_CON_STP, 201 &i2c_base->con); 202 203 /* receive data */ 204 while (1) { 205 status = wait_for_pin(); 206 if (status == 0 || status & I2C_STAT_NACK) { 207 i2c_error = 1; 208 goto read_exit; 209 } 210 if (status & I2C_STAT_RRDY) { 211 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \ 212 defined(CONFIG_OMAP44XX) || defined(CONFIG_AM33XX) 213 *value = readb(&i2c_base->data); 214 #else 215 *value = readw(&i2c_base->data); 216 #endif 217 writew(I2C_STAT_RRDY, &i2c_base->stat); 218 } 219 if (status & I2C_STAT_ARDY) { 220 writew(I2C_STAT_ARDY, &i2c_base->stat); 221 break; 222 } 223 } 224 225 read_exit: 226 flush_fifo(); 227 writew(0xFFFF, &i2c_base->stat); 228 writew(0, &i2c_base->cnt); 229 return i2c_error; 230 } 231 232 static void flush_fifo(void) 233 { u16 stat; 234 235 /* note: if you try and read data when its not there or ready 236 * you get a bus error 237 */ 238 while (1) { 239 stat = readw(&i2c_base->stat); 240 if (stat == I2C_STAT_RRDY) { 241 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \ 242 defined(CONFIG_OMAP44XX) || defined(CONFIG_AM33XX) 243 readb(&i2c_base->data); 244 #else 245 readw(&i2c_base->data); 246 #endif 247 writew(I2C_STAT_RRDY, &i2c_base->stat); 248 udelay(1000); 249 } else 250 break; 251 } 252 } 253 254 int i2c_probe(uchar chip) 255 { 256 u16 status; 257 int res = 1; /* default = fail */ 258 259 if (chip == readw(&i2c_base->oa)) 260 return res; 261 262 /* wait until bus not busy */ 263 wait_for_bb(); 264 265 /* try to read one byte */ 266 writew(1, &i2c_base->cnt); 267 /* set slave address */ 268 writew(chip, &i2c_base->sa); 269 /* stop bit needed here */ 270 writew (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, &i2c_base->con); 271 272 while (1) { 273 status = wait_for_pin(); 274 if (status == 0 || status & I2C_STAT_AL) { 275 res = 1; 276 goto probe_exit; 277 } 278 if (status & I2C_STAT_NACK) { 279 res = 1; 280 writew(0xff, &i2c_base->stat); 281 writew (readw (&i2c_base->con) | I2C_CON_STP, &i2c_base->con); 282 wait_for_bb (); 283 break; 284 } 285 if (status & I2C_STAT_ARDY) { 286 writew(I2C_STAT_ARDY, &i2c_base->stat); 287 break; 288 } 289 if (status & I2C_STAT_RRDY) { 290 res = 0; 291 #if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \ 292 defined(CONFIG_OMAP44XX) || defined(CONFIG_AM33XX) 293 readb(&i2c_base->data); 294 #else 295 readw(&i2c_base->data); 296 #endif 297 writew(I2C_STAT_RRDY, &i2c_base->stat); 298 } 299 } 300 301 probe_exit: 302 flush_fifo(); 303 /* don't allow any more data in... we don't want it. */ 304 writew(0, &i2c_base->cnt); 305 writew(0xFFFF, &i2c_base->stat); 306 return res; 307 } 308 309 int i2c_read(uchar chip, uint addr, int alen, uchar *buffer, int len) 310 { 311 int i; 312 313 if (alen > 2) { 314 printf("I2C read: addr len %d not supported\n", alen); 315 return 1; 316 } 317 318 if (addr + len > (1 << 16)) { 319 puts("I2C read: address out of range\n"); 320 return 1; 321 } 322 323 for (i = 0; i < len; i++) { 324 if (i2c_read_byte(chip, addr + i, alen, &buffer[i])) { 325 puts("I2C read: I/O error\n"); 326 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 327 return 1; 328 } 329 } 330 331 return 0; 332 } 333 334 int i2c_write(uchar chip, uint addr, int alen, uchar *buffer, int len) 335 { 336 int i; 337 u16 status; 338 int i2c_error = 0; 339 u16 w; 340 u8 tmpbuf[2] = {addr >> 8, addr & 0xff}; 341 342 if (alen > 2) { 343 printf("I2C write: addr len %d not supported\n", alen); 344 return 1; 345 } 346 347 if (addr + len > (1 << 16)) { 348 printf("I2C write: address 0x%x + 0x%x out of range\n", 349 addr, len); 350 return 1; 351 } 352 353 /* wait until bus not busy */ 354 wait_for_bb(); 355 356 /* start address phase - will write regoffset + len bytes data */ 357 /* TODO consider case when !CONFIG_OMAP243X/34XX/44XX */ 358 writew(alen + len, &i2c_base->cnt); 359 /* set slave address */ 360 writew(chip, &i2c_base->sa); 361 /* stop bit needed here */ 362 writew(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | 363 I2C_CON_STP, &i2c_base->con); 364 365 /* Send address and data */ 366 for (i = -alen; i < len; i++) { 367 status = wait_for_pin(); 368 369 if (status == 0 || status & I2C_STAT_NACK) { 370 i2c_error = 1; 371 printf("i2c error waiting for data ACK (status=0x%x)\n", 372 status); 373 goto write_exit; 374 } 375 376 if (status & I2C_STAT_XRDY) { 377 w = (i < 0) ? tmpbuf[2+i] : buffer[i]; 378 #if !(defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) || \ 379 defined(CONFIG_OMAP44XX) || defined(CONFIG_AM33XX)) 380 w |= ((++i < 0) ? tmpbuf[2+i] : buffer[i]) << 8; 381 #endif 382 writew(w, &i2c_base->data); 383 writew(I2C_STAT_XRDY, &i2c_base->stat); 384 } else { 385 i2c_error = 1; 386 printf("i2c bus not ready for Tx (i=%d)\n", i); 387 goto write_exit; 388 } 389 } 390 391 write_exit: 392 flush_fifo(); 393 writew(0xFFFF, &i2c_base->stat); 394 return i2c_error; 395 } 396 397 static void wait_for_bb(void) 398 { 399 int timeout = I2C_TIMEOUT; 400 u16 stat; 401 402 writew(0xFFFF, &i2c_base->stat); /* clear current interrupts...*/ 403 while ((stat = readw(&i2c_base->stat) & I2C_STAT_BB) && timeout--) { 404 writew(stat, &i2c_base->stat); 405 udelay(1000); 406 } 407 408 if (timeout <= 0) { 409 printf("timed out in wait_for_bb: I2C_STAT=%x\n", 410 readw(&i2c_base->stat)); 411 } 412 writew(0xFFFF, &i2c_base->stat); /* clear delayed stuff*/ 413 } 414 415 static u16 wait_for_pin(void) 416 { 417 u16 status; 418 int timeout = I2C_TIMEOUT; 419 420 do { 421 udelay(1000); 422 status = readw(&i2c_base->stat); 423 } while (!(status & 424 (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY | 425 I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK | 426 I2C_STAT_AL)) && timeout--); 427 428 if (timeout <= 0) { 429 printf("timed out in wait_for_pin: I2C_STAT=%x\n", 430 readw(&i2c_base->stat)); 431 writew(0xFFFF, &i2c_base->stat); 432 status = 0; 433 } 434 435 return status; 436 } 437 438 int i2c_set_bus_num(unsigned int bus) 439 { 440 if ((bus < 0) || (bus >= I2C_BUS_MAX)) { 441 printf("Bad bus: %d\n", bus); 442 return -1; 443 } 444 445 #if I2C_BUS_MAX == 4 446 if (bus == 3) 447 i2c_base = (struct i2c *)I2C_BASE4; 448 else 449 if (bus == 2) 450 i2c_base = (struct i2c *)I2C_BASE3; 451 else 452 #endif 453 #if I2C_BUS_MAX == 3 454 if (bus == 2) 455 i2c_base = (struct i2c *)I2C_BASE3; 456 else 457 #endif 458 if (bus == 1) 459 i2c_base = (struct i2c *)I2C_BASE2; 460 else 461 i2c_base = (struct i2c *)I2C_BASE1; 462 463 current_bus = bus; 464 465 if (!bus_initialized[current_bus]) 466 i2c_init(CONFIG_SYS_I2C_SPEED, CONFIG_SYS_I2C_SLAVE); 467 468 return 0; 469 } 470 471 int i2c_get_bus_num(void) 472 { 473 return (int) current_bus; 474 } 475