1 /* 2 * i2c driver for Freescale mx31 3 * 4 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <common.h> 26 #include <asm/io.h> 27 28 #if defined(CONFIG_HARD_I2C) 29 30 #include <asm/arch/clock.h> 31 #include <asm/arch/imx-regs.h> 32 33 #define IADR 0x00 34 #define IFDR 0x04 35 #define I2CR 0x08 36 #define I2SR 0x0c 37 #define I2DR 0x10 38 39 #define I2CR_IEN (1 << 7) 40 #define I2CR_IIEN (1 << 6) 41 #define I2CR_MSTA (1 << 5) 42 #define I2CR_MTX (1 << 4) 43 #define I2CR_TX_NO_AK (1 << 3) 44 #define I2CR_RSTA (1 << 2) 45 46 #define I2SR_ICF (1 << 7) 47 #define I2SR_IBB (1 << 5) 48 #define I2SR_IIF (1 << 1) 49 #define I2SR_RX_NO_AK (1 << 0) 50 51 #if defined(CONFIG_SYS_I2C_MX31_PORT1) 52 #define I2C_BASE 0x43f80000 53 #define I2C_CLK_OFFSET 26 54 #elif defined (CONFIG_SYS_I2C_MX31_PORT2) 55 #define I2C_BASE 0x43f98000 56 #define I2C_CLK_OFFSET 28 57 #elif defined (CONFIG_SYS_I2C_MX31_PORT3) 58 #define I2C_BASE 0x43f84000 59 #define I2C_CLK_OFFSET 30 60 #elif defined(CONFIG_SYS_I2C_MX53_PORT1) 61 #define I2C_BASE I2C1_BASE_ADDR 62 #elif defined(CONFIG_SYS_I2C_MX53_PORT2) 63 #define I2C_BASE I2C2_BASE_ADDR 64 #elif defined(CONFIG_SYS_I2C_MX35_PORT1) 65 #define I2C_BASE I2C_BASE_ADDR 66 #else 67 #error "define CONFIG_SYS_I2C_MX<Processor>_PORTx to use the mx I2C driver" 68 #endif 69 70 #define I2C_MAX_TIMEOUT 10000 71 #define I2C_MAX_RETRIES 3 72 73 static u16 div[] = { 30, 32, 36, 42, 48, 52, 60, 72, 80, 88, 104, 128, 144, 74 160, 192, 240, 288, 320, 384, 480, 576, 640, 768, 960, 75 1152, 1280, 1536, 1920, 2304, 2560, 3072, 3840}; 76 77 static inline void i2c_reset(void) 78 { 79 writew(0, I2C_BASE + I2CR); /* Reset module */ 80 writew(0, I2C_BASE + I2SR); 81 writew(I2CR_IEN, I2C_BASE + I2CR); 82 } 83 84 void i2c_init(int speed, int unused) 85 { 86 int freq; 87 int i; 88 89 #if defined(CONFIG_MX31) 90 struct clock_control_regs *sc_regs = 91 (struct clock_control_regs *)CCM_BASE; 92 93 freq = mx31_get_ipg_clk(); 94 /* start the required I2C clock */ 95 writel(readl(&sc_regs->cgr0) | (3 << I2C_CLK_OFFSET), 96 &sc_regs->cgr0); 97 #else 98 freq = mxc_get_clock(MXC_IPG_PERCLK); 99 #endif 100 101 for (i = 0; i < 0x1f; i++) 102 if (freq / div[i] <= speed) 103 break; 104 105 debug("%s: speed: %d\n", __func__, speed); 106 107 writew(i, I2C_BASE + IFDR); 108 i2c_reset(); 109 } 110 111 static int wait_idle(void) 112 { 113 int timeout = I2C_MAX_TIMEOUT; 114 115 while ((readw(I2C_BASE + I2SR) & I2SR_IBB) && --timeout) { 116 writew(0, I2C_BASE + I2SR); 117 udelay(1); 118 } 119 return timeout ? timeout : (!(readw(I2C_BASE + I2SR) & I2SR_IBB)); 120 } 121 122 static int wait_busy(void) 123 { 124 int timeout = I2C_MAX_TIMEOUT; 125 126 while (!(readw(I2C_BASE + I2SR) & I2SR_IBB) && --timeout) 127 udelay(1); 128 writew(0, I2C_BASE + I2SR); /* clear interrupt */ 129 130 return timeout; 131 } 132 133 static int wait_complete(void) 134 { 135 int timeout = I2C_MAX_TIMEOUT; 136 137 while ((!(readw(I2C_BASE + I2SR) & I2SR_ICF)) && (--timeout)) { 138 writew(0, I2C_BASE + I2SR); 139 udelay(1); 140 } 141 udelay(200); 142 143 writew(0, I2C_BASE + I2SR); /* clear interrupt */ 144 145 return timeout; 146 } 147 148 149 static int tx_byte(u8 byte) 150 { 151 writew(byte, I2C_BASE + I2DR); 152 153 if (!wait_complete() || readw(I2C_BASE + I2SR) & I2SR_RX_NO_AK) 154 return -1; 155 return 0; 156 } 157 158 static int rx_byte(int last) 159 { 160 if (!wait_complete()) 161 return -1; 162 163 if (last) 164 writew(I2CR_IEN, I2C_BASE + I2CR); 165 166 return readw(I2C_BASE + I2DR); 167 } 168 169 int i2c_probe(uchar chip) 170 { 171 int ret; 172 173 writew(0, I2C_BASE + I2CR); /* Reset module */ 174 writew(I2CR_IEN, I2C_BASE + I2CR); 175 176 writew(I2CR_IEN | I2CR_MSTA | I2CR_MTX, I2C_BASE + I2CR); 177 ret = tx_byte(chip << 1); 178 writew(I2CR_IEN | I2CR_MTX, I2C_BASE + I2CR); 179 180 return ret; 181 } 182 183 static int i2c_addr(uchar chip, uint addr, int alen) 184 { 185 int i, retry = 0; 186 for (retry = 0; retry < 3; retry++) { 187 if (wait_idle()) 188 break; 189 i2c_reset(); 190 for (i = 0; i < I2C_MAX_TIMEOUT; i++) 191 udelay(1); 192 } 193 if (retry >= I2C_MAX_RETRIES) { 194 debug("%s:bus is busy(%x)\n", 195 __func__, readw(I2C_BASE + I2SR)); 196 return -1; 197 } 198 writew(I2CR_IEN | I2CR_MSTA | I2CR_MTX, I2C_BASE + I2CR); 199 200 if (!wait_busy()) { 201 debug("%s:trigger start fail(%x)\n", 202 __func__, readw(I2C_BASE + I2SR)); 203 return -1; 204 } 205 206 if (tx_byte(chip << 1) || (readw(I2C_BASE + I2SR) & I2SR_RX_NO_AK)) { 207 debug("%s:chip address cycle fail(%x)\n", 208 __func__, readw(I2C_BASE + I2SR)); 209 return -1; 210 } 211 while (alen--) 212 if (tx_byte((addr >> (alen * 8)) & 0xff) || 213 (readw(I2C_BASE + I2SR) & I2SR_RX_NO_AK)) { 214 debug("%s:device address cycle fail(%x)\n", 215 __func__, readw(I2C_BASE + I2SR)); 216 return -1; 217 } 218 return 0; 219 } 220 221 int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len) 222 { 223 int timeout = I2C_MAX_TIMEOUT; 224 int ret; 225 226 debug("%s chip: 0x%02x addr: 0x%04x alen: %d len: %d\n", 227 __func__, chip, addr, alen, len); 228 229 if (i2c_addr(chip, addr, alen)) { 230 printf("i2c_addr failed\n"); 231 return -1; 232 } 233 234 writew(I2CR_IEN | I2CR_MSTA | I2CR_MTX | I2CR_RSTA, I2C_BASE + I2CR); 235 236 if (tx_byte(chip << 1 | 1)) 237 return -1; 238 239 writew(I2CR_IEN | I2CR_MSTA | 240 ((len == 1) ? I2CR_TX_NO_AK : 0), 241 I2C_BASE + I2CR); 242 243 ret = readw(I2C_BASE + I2DR); 244 245 while (len--) { 246 ret = rx_byte(len == 0); 247 if (ret < 0) 248 return -1; 249 *buf++ = ret; 250 if (len <= 1) 251 writew(I2CR_IEN | I2CR_MSTA | 252 I2CR_TX_NO_AK, 253 I2C_BASE + I2CR); 254 } 255 256 writew(I2CR_IEN, I2C_BASE + I2CR); 257 258 while (readw(I2C_BASE + I2SR) & I2SR_IBB && --timeout) 259 udelay(1); 260 261 return 0; 262 } 263 264 int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len) 265 { 266 int timeout = I2C_MAX_TIMEOUT; 267 debug("%s chip: 0x%02x addr: 0x%04x alen: %d len: %d\n", 268 __func__, chip, addr, alen, len); 269 270 if (i2c_addr(chip, addr, alen)) 271 return -1; 272 273 while (len--) 274 if (tx_byte(*buf++)) 275 return -1; 276 277 writew(I2CR_IEN, I2C_BASE + I2CR); 278 279 while (readw(I2C_BASE + I2SR) & I2SR_IBB && --timeout) 280 udelay(1); 281 282 return 0; 283 } 284 285 #endif /* CONFIG_HARD_I2C */ 286