1 /* 2 * i2c driver for Freescale i.MX series 3 * 4 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> 5 * (c) 2011 Marek Vasut <marek.vasut@gmail.com> 6 * 7 * Based on i2c-imx.c from linux kernel: 8 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de> 9 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de> 10 * Copyright (C) 2007 RightHand Technologies, Inc. 11 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt> 12 * 13 * 14 * SPDX-License-Identifier: GPL-2.0+ 15 */ 16 17 #include <common.h> 18 #include <asm/arch/clock.h> 19 #include <asm/arch/imx-regs.h> 20 #include <linux/errno.h> 21 #include <asm/mach-imx/mxc_i2c.h> 22 #include <asm/io.h> 23 #include <i2c.h> 24 #include <watchdog.h> 25 #include <dm.h> 26 #include <dm/pinctrl.h> 27 #include <fdtdec.h> 28 29 DECLARE_GLOBAL_DATA_PTR; 30 31 #define I2C_QUIRK_FLAG (1 << 0) 32 33 #define IMX_I2C_REGSHIFT 2 34 #define VF610_I2C_REGSHIFT 0 35 36 #define I2C_EARLY_INIT_INDEX 0 37 #ifdef CONFIG_SYS_I2C_IFDR_DIV 38 #define I2C_IFDR_DIV_CONSERVATIVE CONFIG_SYS_I2C_IFDR_DIV 39 #else 40 #define I2C_IFDR_DIV_CONSERVATIVE 0x7e 41 #endif 42 43 /* Register index */ 44 #define IADR 0 45 #define IFDR 1 46 #define I2CR 2 47 #define I2SR 3 48 #define I2DR 4 49 50 #define I2CR_IIEN (1 << 6) 51 #define I2CR_MSTA (1 << 5) 52 #define I2CR_MTX (1 << 4) 53 #define I2CR_TX_NO_AK (1 << 3) 54 #define I2CR_RSTA (1 << 2) 55 56 #define I2SR_ICF (1 << 7) 57 #define I2SR_IBB (1 << 5) 58 #define I2SR_IAL (1 << 4) 59 #define I2SR_IIF (1 << 1) 60 #define I2SR_RX_NO_AK (1 << 0) 61 62 #ifdef I2C_QUIRK_REG 63 #define I2CR_IEN (0 << 7) 64 #define I2CR_IDIS (1 << 7) 65 #define I2SR_IIF_CLEAR (1 << 1) 66 #else 67 #define I2CR_IEN (1 << 7) 68 #define I2CR_IDIS (0 << 7) 69 #define I2SR_IIF_CLEAR (0 << 1) 70 #endif 71 72 #ifdef I2C_QUIRK_REG 73 static u16 i2c_clk_div[60][2] = { 74 { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 }, 75 { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 }, 76 { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D }, 77 { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 }, 78 { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 }, 79 { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 }, 80 { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 }, 81 { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 }, 82 { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 }, 83 { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B }, 84 { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 }, 85 { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 }, 86 { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B }, 87 { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A }, 88 { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E }, 89 }; 90 #else 91 static u16 i2c_clk_div[50][2] = { 92 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 }, 93 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 }, 94 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 }, 95 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B }, 96 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A }, 97 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 }, 98 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 }, 99 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 }, 100 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 }, 101 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B }, 102 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E }, 103 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D }, 104 { 3072, 0x1E }, { 3840, 0x1F } 105 }; 106 #endif 107 108 #ifndef CONFIG_SYS_MXC_I2C1_SPEED 109 #define CONFIG_SYS_MXC_I2C1_SPEED 100000 110 #endif 111 #ifndef CONFIG_SYS_MXC_I2C2_SPEED 112 #define CONFIG_SYS_MXC_I2C2_SPEED 100000 113 #endif 114 #ifndef CONFIG_SYS_MXC_I2C3_SPEED 115 #define CONFIG_SYS_MXC_I2C3_SPEED 100000 116 #endif 117 #ifndef CONFIG_SYS_MXC_I2C4_SPEED 118 #define CONFIG_SYS_MXC_I2C4_SPEED 100000 119 #endif 120 121 #ifndef CONFIG_SYS_MXC_I2C1_SLAVE 122 #define CONFIG_SYS_MXC_I2C1_SLAVE 0 123 #endif 124 #ifndef CONFIG_SYS_MXC_I2C2_SLAVE 125 #define CONFIG_SYS_MXC_I2C2_SLAVE 0 126 #endif 127 #ifndef CONFIG_SYS_MXC_I2C3_SLAVE 128 #define CONFIG_SYS_MXC_I2C3_SLAVE 0 129 #endif 130 #ifndef CONFIG_SYS_MXC_I2C4_SLAVE 131 #define CONFIG_SYS_MXC_I2C4_SLAVE 0 132 #endif 133 134 /* 135 * Calculate and set proper clock divider 136 */ 137 static uint8_t i2c_imx_get_clk(struct mxc_i2c_bus *i2c_bus, unsigned int rate) 138 { 139 unsigned int i2c_clk_rate; 140 unsigned int div; 141 u8 clk_div; 142 143 #if defined(CONFIG_MX31) 144 struct clock_control_regs *sc_regs = 145 (struct clock_control_regs *)CCM_BASE; 146 147 /* start the required I2C clock */ 148 writel(readl(&sc_regs->cgr0) | (3 << CONFIG_SYS_I2C_CLK_OFFSET), 149 &sc_regs->cgr0); 150 #endif 151 152 /* Divider value calculation */ 153 i2c_clk_rate = mxc_get_clock(MXC_I2C_CLK); 154 div = (i2c_clk_rate + rate - 1) / rate; 155 if (div < i2c_clk_div[0][0]) 156 clk_div = 0; 157 else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0]) 158 clk_div = ARRAY_SIZE(i2c_clk_div) - 1; 159 else 160 for (clk_div = 0; i2c_clk_div[clk_div][0] < div; clk_div++) 161 ; 162 163 /* Store divider value */ 164 return clk_div; 165 } 166 167 /* 168 * Set I2C Bus speed 169 */ 170 static int bus_i2c_set_bus_speed(struct mxc_i2c_bus *i2c_bus, int speed) 171 { 172 ulong base = i2c_bus->base; 173 bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false; 174 u8 clk_idx = i2c_imx_get_clk(i2c_bus, speed); 175 u8 idx = i2c_clk_div[clk_idx][1]; 176 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT; 177 178 if (!base) 179 return -ENODEV; 180 181 /* Store divider value */ 182 writeb(idx, base + (IFDR << reg_shift)); 183 184 /* Reset module */ 185 writeb(I2CR_IDIS, base + (I2CR << reg_shift)); 186 writeb(0, base + (I2SR << reg_shift)); 187 return 0; 188 } 189 190 #define ST_BUS_IDLE (0 | (I2SR_IBB << 8)) 191 #define ST_BUS_BUSY (I2SR_IBB | (I2SR_IBB << 8)) 192 #define ST_IIF (I2SR_IIF | (I2SR_IIF << 8)) 193 194 static int wait_for_sr_state(struct mxc_i2c_bus *i2c_bus, unsigned state) 195 { 196 unsigned sr; 197 ulong elapsed; 198 bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false; 199 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT; 200 ulong base = i2c_bus->base; 201 ulong start_time = get_timer(0); 202 for (;;) { 203 sr = readb(base + (I2SR << reg_shift)); 204 if (sr & I2SR_IAL) { 205 if (quirk) 206 writeb(sr | I2SR_IAL, base + 207 (I2SR << reg_shift)); 208 else 209 writeb(sr & ~I2SR_IAL, base + 210 (I2SR << reg_shift)); 211 printf("%s: Arbitration lost sr=%x cr=%x state=%x\n", 212 __func__, sr, readb(base + (I2CR << reg_shift)), 213 state); 214 return -ERESTART; 215 } 216 if ((sr & (state >> 8)) == (unsigned char)state) 217 return sr; 218 WATCHDOG_RESET(); 219 elapsed = get_timer(start_time); 220 if (elapsed > (CONFIG_SYS_HZ / 10)) /* .1 seconds */ 221 break; 222 } 223 printf("%s: failed sr=%x cr=%x state=%x\n", __func__, 224 sr, readb(base + (I2CR << reg_shift)), state); 225 return -ETIMEDOUT; 226 } 227 228 static int tx_byte(struct mxc_i2c_bus *i2c_bus, u8 byte) 229 { 230 int ret; 231 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ? 232 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT; 233 ulong base = i2c_bus->base; 234 235 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift)); 236 writeb(byte, base + (I2DR << reg_shift)); 237 238 ret = wait_for_sr_state(i2c_bus, ST_IIF); 239 if (ret < 0) 240 return ret; 241 if (ret & I2SR_RX_NO_AK) 242 return -ENODEV; 243 return 0; 244 } 245 246 /* 247 * Stub implementations for outer i2c slave operations. 248 */ 249 void __i2c_force_reset_slave(void) 250 { 251 } 252 void i2c_force_reset_slave(void) 253 __attribute__((weak, alias("__i2c_force_reset_slave"))); 254 255 /* 256 * Stop I2C transaction 257 */ 258 static void i2c_imx_stop(struct mxc_i2c_bus *i2c_bus) 259 { 260 int ret; 261 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ? 262 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT; 263 ulong base = i2c_bus->base; 264 unsigned int temp = readb(base + (I2CR << reg_shift)); 265 266 temp &= ~(I2CR_MSTA | I2CR_MTX); 267 writeb(temp, base + (I2CR << reg_shift)); 268 ret = wait_for_sr_state(i2c_bus, ST_BUS_IDLE); 269 if (ret < 0) 270 printf("%s:trigger stop failed\n", __func__); 271 } 272 273 /* 274 * Send start signal, chip address and 275 * write register address 276 */ 277 static int i2c_init_transfer_(struct mxc_i2c_bus *i2c_bus, u8 chip, 278 u32 addr, int alen) 279 { 280 unsigned int temp; 281 int ret; 282 bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false; 283 ulong base = i2c_bus->base; 284 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT; 285 286 /* Reset i2c slave */ 287 i2c_force_reset_slave(); 288 289 /* Enable I2C controller */ 290 if (quirk) 291 ret = readb(base + (I2CR << reg_shift)) & I2CR_IDIS; 292 else 293 ret = !(readb(base + (I2CR << reg_shift)) & I2CR_IEN); 294 295 if (ret) { 296 writeb(I2CR_IEN, base + (I2CR << reg_shift)); 297 /* Wait for controller to be stable */ 298 udelay(50); 299 } 300 301 if (readb(base + (IADR << reg_shift)) == (chip << 1)) 302 writeb((chip << 1) ^ 2, base + (IADR << reg_shift)); 303 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift)); 304 ret = wait_for_sr_state(i2c_bus, ST_BUS_IDLE); 305 if (ret < 0) 306 return ret; 307 308 /* Start I2C transaction */ 309 temp = readb(base + (I2CR << reg_shift)); 310 temp |= I2CR_MSTA; 311 writeb(temp, base + (I2CR << reg_shift)); 312 313 ret = wait_for_sr_state(i2c_bus, ST_BUS_BUSY); 314 if (ret < 0) 315 return ret; 316 317 temp |= I2CR_MTX | I2CR_TX_NO_AK; 318 writeb(temp, base + (I2CR << reg_shift)); 319 320 /* write slave address */ 321 ret = tx_byte(i2c_bus, chip << 1); 322 if (ret < 0) 323 return ret; 324 325 while (alen--) { 326 ret = tx_byte(i2c_bus, (addr >> (alen * 8)) & 0xff); 327 if (ret < 0) 328 return ret; 329 } 330 return 0; 331 } 332 333 #ifndef CONFIG_DM_I2C 334 int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus) 335 { 336 if (i2c_bus && i2c_bus->idle_bus_fn) 337 return i2c_bus->idle_bus_fn(i2c_bus->idle_bus_data); 338 return 0; 339 } 340 #else 341 /* 342 * See Linux Documentation/devicetree/bindings/i2c/i2c-imx.txt 343 * " 344 * scl-gpios: specify the gpio related to SCL pin 345 * sda-gpios: specify the gpio related to SDA pin 346 * add pinctrl to configure i2c pins to gpio function for i2c 347 * bus recovery, call it "gpio" state 348 * " 349 * 350 * The i2c_idle_bus is an implementation following Linux Kernel. 351 */ 352 int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus) 353 { 354 struct udevice *bus = i2c_bus->bus; 355 struct gpio_desc *scl_gpio = &i2c_bus->scl_gpio; 356 struct gpio_desc *sda_gpio = &i2c_bus->sda_gpio; 357 int sda, scl; 358 int i, ret = 0; 359 ulong elapsed, start_time; 360 361 if (pinctrl_select_state(bus, "gpio")) { 362 dev_dbg(bus, "Can not to switch to use gpio pinmux\n"); 363 /* 364 * GPIO pinctrl for i2c force idle is not a must, 365 * but it is strongly recommended to be used. 366 * Because it can help you to recover from bad 367 * i2c bus state. Do not return failure, because 368 * it is not a must. 369 */ 370 return 0; 371 } 372 373 dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN); 374 dm_gpio_set_dir_flags(sda_gpio, GPIOD_IS_IN); 375 scl = dm_gpio_get_value(scl_gpio); 376 sda = dm_gpio_get_value(sda_gpio); 377 378 if ((sda & scl) == 1) 379 goto exit; /* Bus is idle already */ 380 381 /* Send high and low on the SCL line */ 382 for (i = 0; i < 9; i++) { 383 dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_OUT); 384 dm_gpio_set_value(scl_gpio, 0); 385 udelay(50); 386 dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN); 387 udelay(50); 388 } 389 start_time = get_timer(0); 390 for (;;) { 391 dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN); 392 dm_gpio_set_dir_flags(sda_gpio, GPIOD_IS_IN); 393 scl = dm_gpio_get_value(scl_gpio); 394 sda = dm_gpio_get_value(sda_gpio); 395 if ((sda & scl) == 1) 396 break; 397 WATCHDOG_RESET(); 398 elapsed = get_timer(start_time); 399 if (elapsed > (CONFIG_SYS_HZ / 5)) { /* .2 seconds */ 400 ret = -EBUSY; 401 printf("%s: failed to clear bus, sda=%d scl=%d\n", __func__, sda, scl); 402 break; 403 } 404 } 405 406 exit: 407 pinctrl_select_state(bus, "default"); 408 return ret; 409 } 410 #endif 411 412 static int i2c_init_transfer(struct mxc_i2c_bus *i2c_bus, u8 chip, 413 u32 addr, int alen) 414 { 415 int retry; 416 int ret; 417 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ? 418 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT; 419 420 if (!i2c_bus->base) 421 return -ENODEV; 422 423 for (retry = 0; retry < 3; retry++) { 424 ret = i2c_init_transfer_(i2c_bus, chip, addr, alen); 425 if (ret >= 0) 426 return 0; 427 i2c_imx_stop(i2c_bus); 428 if (ret == -ENODEV) 429 return ret; 430 431 printf("%s: failed for chip 0x%x retry=%d\n", __func__, chip, 432 retry); 433 if (ret != -ERESTART) 434 /* Disable controller */ 435 writeb(I2CR_IDIS, i2c_bus->base + (I2CR << reg_shift)); 436 udelay(100); 437 if (i2c_idle_bus(i2c_bus) < 0) 438 break; 439 } 440 printf("%s: give up i2c_regs=0x%lx\n", __func__, i2c_bus->base); 441 return ret; 442 } 443 444 445 static int i2c_write_data(struct mxc_i2c_bus *i2c_bus, u8 chip, const u8 *buf, 446 int len) 447 { 448 int i, ret = 0; 449 450 debug("i2c_write_data: chip=0x%x, len=0x%x\n", chip, len); 451 debug("write_data: "); 452 /* use rc for counter */ 453 for (i = 0; i < len; ++i) 454 debug(" 0x%02x", buf[i]); 455 debug("\n"); 456 457 for (i = 0; i < len; i++) { 458 ret = tx_byte(i2c_bus, buf[i]); 459 if (ret < 0) { 460 debug("i2c_write_data(): rc=%d\n", ret); 461 break; 462 } 463 } 464 465 return ret; 466 } 467 468 static int i2c_read_data(struct mxc_i2c_bus *i2c_bus, uchar chip, uchar *buf, 469 int len) 470 { 471 int ret; 472 unsigned int temp; 473 int i; 474 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ? 475 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT; 476 ulong base = i2c_bus->base; 477 478 debug("i2c_read_data: chip=0x%x, len=0x%x\n", chip, len); 479 480 /* setup bus to read data */ 481 temp = readb(base + (I2CR << reg_shift)); 482 temp &= ~(I2CR_MTX | I2CR_TX_NO_AK); 483 if (len == 1) 484 temp |= I2CR_TX_NO_AK; 485 writeb(temp, base + (I2CR << reg_shift)); 486 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift)); 487 /* dummy read to clear ICF */ 488 readb(base + (I2DR << reg_shift)); 489 490 /* read data */ 491 for (i = 0; i < len; i++) { 492 ret = wait_for_sr_state(i2c_bus, ST_IIF); 493 if (ret < 0) { 494 debug("i2c_read_data(): ret=%d\n", ret); 495 i2c_imx_stop(i2c_bus); 496 return ret; 497 } 498 499 /* 500 * It must generate STOP before read I2DR to prevent 501 * controller from generating another clock cycle 502 */ 503 if (i == (len - 1)) { 504 i2c_imx_stop(i2c_bus); 505 } else if (i == (len - 2)) { 506 temp = readb(base + (I2CR << reg_shift)); 507 temp |= I2CR_TX_NO_AK; 508 writeb(temp, base + (I2CR << reg_shift)); 509 } 510 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift)); 511 buf[i] = readb(base + (I2DR << reg_shift)); 512 } 513 514 /* reuse ret for counter*/ 515 for (ret = 0; ret < len; ++ret) 516 debug(" 0x%02x", buf[ret]); 517 debug("\n"); 518 519 i2c_imx_stop(i2c_bus); 520 return 0; 521 } 522 523 #ifndef CONFIG_DM_I2C 524 /* 525 * Read data from I2C device 526 */ 527 static int bus_i2c_read(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr, 528 int alen, u8 *buf, int len) 529 { 530 int ret = 0; 531 u32 temp; 532 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ? 533 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT; 534 ulong base = i2c_bus->base; 535 536 ret = i2c_init_transfer(i2c_bus, chip, addr, alen); 537 if (ret < 0) 538 return ret; 539 540 temp = readb(base + (I2CR << reg_shift)); 541 temp |= I2CR_RSTA; 542 writeb(temp, base + (I2CR << reg_shift)); 543 544 ret = tx_byte(i2c_bus, (chip << 1) | 1); 545 if (ret < 0) { 546 i2c_imx_stop(i2c_bus); 547 return ret; 548 } 549 550 ret = i2c_read_data(i2c_bus, chip, buf, len); 551 552 i2c_imx_stop(i2c_bus); 553 return ret; 554 } 555 556 /* 557 * Write data to I2C device 558 */ 559 static int bus_i2c_write(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr, 560 int alen, const u8 *buf, int len) 561 { 562 int ret = 0; 563 564 ret = i2c_init_transfer(i2c_bus, chip, addr, alen); 565 if (ret < 0) 566 return ret; 567 568 ret = i2c_write_data(i2c_bus, chip, buf, len); 569 570 i2c_imx_stop(i2c_bus); 571 572 return ret; 573 } 574 575 #if !defined(I2C2_BASE_ADDR) 576 #define I2C2_BASE_ADDR 0 577 #endif 578 579 #if !defined(I2C3_BASE_ADDR) 580 #define I2C3_BASE_ADDR 0 581 #endif 582 583 #if !defined(I2C4_BASE_ADDR) 584 #define I2C4_BASE_ADDR 0 585 #endif 586 587 static struct mxc_i2c_bus mxc_i2c_buses[] = { 588 #if defined(CONFIG_ARCH_LS1021A) || defined(CONFIG_VF610) || \ 589 defined(CONFIG_FSL_LAYERSCAPE) 590 { 0, I2C1_BASE_ADDR, I2C_QUIRK_FLAG }, 591 { 1, I2C2_BASE_ADDR, I2C_QUIRK_FLAG }, 592 { 2, I2C3_BASE_ADDR, I2C_QUIRK_FLAG }, 593 { 3, I2C4_BASE_ADDR, I2C_QUIRK_FLAG }, 594 #else 595 { 0, I2C1_BASE_ADDR, 0 }, 596 { 1, I2C2_BASE_ADDR, 0 }, 597 { 2, I2C3_BASE_ADDR, 0 }, 598 { 3, I2C4_BASE_ADDR, 0 }, 599 #endif 600 }; 601 602 struct mxc_i2c_bus *i2c_get_base(struct i2c_adapter *adap) 603 { 604 return &mxc_i2c_buses[adap->hwadapnr]; 605 } 606 607 static int mxc_i2c_read(struct i2c_adapter *adap, uint8_t chip, 608 uint addr, int alen, uint8_t *buffer, 609 int len) 610 { 611 return bus_i2c_read(i2c_get_base(adap), chip, addr, alen, buffer, len); 612 } 613 614 static int mxc_i2c_write(struct i2c_adapter *adap, uint8_t chip, 615 uint addr, int alen, uint8_t *buffer, 616 int len) 617 { 618 return bus_i2c_write(i2c_get_base(adap), chip, addr, alen, buffer, len); 619 } 620 621 /* 622 * Test if a chip at a given address responds (probe the chip) 623 */ 624 static int mxc_i2c_probe(struct i2c_adapter *adap, uint8_t chip) 625 { 626 return bus_i2c_write(i2c_get_base(adap), chip, 0, 0, NULL, 0); 627 } 628 629 int __enable_i2c_clk(unsigned char enable, unsigned i2c_num) 630 { 631 return 1; 632 } 633 int enable_i2c_clk(unsigned char enable, unsigned i2c_num) 634 __attribute__((weak, alias("__enable_i2c_clk"))); 635 636 void bus_i2c_init(int index, int speed, int unused, 637 int (*idle_bus_fn)(void *p), void *idle_bus_data) 638 { 639 int ret; 640 641 if (index >= ARRAY_SIZE(mxc_i2c_buses)) { 642 debug("Error i2c index\n"); 643 return; 644 } 645 646 /* 647 * Warning: Be careful to allow the assignment to a static 648 * variable here. This function could be called while U-Boot is 649 * still running in flash memory. So such assignment is equal 650 * to write data to flash without erasing. 651 */ 652 if (idle_bus_fn) 653 mxc_i2c_buses[index].idle_bus_fn = idle_bus_fn; 654 if (idle_bus_data) 655 mxc_i2c_buses[index].idle_bus_data = idle_bus_data; 656 657 ret = enable_i2c_clk(1, index); 658 if (ret < 0) { 659 debug("I2C-%d clk fail to enable.\n", index); 660 return; 661 } 662 663 bus_i2c_set_bus_speed(&mxc_i2c_buses[index], speed); 664 } 665 666 /* 667 * Early init I2C for prepare read the clk through I2C. 668 */ 669 void i2c_early_init_f(void) 670 { 671 ulong base = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].base; 672 bool quirk = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].driver_data 673 & I2C_QUIRK_FLAG ? true : false; 674 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT; 675 676 /* Set I2C divider value */ 677 writeb(I2C_IFDR_DIV_CONSERVATIVE, base + (IFDR << reg_shift)); 678 /* Reset module */ 679 writeb(I2CR_IDIS, base + (I2CR << reg_shift)); 680 writeb(0, base + (I2SR << reg_shift)); 681 /* Enable I2C */ 682 writeb(I2CR_IEN, base + (I2CR << reg_shift)); 683 } 684 685 /* 686 * Init I2C Bus 687 */ 688 static void mxc_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr) 689 { 690 bus_i2c_init(adap->hwadapnr, speed, slaveaddr, NULL, NULL); 691 } 692 693 /* 694 * Set I2C Speed 695 */ 696 static u32 mxc_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed) 697 { 698 return bus_i2c_set_bus_speed(i2c_get_base(adap), speed); 699 } 700 701 /* 702 * Register mxc i2c adapters 703 */ 704 #ifdef CONFIG_SYS_I2C_MXC_I2C1 705 U_BOOT_I2C_ADAP_COMPLETE(mxc0, mxc_i2c_init, mxc_i2c_probe, 706 mxc_i2c_read, mxc_i2c_write, 707 mxc_i2c_set_bus_speed, 708 CONFIG_SYS_MXC_I2C1_SPEED, 709 CONFIG_SYS_MXC_I2C1_SLAVE, 0) 710 #endif 711 712 #ifdef CONFIG_SYS_I2C_MXC_I2C2 713 U_BOOT_I2C_ADAP_COMPLETE(mxc1, mxc_i2c_init, mxc_i2c_probe, 714 mxc_i2c_read, mxc_i2c_write, 715 mxc_i2c_set_bus_speed, 716 CONFIG_SYS_MXC_I2C2_SPEED, 717 CONFIG_SYS_MXC_I2C2_SLAVE, 1) 718 #endif 719 720 #ifdef CONFIG_SYS_I2C_MXC_I2C3 721 U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe, 722 mxc_i2c_read, mxc_i2c_write, 723 mxc_i2c_set_bus_speed, 724 CONFIG_SYS_MXC_I2C3_SPEED, 725 CONFIG_SYS_MXC_I2C3_SLAVE, 2) 726 #endif 727 728 #ifdef CONFIG_SYS_I2C_MXC_I2C4 729 U_BOOT_I2C_ADAP_COMPLETE(mxc3, mxc_i2c_init, mxc_i2c_probe, 730 mxc_i2c_read, mxc_i2c_write, 731 mxc_i2c_set_bus_speed, 732 CONFIG_SYS_MXC_I2C4_SPEED, 733 CONFIG_SYS_MXC_I2C4_SLAVE, 3) 734 #endif 735 736 #else 737 738 static int mxc_i2c_set_bus_speed(struct udevice *bus, unsigned int speed) 739 { 740 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus); 741 742 return bus_i2c_set_bus_speed(i2c_bus, speed); 743 } 744 745 static int mxc_i2c_probe(struct udevice *bus) 746 { 747 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus); 748 const void *fdt = gd->fdt_blob; 749 int node = dev_of_offset(bus); 750 fdt_addr_t addr; 751 int ret, ret2; 752 753 i2c_bus->driver_data = dev_get_driver_data(bus); 754 755 addr = devfdt_get_addr(bus); 756 if (addr == FDT_ADDR_T_NONE) 757 return -ENODEV; 758 759 i2c_bus->base = addr; 760 i2c_bus->index = bus->seq; 761 i2c_bus->bus = bus; 762 763 /* Enable clk */ 764 ret = enable_i2c_clk(1, bus->seq); 765 if (ret < 0) 766 return ret; 767 768 /* 769 * See Documentation/devicetree/bindings/i2c/i2c-imx.txt 770 * Use gpio to force bus idle when necessary. 771 */ 772 ret = fdt_stringlist_search(fdt, node, "pinctrl-names", "gpio"); 773 if (ret < 0) { 774 debug("i2c bus %d at 0x%2lx, no gpio pinctrl state.\n", bus->seq, i2c_bus->base); 775 } else { 776 ret = gpio_request_by_name_nodev(offset_to_ofnode(node), 777 "scl-gpios", 0, &i2c_bus->scl_gpio, 778 GPIOD_IS_OUT); 779 ret2 = gpio_request_by_name_nodev(offset_to_ofnode(node), 780 "sda-gpios", 0, &i2c_bus->sda_gpio, 781 GPIOD_IS_OUT); 782 if (!dm_gpio_is_valid(&i2c_bus->sda_gpio) | 783 !dm_gpio_is_valid(&i2c_bus->scl_gpio) | 784 ret | ret2) { 785 dev_err(dev, "i2c bus %d at %lu, fail to request scl/sda gpio\n", bus->seq, i2c_bus->base); 786 return -ENODEV; 787 } 788 } 789 790 ret = i2c_idle_bus(i2c_bus); 791 if (ret < 0) { 792 /* Disable clk */ 793 enable_i2c_clk(0, bus->seq); 794 return ret; 795 } 796 797 /* 798 * Pinmux settings are in board file now, until pinmux is supported, 799 * we can set pinmux here in probe function. 800 */ 801 802 debug("i2c : controller bus %d at %lu , speed %d: ", 803 bus->seq, i2c_bus->base, 804 i2c_bus->speed); 805 806 return 0; 807 } 808 809 static int mxc_i2c_probe_chip(struct udevice *bus, u32 chip_addr, 810 u32 chip_flags) 811 { 812 int ret; 813 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus); 814 815 ret = i2c_init_transfer(i2c_bus, chip_addr, 0, 0); 816 if (ret < 0) { 817 debug("%s failed, ret = %d\n", __func__, ret); 818 return ret; 819 } 820 821 i2c_imx_stop(i2c_bus); 822 823 return 0; 824 } 825 826 static int mxc_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs) 827 { 828 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus); 829 int ret = 0; 830 ulong base = i2c_bus->base; 831 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ? 832 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT; 833 834 /* 835 * Here the 3rd parameter addr and the 4th one alen are set to 0, 836 * because here we only want to send out chip address. The register 837 * address is wrapped in msg. 838 */ 839 ret = i2c_init_transfer(i2c_bus, msg->addr, 0, 0); 840 if (ret < 0) { 841 debug("i2c_init_transfer error: %d\n", ret); 842 return ret; 843 } 844 845 for (; nmsgs > 0; nmsgs--, msg++) { 846 bool next_is_read = nmsgs > 1 && (msg[1].flags & I2C_M_RD); 847 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len); 848 if (msg->flags & I2C_M_RD) 849 ret = i2c_read_data(i2c_bus, msg->addr, msg->buf, 850 msg->len); 851 else { 852 ret = i2c_write_data(i2c_bus, msg->addr, msg->buf, 853 msg->len); 854 if (ret) 855 break; 856 if (next_is_read) { 857 /* Reuse ret */ 858 ret = readb(base + (I2CR << reg_shift)); 859 ret |= I2CR_RSTA; 860 writeb(ret, base + (I2CR << reg_shift)); 861 862 ret = tx_byte(i2c_bus, (msg->addr << 1) | 1); 863 if (ret < 0) { 864 i2c_imx_stop(i2c_bus); 865 break; 866 } 867 } 868 } 869 } 870 871 if (ret) 872 debug("i2c_write: error sending\n"); 873 874 i2c_imx_stop(i2c_bus); 875 876 return ret; 877 } 878 879 static const struct dm_i2c_ops mxc_i2c_ops = { 880 .xfer = mxc_i2c_xfer, 881 .probe_chip = mxc_i2c_probe_chip, 882 .set_bus_speed = mxc_i2c_set_bus_speed, 883 }; 884 885 static const struct udevice_id mxc_i2c_ids[] = { 886 { .compatible = "fsl,imx21-i2c", }, 887 { .compatible = "fsl,vf610-i2c", .data = I2C_QUIRK_FLAG, }, 888 {} 889 }; 890 891 U_BOOT_DRIVER(i2c_mxc) = { 892 .name = "i2c_mxc", 893 .id = UCLASS_I2C, 894 .of_match = mxc_i2c_ids, 895 .probe = mxc_i2c_probe, 896 .priv_auto_alloc_size = sizeof(struct mxc_i2c_bus), 897 .ops = &mxc_i2c_ops, 898 }; 899 #endif 900