1 /* 2 * i2c driver for Freescale i.MX series 3 * 4 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> 5 * (c) 2011 Marek Vasut <marek.vasut@gmail.com> 6 * 7 * Based on i2c-imx.c from linux kernel: 8 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de> 9 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de> 10 * Copyright (C) 2007 RightHand Technologies, Inc. 11 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt> 12 * 13 * 14 * SPDX-License-Identifier: GPL-2.0+ 15 */ 16 17 #include <common.h> 18 #include <asm/arch/clock.h> 19 #include <asm/arch/imx-regs.h> 20 #include <linux/errno.h> 21 #include <asm/imx-common/mxc_i2c.h> 22 #include <asm/io.h> 23 #include <i2c.h> 24 #include <watchdog.h> 25 #include <dm.h> 26 #include <dm/pinctrl.h> 27 #include <fdtdec.h> 28 29 DECLARE_GLOBAL_DATA_PTR; 30 31 #define I2C_QUIRK_FLAG (1 << 0) 32 33 #define IMX_I2C_REGSHIFT 2 34 #define VF610_I2C_REGSHIFT 0 35 36 #define I2C_EARLY_INIT_INDEX 0 37 #ifdef CONFIG_SYS_I2C_IFDR_DIV 38 #define I2C_IFDR_DIV_CONSERVATIVE CONFIG_SYS_I2C_IFDR_DIV 39 #else 40 #define I2C_IFDR_DIV_CONSERVATIVE 0x7e 41 #endif 42 43 /* Register index */ 44 #define IADR 0 45 #define IFDR 1 46 #define I2CR 2 47 #define I2SR 3 48 #define I2DR 4 49 50 #define I2CR_IIEN (1 << 6) 51 #define I2CR_MSTA (1 << 5) 52 #define I2CR_MTX (1 << 4) 53 #define I2CR_TX_NO_AK (1 << 3) 54 #define I2CR_RSTA (1 << 2) 55 56 #define I2SR_ICF (1 << 7) 57 #define I2SR_IBB (1 << 5) 58 #define I2SR_IAL (1 << 4) 59 #define I2SR_IIF (1 << 1) 60 #define I2SR_RX_NO_AK (1 << 0) 61 62 #ifdef I2C_QUIRK_REG 63 #define I2CR_IEN (0 << 7) 64 #define I2CR_IDIS (1 << 7) 65 #define I2SR_IIF_CLEAR (1 << 1) 66 #else 67 #define I2CR_IEN (1 << 7) 68 #define I2CR_IDIS (0 << 7) 69 #define I2SR_IIF_CLEAR (0 << 1) 70 #endif 71 72 #if defined(CONFIG_HARD_I2C) && !defined(CONFIG_SYS_I2C_BASE) 73 #error "define CONFIG_SYS_I2C_BASE to use the mxc_i2c driver" 74 #endif 75 76 #ifdef I2C_QUIRK_REG 77 static u16 i2c_clk_div[60][2] = { 78 { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 }, 79 { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 }, 80 { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D }, 81 { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 }, 82 { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 }, 83 { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 }, 84 { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 }, 85 { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 }, 86 { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 }, 87 { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B }, 88 { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 }, 89 { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 }, 90 { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B }, 91 { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A }, 92 { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E }, 93 }; 94 #else 95 static u16 i2c_clk_div[50][2] = { 96 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 }, 97 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 }, 98 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 }, 99 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B }, 100 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A }, 101 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 }, 102 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 }, 103 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 }, 104 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 }, 105 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B }, 106 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E }, 107 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D }, 108 { 3072, 0x1E }, { 3840, 0x1F } 109 }; 110 #endif 111 112 #ifndef CONFIG_SYS_MXC_I2C1_SPEED 113 #define CONFIG_SYS_MXC_I2C1_SPEED 100000 114 #endif 115 #ifndef CONFIG_SYS_MXC_I2C2_SPEED 116 #define CONFIG_SYS_MXC_I2C2_SPEED 100000 117 #endif 118 #ifndef CONFIG_SYS_MXC_I2C3_SPEED 119 #define CONFIG_SYS_MXC_I2C3_SPEED 100000 120 #endif 121 #ifndef CONFIG_SYS_MXC_I2C4_SPEED 122 #define CONFIG_SYS_MXC_I2C4_SPEED 100000 123 #endif 124 125 #ifndef CONFIG_SYS_MXC_I2C1_SLAVE 126 #define CONFIG_SYS_MXC_I2C1_SLAVE 0 127 #endif 128 #ifndef CONFIG_SYS_MXC_I2C2_SLAVE 129 #define CONFIG_SYS_MXC_I2C2_SLAVE 0 130 #endif 131 #ifndef CONFIG_SYS_MXC_I2C3_SLAVE 132 #define CONFIG_SYS_MXC_I2C3_SLAVE 0 133 #endif 134 #ifndef CONFIG_SYS_MXC_I2C4_SLAVE 135 #define CONFIG_SYS_MXC_I2C4_SLAVE 0 136 #endif 137 138 /* 139 * Calculate and set proper clock divider 140 */ 141 static uint8_t i2c_imx_get_clk(struct mxc_i2c_bus *i2c_bus, unsigned int rate) 142 { 143 unsigned int i2c_clk_rate; 144 unsigned int div; 145 u8 clk_div; 146 147 #if defined(CONFIG_MX31) 148 struct clock_control_regs *sc_regs = 149 (struct clock_control_regs *)CCM_BASE; 150 151 /* start the required I2C clock */ 152 writel(readl(&sc_regs->cgr0) | (3 << CONFIG_SYS_I2C_CLK_OFFSET), 153 &sc_regs->cgr0); 154 #endif 155 156 /* Divider value calculation */ 157 i2c_clk_rate = mxc_get_clock(MXC_I2C_CLK); 158 div = (i2c_clk_rate + rate - 1) / rate; 159 if (div < i2c_clk_div[0][0]) 160 clk_div = 0; 161 else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0]) 162 clk_div = ARRAY_SIZE(i2c_clk_div) - 1; 163 else 164 for (clk_div = 0; i2c_clk_div[clk_div][0] < div; clk_div++) 165 ; 166 167 /* Store divider value */ 168 return clk_div; 169 } 170 171 /* 172 * Set I2C Bus speed 173 */ 174 static int bus_i2c_set_bus_speed(struct mxc_i2c_bus *i2c_bus, int speed) 175 { 176 ulong base = i2c_bus->base; 177 bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false; 178 u8 clk_idx = i2c_imx_get_clk(i2c_bus, speed); 179 u8 idx = i2c_clk_div[clk_idx][1]; 180 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT; 181 182 if (!base) 183 return -ENODEV; 184 185 /* Store divider value */ 186 writeb(idx, base + (IFDR << reg_shift)); 187 188 /* Reset module */ 189 writeb(I2CR_IDIS, base + (I2CR << reg_shift)); 190 writeb(0, base + (I2SR << reg_shift)); 191 return 0; 192 } 193 194 #define ST_BUS_IDLE (0 | (I2SR_IBB << 8)) 195 #define ST_BUS_BUSY (I2SR_IBB | (I2SR_IBB << 8)) 196 #define ST_IIF (I2SR_IIF | (I2SR_IIF << 8)) 197 198 static int wait_for_sr_state(struct mxc_i2c_bus *i2c_bus, unsigned state) 199 { 200 unsigned sr; 201 ulong elapsed; 202 bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false; 203 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT; 204 ulong base = i2c_bus->base; 205 ulong start_time = get_timer(0); 206 for (;;) { 207 sr = readb(base + (I2SR << reg_shift)); 208 if (sr & I2SR_IAL) { 209 if (quirk) 210 writeb(sr | I2SR_IAL, base + 211 (I2SR << reg_shift)); 212 else 213 writeb(sr & ~I2SR_IAL, base + 214 (I2SR << reg_shift)); 215 printf("%s: Arbitration lost sr=%x cr=%x state=%x\n", 216 __func__, sr, readb(base + (I2CR << reg_shift)), 217 state); 218 return -ERESTART; 219 } 220 if ((sr & (state >> 8)) == (unsigned char)state) 221 return sr; 222 WATCHDOG_RESET(); 223 elapsed = get_timer(start_time); 224 if (elapsed > (CONFIG_SYS_HZ / 10)) /* .1 seconds */ 225 break; 226 } 227 printf("%s: failed sr=%x cr=%x state=%x\n", __func__, 228 sr, readb(base + (I2CR << reg_shift)), state); 229 return -ETIMEDOUT; 230 } 231 232 static int tx_byte(struct mxc_i2c_bus *i2c_bus, u8 byte) 233 { 234 int ret; 235 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ? 236 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT; 237 ulong base = i2c_bus->base; 238 239 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift)); 240 writeb(byte, base + (I2DR << reg_shift)); 241 242 ret = wait_for_sr_state(i2c_bus, ST_IIF); 243 if (ret < 0) 244 return ret; 245 if (ret & I2SR_RX_NO_AK) 246 return -ENODEV; 247 return 0; 248 } 249 250 /* 251 * Stub implementations for outer i2c slave operations. 252 */ 253 void __i2c_force_reset_slave(void) 254 { 255 } 256 void i2c_force_reset_slave(void) 257 __attribute__((weak, alias("__i2c_force_reset_slave"))); 258 259 /* 260 * Stop I2C transaction 261 */ 262 static void i2c_imx_stop(struct mxc_i2c_bus *i2c_bus) 263 { 264 int ret; 265 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ? 266 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT; 267 ulong base = i2c_bus->base; 268 unsigned int temp = readb(base + (I2CR << reg_shift)); 269 270 temp &= ~(I2CR_MSTA | I2CR_MTX); 271 writeb(temp, base + (I2CR << reg_shift)); 272 ret = wait_for_sr_state(i2c_bus, ST_BUS_IDLE); 273 if (ret < 0) 274 printf("%s:trigger stop failed\n", __func__); 275 } 276 277 /* 278 * Send start signal, chip address and 279 * write register address 280 */ 281 static int i2c_init_transfer_(struct mxc_i2c_bus *i2c_bus, u8 chip, 282 u32 addr, int alen) 283 { 284 unsigned int temp; 285 int ret; 286 bool quirk = i2c_bus->driver_data & I2C_QUIRK_FLAG ? true : false; 287 ulong base = i2c_bus->base; 288 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT; 289 290 /* Reset i2c slave */ 291 i2c_force_reset_slave(); 292 293 /* Enable I2C controller */ 294 if (quirk) 295 ret = readb(base + (I2CR << reg_shift)) & I2CR_IDIS; 296 else 297 ret = !(readb(base + (I2CR << reg_shift)) & I2CR_IEN); 298 299 if (ret) { 300 writeb(I2CR_IEN, base + (I2CR << reg_shift)); 301 /* Wait for controller to be stable */ 302 udelay(50); 303 } 304 305 if (readb(base + (IADR << reg_shift)) == (chip << 1)) 306 writeb((chip << 1) ^ 2, base + (IADR << reg_shift)); 307 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift)); 308 ret = wait_for_sr_state(i2c_bus, ST_BUS_IDLE); 309 if (ret < 0) 310 return ret; 311 312 /* Start I2C transaction */ 313 temp = readb(base + (I2CR << reg_shift)); 314 temp |= I2CR_MSTA; 315 writeb(temp, base + (I2CR << reg_shift)); 316 317 ret = wait_for_sr_state(i2c_bus, ST_BUS_BUSY); 318 if (ret < 0) 319 return ret; 320 321 temp |= I2CR_MTX | I2CR_TX_NO_AK; 322 writeb(temp, base + (I2CR << reg_shift)); 323 324 /* write slave address */ 325 ret = tx_byte(i2c_bus, chip << 1); 326 if (ret < 0) 327 return ret; 328 329 while (alen--) { 330 ret = tx_byte(i2c_bus, (addr >> (alen * 8)) & 0xff); 331 if (ret < 0) 332 return ret; 333 } 334 return 0; 335 } 336 337 #ifndef CONFIG_DM_I2C 338 int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus) 339 { 340 if (i2c_bus && i2c_bus->idle_bus_fn) 341 return i2c_bus->idle_bus_fn(i2c_bus->idle_bus_data); 342 return 0; 343 } 344 #else 345 /* 346 * See Linux Documentation/devicetree/bindings/i2c/i2c-imx.txt 347 * " 348 * scl-gpios: specify the gpio related to SCL pin 349 * sda-gpios: specify the gpio related to SDA pin 350 * add pinctrl to configure i2c pins to gpio function for i2c 351 * bus recovery, call it "gpio" state 352 * " 353 * 354 * The i2c_idle_bus is an implementation following Linux Kernel. 355 */ 356 int i2c_idle_bus(struct mxc_i2c_bus *i2c_bus) 357 { 358 struct udevice *bus = i2c_bus->bus; 359 struct gpio_desc *scl_gpio = &i2c_bus->scl_gpio; 360 struct gpio_desc *sda_gpio = &i2c_bus->sda_gpio; 361 int sda, scl; 362 int i, ret = 0; 363 ulong elapsed, start_time; 364 365 if (pinctrl_select_state(bus, "gpio")) { 366 dev_dbg(bus, "Can not to switch to use gpio pinmux\n"); 367 /* 368 * GPIO pinctrl for i2c force idle is not a must, 369 * but it is strongly recommended to be used. 370 * Because it can help you to recover from bad 371 * i2c bus state. Do not return failure, because 372 * it is not a must. 373 */ 374 return 0; 375 } 376 377 dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN); 378 dm_gpio_set_dir_flags(sda_gpio, GPIOD_IS_IN); 379 scl = dm_gpio_get_value(scl_gpio); 380 sda = dm_gpio_get_value(sda_gpio); 381 382 if ((sda & scl) == 1) 383 goto exit; /* Bus is idle already */ 384 385 /* Send high and low on the SCL line */ 386 for (i = 0; i < 9; i++) { 387 dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_OUT); 388 dm_gpio_set_value(scl_gpio, 0); 389 udelay(50); 390 dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN); 391 udelay(50); 392 } 393 start_time = get_timer(0); 394 for (;;) { 395 dm_gpio_set_dir_flags(scl_gpio, GPIOD_IS_IN); 396 dm_gpio_set_dir_flags(sda_gpio, GPIOD_IS_IN); 397 scl = dm_gpio_get_value(scl_gpio); 398 sda = dm_gpio_get_value(sda_gpio); 399 if ((sda & scl) == 1) 400 break; 401 WATCHDOG_RESET(); 402 elapsed = get_timer(start_time); 403 if (elapsed > (CONFIG_SYS_HZ / 5)) { /* .2 seconds */ 404 ret = -EBUSY; 405 printf("%s: failed to clear bus, sda=%d scl=%d\n", __func__, sda, scl); 406 break; 407 } 408 } 409 410 exit: 411 pinctrl_select_state(bus, "default"); 412 return ret; 413 } 414 #endif 415 416 static int i2c_init_transfer(struct mxc_i2c_bus *i2c_bus, u8 chip, 417 u32 addr, int alen) 418 { 419 int retry; 420 int ret; 421 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ? 422 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT; 423 424 if (!i2c_bus->base) 425 return -ENODEV; 426 427 for (retry = 0; retry < 3; retry++) { 428 ret = i2c_init_transfer_(i2c_bus, chip, addr, alen); 429 if (ret >= 0) 430 return 0; 431 i2c_imx_stop(i2c_bus); 432 if (ret == -ENODEV) 433 return ret; 434 435 printf("%s: failed for chip 0x%x retry=%d\n", __func__, chip, 436 retry); 437 if (ret != -ERESTART) 438 /* Disable controller */ 439 writeb(I2CR_IDIS, i2c_bus->base + (I2CR << reg_shift)); 440 udelay(100); 441 if (i2c_idle_bus(i2c_bus) < 0) 442 break; 443 } 444 printf("%s: give up i2c_regs=0x%lx\n", __func__, i2c_bus->base); 445 return ret; 446 } 447 448 449 static int i2c_write_data(struct mxc_i2c_bus *i2c_bus, u8 chip, const u8 *buf, 450 int len) 451 { 452 int i, ret = 0; 453 454 debug("i2c_write_data: chip=0x%x, len=0x%x\n", chip, len); 455 debug("write_data: "); 456 /* use rc for counter */ 457 for (i = 0; i < len; ++i) 458 debug(" 0x%02x", buf[i]); 459 debug("\n"); 460 461 for (i = 0; i < len; i++) { 462 ret = tx_byte(i2c_bus, buf[i]); 463 if (ret < 0) { 464 debug("i2c_write_data(): rc=%d\n", ret); 465 break; 466 } 467 } 468 469 return ret; 470 } 471 472 static int i2c_read_data(struct mxc_i2c_bus *i2c_bus, uchar chip, uchar *buf, 473 int len) 474 { 475 int ret; 476 unsigned int temp; 477 int i; 478 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ? 479 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT; 480 ulong base = i2c_bus->base; 481 482 debug("i2c_read_data: chip=0x%x, len=0x%x\n", chip, len); 483 484 /* setup bus to read data */ 485 temp = readb(base + (I2CR << reg_shift)); 486 temp &= ~(I2CR_MTX | I2CR_TX_NO_AK); 487 if (len == 1) 488 temp |= I2CR_TX_NO_AK; 489 writeb(temp, base + (I2CR << reg_shift)); 490 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift)); 491 /* dummy read to clear ICF */ 492 readb(base + (I2DR << reg_shift)); 493 494 /* read data */ 495 for (i = 0; i < len; i++) { 496 ret = wait_for_sr_state(i2c_bus, ST_IIF); 497 if (ret < 0) { 498 debug("i2c_read_data(): ret=%d\n", ret); 499 i2c_imx_stop(i2c_bus); 500 return ret; 501 } 502 503 /* 504 * It must generate STOP before read I2DR to prevent 505 * controller from generating another clock cycle 506 */ 507 if (i == (len - 1)) { 508 i2c_imx_stop(i2c_bus); 509 } else if (i == (len - 2)) { 510 temp = readb(base + (I2CR << reg_shift)); 511 temp |= I2CR_TX_NO_AK; 512 writeb(temp, base + (I2CR << reg_shift)); 513 } 514 writeb(I2SR_IIF_CLEAR, base + (I2SR << reg_shift)); 515 buf[i] = readb(base + (I2DR << reg_shift)); 516 } 517 518 /* reuse ret for counter*/ 519 for (ret = 0; ret < len; ++ret) 520 debug(" 0x%02x", buf[ret]); 521 debug("\n"); 522 523 i2c_imx_stop(i2c_bus); 524 return 0; 525 } 526 527 #ifndef CONFIG_DM_I2C 528 /* 529 * Read data from I2C device 530 */ 531 static int bus_i2c_read(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr, 532 int alen, u8 *buf, int len) 533 { 534 int ret = 0; 535 u32 temp; 536 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ? 537 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT; 538 ulong base = i2c_bus->base; 539 540 ret = i2c_init_transfer(i2c_bus, chip, addr, alen); 541 if (ret < 0) 542 return ret; 543 544 temp = readb(base + (I2CR << reg_shift)); 545 temp |= I2CR_RSTA; 546 writeb(temp, base + (I2CR << reg_shift)); 547 548 ret = tx_byte(i2c_bus, (chip << 1) | 1); 549 if (ret < 0) { 550 i2c_imx_stop(i2c_bus); 551 return ret; 552 } 553 554 ret = i2c_read_data(i2c_bus, chip, buf, len); 555 556 i2c_imx_stop(i2c_bus); 557 return ret; 558 } 559 560 /* 561 * Write data to I2C device 562 */ 563 static int bus_i2c_write(struct mxc_i2c_bus *i2c_bus, u8 chip, u32 addr, 564 int alen, const u8 *buf, int len) 565 { 566 int ret = 0; 567 568 ret = i2c_init_transfer(i2c_bus, chip, addr, alen); 569 if (ret < 0) 570 return ret; 571 572 ret = i2c_write_data(i2c_bus, chip, buf, len); 573 574 i2c_imx_stop(i2c_bus); 575 576 return ret; 577 } 578 579 #if !defined(I2C2_BASE_ADDR) 580 #define I2C2_BASE_ADDR 0 581 #endif 582 583 #if !defined(I2C3_BASE_ADDR) 584 #define I2C3_BASE_ADDR 0 585 #endif 586 587 #if !defined(I2C4_BASE_ADDR) 588 #define I2C4_BASE_ADDR 0 589 #endif 590 591 static struct mxc_i2c_bus mxc_i2c_buses[] = { 592 #if defined(CONFIG_ARCH_LS1021A) || defined(CONFIG_VF610) || \ 593 defined(CONFIG_FSL_LAYERSCAPE) 594 { 0, I2C1_BASE_ADDR, I2C_QUIRK_FLAG }, 595 { 1, I2C2_BASE_ADDR, I2C_QUIRK_FLAG }, 596 { 2, I2C3_BASE_ADDR, I2C_QUIRK_FLAG }, 597 { 3, I2C4_BASE_ADDR, I2C_QUIRK_FLAG }, 598 #else 599 { 0, I2C1_BASE_ADDR, 0 }, 600 { 1, I2C2_BASE_ADDR, 0 }, 601 { 2, I2C3_BASE_ADDR, 0 }, 602 { 3, I2C4_BASE_ADDR, 0 }, 603 #endif 604 }; 605 606 struct mxc_i2c_bus *i2c_get_base(struct i2c_adapter *adap) 607 { 608 return &mxc_i2c_buses[adap->hwadapnr]; 609 } 610 611 static int mxc_i2c_read(struct i2c_adapter *adap, uint8_t chip, 612 uint addr, int alen, uint8_t *buffer, 613 int len) 614 { 615 return bus_i2c_read(i2c_get_base(adap), chip, addr, alen, buffer, len); 616 } 617 618 static int mxc_i2c_write(struct i2c_adapter *adap, uint8_t chip, 619 uint addr, int alen, uint8_t *buffer, 620 int len) 621 { 622 return bus_i2c_write(i2c_get_base(adap), chip, addr, alen, buffer, len); 623 } 624 625 /* 626 * Test if a chip at a given address responds (probe the chip) 627 */ 628 static int mxc_i2c_probe(struct i2c_adapter *adap, uint8_t chip) 629 { 630 return bus_i2c_write(i2c_get_base(adap), chip, 0, 0, NULL, 0); 631 } 632 633 int __enable_i2c_clk(unsigned char enable, unsigned i2c_num) 634 { 635 return 1; 636 } 637 int enable_i2c_clk(unsigned char enable, unsigned i2c_num) 638 __attribute__((weak, alias("__enable_i2c_clk"))); 639 640 void bus_i2c_init(int index, int speed, int unused, 641 int (*idle_bus_fn)(void *p), void *idle_bus_data) 642 { 643 int ret; 644 645 if (index >= ARRAY_SIZE(mxc_i2c_buses)) { 646 debug("Error i2c index\n"); 647 return; 648 } 649 650 /* 651 * Warning: Be careful to allow the assignment to a static 652 * variable here. This function could be called while U-Boot is 653 * still running in flash memory. So such assignment is equal 654 * to write data to flash without erasing. 655 */ 656 if (idle_bus_fn) 657 mxc_i2c_buses[index].idle_bus_fn = idle_bus_fn; 658 if (idle_bus_data) 659 mxc_i2c_buses[index].idle_bus_data = idle_bus_data; 660 661 ret = enable_i2c_clk(1, index); 662 if (ret < 0) { 663 debug("I2C-%d clk fail to enable.\n", index); 664 return; 665 } 666 667 bus_i2c_set_bus_speed(&mxc_i2c_buses[index], speed); 668 } 669 670 /* 671 * Early init I2C for prepare read the clk through I2C. 672 */ 673 void i2c_early_init_f(void) 674 { 675 ulong base = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].base; 676 bool quirk = mxc_i2c_buses[I2C_EARLY_INIT_INDEX].driver_data 677 & I2C_QUIRK_FLAG ? true : false; 678 int reg_shift = quirk ? VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT; 679 680 /* Set I2C divider value */ 681 writeb(I2C_IFDR_DIV_CONSERVATIVE, base + (IFDR << reg_shift)); 682 /* Reset module */ 683 writeb(I2CR_IDIS, base + (I2CR << reg_shift)); 684 writeb(0, base + (I2SR << reg_shift)); 685 /* Enable I2C */ 686 writeb(I2CR_IEN, base + (I2CR << reg_shift)); 687 } 688 689 /* 690 * Init I2C Bus 691 */ 692 static void mxc_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr) 693 { 694 bus_i2c_init(adap->hwadapnr, speed, slaveaddr, NULL, NULL); 695 } 696 697 /* 698 * Set I2C Speed 699 */ 700 static u32 mxc_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed) 701 { 702 return bus_i2c_set_bus_speed(i2c_get_base(adap), speed); 703 } 704 705 /* 706 * Register mxc i2c adapters 707 */ 708 #ifdef CONFIG_SYS_I2C_MXC_I2C1 709 U_BOOT_I2C_ADAP_COMPLETE(mxc0, mxc_i2c_init, mxc_i2c_probe, 710 mxc_i2c_read, mxc_i2c_write, 711 mxc_i2c_set_bus_speed, 712 CONFIG_SYS_MXC_I2C1_SPEED, 713 CONFIG_SYS_MXC_I2C1_SLAVE, 0) 714 #endif 715 716 #ifdef CONFIG_SYS_I2C_MXC_I2C2 717 U_BOOT_I2C_ADAP_COMPLETE(mxc1, mxc_i2c_init, mxc_i2c_probe, 718 mxc_i2c_read, mxc_i2c_write, 719 mxc_i2c_set_bus_speed, 720 CONFIG_SYS_MXC_I2C2_SPEED, 721 CONFIG_SYS_MXC_I2C2_SLAVE, 1) 722 #endif 723 724 #ifdef CONFIG_SYS_I2C_MXC_I2C3 725 U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe, 726 mxc_i2c_read, mxc_i2c_write, 727 mxc_i2c_set_bus_speed, 728 CONFIG_SYS_MXC_I2C3_SPEED, 729 CONFIG_SYS_MXC_I2C3_SLAVE, 2) 730 #endif 731 732 #ifdef CONFIG_SYS_I2C_MXC_I2C4 733 U_BOOT_I2C_ADAP_COMPLETE(mxc3, mxc_i2c_init, mxc_i2c_probe, 734 mxc_i2c_read, mxc_i2c_write, 735 mxc_i2c_set_bus_speed, 736 CONFIG_SYS_MXC_I2C4_SPEED, 737 CONFIG_SYS_MXC_I2C4_SLAVE, 3) 738 #endif 739 740 #else 741 742 static int mxc_i2c_set_bus_speed(struct udevice *bus, unsigned int speed) 743 { 744 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus); 745 746 return bus_i2c_set_bus_speed(i2c_bus, speed); 747 } 748 749 static int mxc_i2c_probe(struct udevice *bus) 750 { 751 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus); 752 const void *fdt = gd->fdt_blob; 753 int node = dev_of_offset(bus); 754 fdt_addr_t addr; 755 int ret, ret2; 756 757 i2c_bus->driver_data = dev_get_driver_data(bus); 758 759 addr = dev_get_addr(bus); 760 if (addr == FDT_ADDR_T_NONE) 761 return -ENODEV; 762 763 i2c_bus->base = addr; 764 i2c_bus->index = bus->seq; 765 i2c_bus->bus = bus; 766 767 /* Enable clk */ 768 ret = enable_i2c_clk(1, bus->seq); 769 if (ret < 0) 770 return ret; 771 772 /* 773 * See Documentation/devicetree/bindings/i2c/i2c-imx.txt 774 * Use gpio to force bus idle when necessary. 775 */ 776 ret = fdt_stringlist_search(fdt, node, "pinctrl-names", "gpio"); 777 if (ret < 0) { 778 debug("i2c bus %d at 0x%2lx, no gpio pinctrl state.\n", bus->seq, i2c_bus->base); 779 } else { 780 ret = gpio_request_by_name_nodev(fdt, node, "scl-gpios", 781 0, &i2c_bus->scl_gpio, 782 GPIOD_IS_OUT); 783 ret2 = gpio_request_by_name_nodev(fdt, node, "sda-gpios", 784 0, &i2c_bus->sda_gpio, 785 GPIOD_IS_OUT); 786 if (!dm_gpio_is_valid(&i2c_bus->sda_gpio) | 787 !dm_gpio_is_valid(&i2c_bus->scl_gpio) | 788 ret | ret2) { 789 dev_err(dev, "i2c bus %d at %lu, fail to request scl/sda gpio\n", bus->seq, i2c_bus->base); 790 return -ENODEV; 791 } 792 } 793 794 ret = i2c_idle_bus(i2c_bus); 795 if (ret < 0) { 796 /* Disable clk */ 797 enable_i2c_clk(0, bus->seq); 798 return ret; 799 } 800 801 /* 802 * Pinmux settings are in board file now, until pinmux is supported, 803 * we can set pinmux here in probe function. 804 */ 805 806 debug("i2c : controller bus %d at %lu , speed %d: ", 807 bus->seq, i2c_bus->base, 808 i2c_bus->speed); 809 810 return 0; 811 } 812 813 static int mxc_i2c_probe_chip(struct udevice *bus, u32 chip_addr, 814 u32 chip_flags) 815 { 816 int ret; 817 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus); 818 819 ret = i2c_init_transfer(i2c_bus, chip_addr, 0, 0); 820 if (ret < 0) { 821 debug("%s failed, ret = %d\n", __func__, ret); 822 return ret; 823 } 824 825 i2c_imx_stop(i2c_bus); 826 827 return 0; 828 } 829 830 static int mxc_i2c_xfer(struct udevice *bus, struct i2c_msg *msg, int nmsgs) 831 { 832 struct mxc_i2c_bus *i2c_bus = dev_get_priv(bus); 833 int ret = 0; 834 ulong base = i2c_bus->base; 835 int reg_shift = i2c_bus->driver_data & I2C_QUIRK_FLAG ? 836 VF610_I2C_REGSHIFT : IMX_I2C_REGSHIFT; 837 838 /* 839 * Here the 3rd parameter addr and the 4th one alen are set to 0, 840 * because here we only want to send out chip address. The register 841 * address is wrapped in msg. 842 */ 843 ret = i2c_init_transfer(i2c_bus, msg->addr, 0, 0); 844 if (ret < 0) { 845 debug("i2c_init_transfer error: %d\n", ret); 846 return ret; 847 } 848 849 for (; nmsgs > 0; nmsgs--, msg++) { 850 bool next_is_read = nmsgs > 1 && (msg[1].flags & I2C_M_RD); 851 debug("i2c_xfer: chip=0x%x, len=0x%x\n", msg->addr, msg->len); 852 if (msg->flags & I2C_M_RD) 853 ret = i2c_read_data(i2c_bus, msg->addr, msg->buf, 854 msg->len); 855 else { 856 ret = i2c_write_data(i2c_bus, msg->addr, msg->buf, 857 msg->len); 858 if (ret) 859 break; 860 if (next_is_read) { 861 /* Reuse ret */ 862 ret = readb(base + (I2CR << reg_shift)); 863 ret |= I2CR_RSTA; 864 writeb(ret, base + (I2CR << reg_shift)); 865 866 ret = tx_byte(i2c_bus, (msg->addr << 1) | 1); 867 if (ret < 0) { 868 i2c_imx_stop(i2c_bus); 869 break; 870 } 871 } 872 } 873 } 874 875 if (ret) 876 debug("i2c_write: error sending\n"); 877 878 i2c_imx_stop(i2c_bus); 879 880 return ret; 881 } 882 883 static const struct dm_i2c_ops mxc_i2c_ops = { 884 .xfer = mxc_i2c_xfer, 885 .probe_chip = mxc_i2c_probe_chip, 886 .set_bus_speed = mxc_i2c_set_bus_speed, 887 }; 888 889 static const struct udevice_id mxc_i2c_ids[] = { 890 { .compatible = "fsl,imx21-i2c", }, 891 { .compatible = "fsl,vf610-i2c", .data = I2C_QUIRK_FLAG, }, 892 {} 893 }; 894 895 U_BOOT_DRIVER(i2c_mxc) = { 896 .name = "i2c_mxc", 897 .id = UCLASS_I2C, 898 .of_match = mxc_i2c_ids, 899 .probe = mxc_i2c_probe, 900 .priv_auto_alloc_size = sizeof(struct mxc_i2c_bus), 901 .ops = &mxc_i2c_ops, 902 }; 903 #endif 904