1 /* 2 * i2c driver for Freescale i.MX series 3 * 4 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> 5 * (c) 2011 Marek Vasut <marek.vasut@gmail.com> 6 * 7 * Based on i2c-imx.c from linux kernel: 8 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de> 9 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de> 10 * Copyright (C) 2007 RightHand Technologies, Inc. 11 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt> 12 * 13 * 14 * SPDX-License-Identifier: GPL-2.0+ 15 */ 16 17 #include <common.h> 18 #include <asm/arch/clock.h> 19 #include <asm/arch/imx-regs.h> 20 #include <asm/errno.h> 21 #include <asm/io.h> 22 #include <i2c.h> 23 #include <watchdog.h> 24 25 #ifdef I2C_QUIRK_REG 26 struct mxc_i2c_regs { 27 uint8_t iadr; 28 uint8_t ifdr; 29 uint8_t i2cr; 30 uint8_t i2sr; 31 uint8_t i2dr; 32 }; 33 #else 34 struct mxc_i2c_regs { 35 uint32_t iadr; 36 uint32_t ifdr; 37 uint32_t i2cr; 38 uint32_t i2sr; 39 uint32_t i2dr; 40 }; 41 #endif 42 43 #define I2CR_IIEN (1 << 6) 44 #define I2CR_MSTA (1 << 5) 45 #define I2CR_MTX (1 << 4) 46 #define I2CR_TX_NO_AK (1 << 3) 47 #define I2CR_RSTA (1 << 2) 48 49 #define I2SR_ICF (1 << 7) 50 #define I2SR_IBB (1 << 5) 51 #define I2SR_IAL (1 << 4) 52 #define I2SR_IIF (1 << 1) 53 #define I2SR_RX_NO_AK (1 << 0) 54 55 #ifdef I2C_QUIRK_REG 56 #define I2CR_IEN (0 << 7) 57 #define I2CR_IDIS (1 << 7) 58 #define I2SR_IIF_CLEAR (1 << 1) 59 #else 60 #define I2CR_IEN (1 << 7) 61 #define I2CR_IDIS (0 << 7) 62 #define I2SR_IIF_CLEAR (0 << 1) 63 #endif 64 65 #if defined(CONFIG_HARD_I2C) && !defined(CONFIG_SYS_I2C_BASE) 66 #error "define CONFIG_SYS_I2C_BASE to use the mxc_i2c driver" 67 #endif 68 69 #ifdef I2C_QUIRK_REG 70 static u16 i2c_clk_div[60][2] = { 71 { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 }, 72 { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 }, 73 { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D }, 74 { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 }, 75 { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 }, 76 { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 }, 77 { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 }, 78 { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 }, 79 { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 }, 80 { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B }, 81 { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 }, 82 { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 }, 83 { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B }, 84 { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A }, 85 { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E }, 86 }; 87 #else 88 static u16 i2c_clk_div[50][2] = { 89 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 }, 90 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 }, 91 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 }, 92 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B }, 93 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A }, 94 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 }, 95 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 }, 96 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 }, 97 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 }, 98 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B }, 99 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E }, 100 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D }, 101 { 3072, 0x1E }, { 3840, 0x1F } 102 }; 103 #endif 104 105 106 #ifndef CONFIG_SYS_MXC_I2C1_SPEED 107 #define CONFIG_SYS_MXC_I2C1_SPEED 100000 108 #endif 109 #ifndef CONFIG_SYS_MXC_I2C2_SPEED 110 #define CONFIG_SYS_MXC_I2C2_SPEED 100000 111 #endif 112 #ifndef CONFIG_SYS_MXC_I2C3_SPEED 113 #define CONFIG_SYS_MXC_I2C3_SPEED 100000 114 #endif 115 116 #ifndef CONFIG_SYS_MXC_I2C1_SLAVE 117 #define CONFIG_SYS_MXC_I2C1_SLAVE 0 118 #endif 119 #ifndef CONFIG_SYS_MXC_I2C2_SLAVE 120 #define CONFIG_SYS_MXC_I2C2_SLAVE 0 121 #endif 122 #ifndef CONFIG_SYS_MXC_I2C3_SLAVE 123 #define CONFIG_SYS_MXC_I2C3_SLAVE 0 124 #endif 125 126 127 /* 128 * Calculate and set proper clock divider 129 */ 130 static uint8_t i2c_imx_get_clk(unsigned int rate) 131 { 132 unsigned int i2c_clk_rate; 133 unsigned int div; 134 u8 clk_div; 135 136 #if defined(CONFIG_MX31) 137 struct clock_control_regs *sc_regs = 138 (struct clock_control_regs *)CCM_BASE; 139 140 /* start the required I2C clock */ 141 writel(readl(&sc_regs->cgr0) | (3 << CONFIG_SYS_I2C_CLK_OFFSET), 142 &sc_regs->cgr0); 143 #endif 144 145 /* Divider value calculation */ 146 i2c_clk_rate = mxc_get_clock(MXC_I2C_CLK); 147 div = (i2c_clk_rate + rate - 1) / rate; 148 if (div < i2c_clk_div[0][0]) 149 clk_div = 0; 150 else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0]) 151 clk_div = ARRAY_SIZE(i2c_clk_div) - 1; 152 else 153 for (clk_div = 0; i2c_clk_div[clk_div][0] < div; clk_div++) 154 ; 155 156 /* Store divider value */ 157 return clk_div; 158 } 159 160 /* 161 * Set I2C Bus speed 162 */ 163 static int bus_i2c_set_bus_speed(void *base, int speed) 164 { 165 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)base; 166 u8 clk_idx = i2c_imx_get_clk(speed); 167 u8 idx = i2c_clk_div[clk_idx][1]; 168 169 /* Store divider value */ 170 writeb(idx, &i2c_regs->ifdr); 171 172 /* Reset module */ 173 writeb(I2CR_IDIS, &i2c_regs->i2cr); 174 writeb(0, &i2c_regs->i2sr); 175 return 0; 176 } 177 178 #define ST_BUS_IDLE (0 | (I2SR_IBB << 8)) 179 #define ST_BUS_BUSY (I2SR_IBB | (I2SR_IBB << 8)) 180 #define ST_IIF (I2SR_IIF | (I2SR_IIF << 8)) 181 182 static int wait_for_sr_state(struct mxc_i2c_regs *i2c_regs, unsigned state) 183 { 184 unsigned sr; 185 ulong elapsed; 186 ulong start_time = get_timer(0); 187 for (;;) { 188 sr = readb(&i2c_regs->i2sr); 189 if (sr & I2SR_IAL) { 190 #ifdef I2C_QUIRK_REG 191 writeb(sr | I2SR_IAL, &i2c_regs->i2sr); 192 #else 193 writeb(sr & ~I2SR_IAL, &i2c_regs->i2sr); 194 #endif 195 printf("%s: Arbitration lost sr=%x cr=%x state=%x\n", 196 __func__, sr, readb(&i2c_regs->i2cr), state); 197 return -ERESTART; 198 } 199 if ((sr & (state >> 8)) == (unsigned char)state) 200 return sr; 201 WATCHDOG_RESET(); 202 elapsed = get_timer(start_time); 203 if (elapsed > (CONFIG_SYS_HZ / 10)) /* .1 seconds */ 204 break; 205 } 206 printf("%s: failed sr=%x cr=%x state=%x\n", __func__, 207 sr, readb(&i2c_regs->i2cr), state); 208 return -ETIMEDOUT; 209 } 210 211 static int tx_byte(struct mxc_i2c_regs *i2c_regs, u8 byte) 212 { 213 int ret; 214 215 writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr); 216 writeb(byte, &i2c_regs->i2dr); 217 ret = wait_for_sr_state(i2c_regs, ST_IIF); 218 if (ret < 0) 219 return ret; 220 if (ret & I2SR_RX_NO_AK) 221 return -ENODEV; 222 return 0; 223 } 224 225 /* 226 * Stop I2C transaction 227 */ 228 static void i2c_imx_stop(struct mxc_i2c_regs *i2c_regs) 229 { 230 int ret; 231 unsigned int temp = readb(&i2c_regs->i2cr); 232 233 temp &= ~(I2CR_MSTA | I2CR_MTX); 234 writeb(temp, &i2c_regs->i2cr); 235 ret = wait_for_sr_state(i2c_regs, ST_BUS_IDLE); 236 if (ret < 0) 237 printf("%s:trigger stop failed\n", __func__); 238 } 239 240 /* 241 * Send start signal, chip address and 242 * write register address 243 */ 244 static int i2c_init_transfer_(struct mxc_i2c_regs *i2c_regs, 245 uchar chip, uint addr, int alen) 246 { 247 unsigned int temp; 248 int ret; 249 250 /* Enable I2C controller */ 251 #ifdef I2C_QUIRK_REG 252 if (readb(&i2c_regs->i2cr) & I2CR_IDIS) { 253 #else 254 if (!(readb(&i2c_regs->i2cr) & I2CR_IEN)) { 255 #endif 256 writeb(I2CR_IEN, &i2c_regs->i2cr); 257 /* Wait for controller to be stable */ 258 udelay(50); 259 } 260 if (readb(&i2c_regs->iadr) == (chip << 1)) 261 writeb((chip << 1) ^ 2, &i2c_regs->iadr); 262 writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr); 263 ret = wait_for_sr_state(i2c_regs, ST_BUS_IDLE); 264 if (ret < 0) 265 return ret; 266 267 /* Start I2C transaction */ 268 temp = readb(&i2c_regs->i2cr); 269 temp |= I2CR_MSTA; 270 writeb(temp, &i2c_regs->i2cr); 271 272 ret = wait_for_sr_state(i2c_regs, ST_BUS_BUSY); 273 if (ret < 0) 274 return ret; 275 276 temp |= I2CR_MTX | I2CR_TX_NO_AK; 277 writeb(temp, &i2c_regs->i2cr); 278 279 /* write slave address */ 280 ret = tx_byte(i2c_regs, chip << 1); 281 if (ret < 0) 282 return ret; 283 284 while (alen--) { 285 ret = tx_byte(i2c_regs, (addr >> (alen * 8)) & 0xff); 286 if (ret < 0) 287 return ret; 288 } 289 return 0; 290 } 291 292 static int i2c_idle_bus(void *base); 293 294 static int i2c_init_transfer(struct mxc_i2c_regs *i2c_regs, 295 uchar chip, uint addr, int alen) 296 { 297 int retry; 298 int ret; 299 for (retry = 0; retry < 3; retry++) { 300 ret = i2c_init_transfer_(i2c_regs, chip, addr, alen); 301 if (ret >= 0) 302 return 0; 303 i2c_imx_stop(i2c_regs); 304 if (ret == -ENODEV) 305 return ret; 306 307 printf("%s: failed for chip 0x%x retry=%d\n", __func__, chip, 308 retry); 309 if (ret != -ERESTART) 310 /* Disable controller */ 311 writeb(I2CR_IDIS, &i2c_regs->i2cr); 312 udelay(100); 313 if (i2c_idle_bus(i2c_regs) < 0) 314 break; 315 } 316 printf("%s: give up i2c_regs=%p\n", __func__, i2c_regs); 317 return ret; 318 } 319 320 /* 321 * Read data from I2C device 322 */ 323 int bus_i2c_read(void *base, uchar chip, uint addr, int alen, uchar *buf, 324 int len) 325 { 326 int ret; 327 unsigned int temp; 328 int i; 329 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)base; 330 331 ret = i2c_init_transfer(i2c_regs, chip, addr, alen); 332 if (ret < 0) 333 return ret; 334 335 temp = readb(&i2c_regs->i2cr); 336 temp |= I2CR_RSTA; 337 writeb(temp, &i2c_regs->i2cr); 338 339 ret = tx_byte(i2c_regs, (chip << 1) | 1); 340 if (ret < 0) { 341 i2c_imx_stop(i2c_regs); 342 return ret; 343 } 344 345 /* setup bus to read data */ 346 temp = readb(&i2c_regs->i2cr); 347 temp &= ~(I2CR_MTX | I2CR_TX_NO_AK); 348 if (len == 1) 349 temp |= I2CR_TX_NO_AK; 350 writeb(temp, &i2c_regs->i2cr); 351 writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr); 352 readb(&i2c_regs->i2dr); /* dummy read to clear ICF */ 353 354 /* read data */ 355 for (i = 0; i < len; i++) { 356 ret = wait_for_sr_state(i2c_regs, ST_IIF); 357 if (ret < 0) { 358 i2c_imx_stop(i2c_regs); 359 return ret; 360 } 361 362 /* 363 * It must generate STOP before read I2DR to prevent 364 * controller from generating another clock cycle 365 */ 366 if (i == (len - 1)) { 367 i2c_imx_stop(i2c_regs); 368 } else if (i == (len - 2)) { 369 temp = readb(&i2c_regs->i2cr); 370 temp |= I2CR_TX_NO_AK; 371 writeb(temp, &i2c_regs->i2cr); 372 } 373 writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr); 374 buf[i] = readb(&i2c_regs->i2dr); 375 } 376 i2c_imx_stop(i2c_regs); 377 return 0; 378 } 379 380 /* 381 * Write data to I2C device 382 */ 383 int bus_i2c_write(void *base, uchar chip, uint addr, int alen, 384 const uchar *buf, int len) 385 { 386 int ret; 387 int i; 388 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)base; 389 390 ret = i2c_init_transfer(i2c_regs, chip, addr, alen); 391 if (ret < 0) 392 return ret; 393 394 for (i = 0; i < len; i++) { 395 ret = tx_byte(i2c_regs, buf[i]); 396 if (ret < 0) 397 break; 398 } 399 i2c_imx_stop(i2c_regs); 400 return ret; 401 } 402 403 struct i2c_parms { 404 void *base; 405 void *idle_bus_data; 406 int (*idle_bus_fn)(void *p); 407 }; 408 409 struct sram_data { 410 unsigned curr_i2c_bus; 411 struct i2c_parms i2c_data[3]; 412 }; 413 414 /* 415 * For SPL boot some boards need i2c before SDRAM is initialized so force 416 * variables to live in SRAM 417 */ 418 static struct sram_data __attribute__((section(".data"))) srdata; 419 420 static void * const i2c_bases[] = { 421 #if defined(CONFIG_MX25) 422 (void *)IMX_I2C_BASE, 423 (void *)IMX_I2C2_BASE, 424 (void *)IMX_I2C3_BASE 425 #elif defined(CONFIG_MX27) 426 (void *)IMX_I2C1_BASE, 427 (void *)IMX_I2C2_BASE 428 #elif defined(CONFIG_MX31) || defined(CONFIG_MX35) || \ 429 defined(CONFIG_MX51) || defined(CONFIG_MX53) || \ 430 defined(CONFIG_MX6) 431 (void *)I2C1_BASE_ADDR, 432 (void *)I2C2_BASE_ADDR, 433 (void *)I2C3_BASE_ADDR 434 #elif defined(CONFIG_VF610) 435 (void *)I2C0_BASE_ADDR 436 #else 437 #error "architecture not supported" 438 #endif 439 }; 440 441 void *i2c_get_base(struct i2c_adapter *adap) 442 { 443 return i2c_bases[adap->hwadapnr]; 444 } 445 446 static struct i2c_parms *i2c_get_parms(void *base) 447 { 448 int i = 0; 449 struct i2c_parms *p = srdata.i2c_data; 450 while (i < ARRAY_SIZE(srdata.i2c_data)) { 451 if (p->base == base) 452 return p; 453 p++; 454 i++; 455 } 456 printf("Invalid I2C base: %p\n", base); 457 return NULL; 458 } 459 460 static int i2c_idle_bus(void *base) 461 { 462 struct i2c_parms *p = i2c_get_parms(base); 463 if (p && p->idle_bus_fn) 464 return p->idle_bus_fn(p->idle_bus_data); 465 return 0; 466 } 467 468 static int mxc_i2c_read(struct i2c_adapter *adap, uint8_t chip, 469 uint addr, int alen, uint8_t *buffer, 470 int len) 471 { 472 return bus_i2c_read(i2c_get_base(adap), chip, addr, alen, buffer, len); 473 } 474 475 static int mxc_i2c_write(struct i2c_adapter *adap, uint8_t chip, 476 uint addr, int alen, uint8_t *buffer, 477 int len) 478 { 479 return bus_i2c_write(i2c_get_base(adap), chip, addr, alen, buffer, len); 480 } 481 482 /* 483 * Test if a chip at a given address responds (probe the chip) 484 */ 485 static int mxc_i2c_probe(struct i2c_adapter *adap, uint8_t chip) 486 { 487 return bus_i2c_write(i2c_get_base(adap), chip, 0, 0, NULL, 0); 488 } 489 490 void bus_i2c_init(void *base, int speed, int unused, 491 int (*idle_bus_fn)(void *p), void *idle_bus_data) 492 { 493 int i = 0; 494 struct i2c_parms *p = srdata.i2c_data; 495 if (!base) 496 return; 497 for (;;) { 498 if (!p->base || (p->base == base)) { 499 p->base = base; 500 if (idle_bus_fn) { 501 p->idle_bus_fn = idle_bus_fn; 502 p->idle_bus_data = idle_bus_data; 503 } 504 break; 505 } 506 p++; 507 i++; 508 if (i >= ARRAY_SIZE(srdata.i2c_data)) 509 return; 510 } 511 bus_i2c_set_bus_speed(base, speed); 512 } 513 514 /* 515 * Init I2C Bus 516 */ 517 static void mxc_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr) 518 { 519 bus_i2c_init(i2c_get_base(adap), speed, slaveaddr, NULL, NULL); 520 } 521 522 /* 523 * Set I2C Speed 524 */ 525 static uint mxc_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed) 526 { 527 return bus_i2c_set_bus_speed(i2c_get_base(adap), speed); 528 } 529 530 /* 531 * Register mxc i2c adapters 532 */ 533 U_BOOT_I2C_ADAP_COMPLETE(mxc0, mxc_i2c_init, mxc_i2c_probe, 534 mxc_i2c_read, mxc_i2c_write, 535 mxc_i2c_set_bus_speed, 536 CONFIG_SYS_MXC_I2C1_SPEED, 537 CONFIG_SYS_MXC_I2C1_SLAVE, 0) 538 U_BOOT_I2C_ADAP_COMPLETE(mxc1, mxc_i2c_init, mxc_i2c_probe, 539 mxc_i2c_read, mxc_i2c_write, 540 mxc_i2c_set_bus_speed, 541 CONFIG_SYS_MXC_I2C2_SPEED, 542 CONFIG_SYS_MXC_I2C2_SLAVE, 1) 543 #if defined(CONFIG_MX31) || defined(CONFIG_MX35) ||\ 544 defined(CONFIG_MX51) || defined(CONFIG_MX53) ||\ 545 defined(CONFIG_MX6) 546 U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe, 547 mxc_i2c_read, mxc_i2c_write, 548 mxc_i2c_set_bus_speed, 549 CONFIG_SYS_MXC_I2C3_SPEED, 550 CONFIG_SYS_MXC_I2C3_SLAVE, 2) 551 #endif 552