1 /* 2 * i2c driver for Freescale mx31 3 * 4 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> 5 * 6 * See file CREDITS for list of people who contributed to this 7 * project. 8 * 9 * This program is free software; you can redistribute it and/or 10 * modify it under the terms of the GNU General Public License as 11 * published by the Free Software Foundation; either version 2 of 12 * the License, or (at your option) any later version. 13 * 14 * This program is distributed in the hope that it will be useful, 15 * but WITHOUT ANY WARRANTY; without even the implied warranty of 16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 17 * GNU General Public License for more details. 18 * 19 * You should have received a copy of the GNU General Public License 20 * along with this program; if not, write to the Free Software 21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 22 * MA 02111-1307 USA 23 */ 24 25 #include <common.h> 26 #include <asm/io.h> 27 28 #if defined(CONFIG_HARD_I2C) 29 30 #if defined(CONFIG_MX31) 31 #include <asm/arch/mx31.h> 32 #include <asm/arch/mx31-regs.h> 33 #else 34 #include <asm/arch/imx-regs.h> 35 #include <asm/arch/clock.h> 36 #endif 37 38 #define IADR 0x00 39 #define IFDR 0x04 40 #define I2CR 0x08 41 #define I2SR 0x0c 42 #define I2DR 0x10 43 44 #define I2CR_IEN (1 << 7) 45 #define I2CR_IIEN (1 << 6) 46 #define I2CR_MSTA (1 << 5) 47 #define I2CR_MTX (1 << 4) 48 #define I2CR_TX_NO_AK (1 << 3) 49 #define I2CR_RSTA (1 << 2) 50 51 #define I2SR_ICF (1 << 7) 52 #define I2SR_IBB (1 << 5) 53 #define I2SR_IIF (1 << 1) 54 #define I2SR_RX_NO_AK (1 << 0) 55 56 #if defined(CONFIG_SYS_I2C_MX31_PORT1) 57 #define I2C_BASE 0x43f80000 58 #define I2C_CLK_OFFSET 26 59 #elif defined (CONFIG_SYS_I2C_MX31_PORT2) 60 #define I2C_BASE 0x43f98000 61 #define I2C_CLK_OFFSET 28 62 #elif defined (CONFIG_SYS_I2C_MX31_PORT3) 63 #define I2C_BASE 0x43f84000 64 #define I2C_CLK_OFFSET 30 65 #elif defined(CONFIG_SYS_I2C_MX53_PORT1) 66 #define I2C_BASE I2C1_BASE_ADDR 67 #elif defined(CONFIG_SYS_I2C_MX53_PORT2) 68 #define I2C_BASE I2C2_BASE_ADDR 69 #elif defined(CONFIG_SYS_I2C_MX35_PORT1) 70 #define I2C_BASE I2C_BASE_ADDR 71 #else 72 #error "define CONFIG_SYS_I2C_MX<Processor>_PORTx to use the mx I2C driver" 73 #endif 74 75 #define I2C_MAX_TIMEOUT 10000 76 #define I2C_MAX_RETRIES 3 77 78 static u16 div[] = { 30, 32, 36, 42, 48, 52, 60, 72, 80, 88, 104, 128, 144, 79 160, 192, 240, 288, 320, 384, 480, 576, 640, 768, 960, 80 1152, 1280, 1536, 1920, 2304, 2560, 3072, 3840}; 81 82 static inline void i2c_reset(void) 83 { 84 writew(0, I2C_BASE + I2CR); /* Reset module */ 85 writew(0, I2C_BASE + I2SR); 86 writew(I2CR_IEN, I2C_BASE + I2CR); 87 } 88 89 void i2c_init(int speed, int unused) 90 { 91 int freq; 92 int i; 93 94 #if defined(CONFIG_MX31) 95 struct clock_control_regs *sc_regs = 96 (struct clock_control_regs *)CCM_BASE; 97 98 freq = mx31_get_ipg_clk(); 99 /* start the required I2C clock */ 100 writel(readl(&sc_regs->cgr0) | (3 << I2C_CLK_OFFSET), 101 &sc_regs->cgr0); 102 #else 103 freq = mxc_get_clock(MXC_IPG_PERCLK); 104 #endif 105 106 for (i = 0; i < 0x1f; i++) 107 if (freq / div[i] <= speed) 108 break; 109 110 debug("%s: speed: %d\n", __func__, speed); 111 112 writew(i, I2C_BASE + IFDR); 113 i2c_reset(); 114 } 115 116 static int wait_idle(void) 117 { 118 int timeout = I2C_MAX_TIMEOUT; 119 120 while ((readw(I2C_BASE + I2SR) & I2SR_IBB) && --timeout) { 121 writew(0, I2C_BASE + I2SR); 122 udelay(1); 123 } 124 return timeout ? timeout : (!(readw(I2C_BASE + I2SR) & I2SR_IBB)); 125 } 126 127 static int wait_busy(void) 128 { 129 int timeout = I2C_MAX_TIMEOUT; 130 131 while (!(readw(I2C_BASE + I2SR) & I2SR_IBB) && --timeout) 132 udelay(1); 133 writew(0, I2C_BASE + I2SR); /* clear interrupt */ 134 135 return timeout; 136 } 137 138 static int wait_complete(void) 139 { 140 int timeout = I2C_MAX_TIMEOUT; 141 142 while ((!(readw(I2C_BASE + I2SR) & I2SR_ICF)) && (--timeout)) { 143 writew(0, I2C_BASE + I2SR); 144 udelay(1); 145 } 146 udelay(200); 147 148 writew(0, I2C_BASE + I2SR); /* clear interrupt */ 149 150 return timeout; 151 } 152 153 154 static int tx_byte(u8 byte) 155 { 156 writew(byte, I2C_BASE + I2DR); 157 158 if (!wait_complete() || readw(I2C_BASE + I2SR) & I2SR_RX_NO_AK) 159 return -1; 160 return 0; 161 } 162 163 static int rx_byte(int last) 164 { 165 if (!wait_complete()) 166 return -1; 167 168 if (last) 169 writew(I2CR_IEN, I2C_BASE + I2CR); 170 171 return readw(I2C_BASE + I2DR); 172 } 173 174 int i2c_probe(uchar chip) 175 { 176 int ret; 177 178 writew(0, I2C_BASE + I2CR); /* Reset module */ 179 writew(I2CR_IEN, I2C_BASE + I2CR); 180 181 writew(I2CR_IEN | I2CR_MSTA | I2CR_MTX, I2C_BASE + I2CR); 182 ret = tx_byte(chip << 1); 183 writew(I2CR_IEN | I2CR_MTX, I2C_BASE + I2CR); 184 185 return ret; 186 } 187 188 static int i2c_addr(uchar chip, uint addr, int alen) 189 { 190 int i, retry = 0; 191 for (retry = 0; retry < 3; retry++) { 192 if (wait_idle()) 193 break; 194 i2c_reset(); 195 for (i = 0; i < I2C_MAX_TIMEOUT; i++) 196 udelay(1); 197 } 198 if (retry >= I2C_MAX_RETRIES) { 199 debug("%s:bus is busy(%x)\n", 200 __func__, readw(I2C_BASE + I2SR)); 201 return -1; 202 } 203 writew(I2CR_IEN | I2CR_MSTA | I2CR_MTX, I2C_BASE + I2CR); 204 205 if (!wait_busy()) { 206 debug("%s:trigger start fail(%x)\n", 207 __func__, readw(I2C_BASE + I2SR)); 208 return -1; 209 } 210 211 if (tx_byte(chip << 1) || (readw(I2C_BASE + I2SR) & I2SR_RX_NO_AK)) { 212 debug("%s:chip address cycle fail(%x)\n", 213 __func__, readw(I2C_BASE + I2SR)); 214 return -1; 215 } 216 while (alen--) 217 if (tx_byte((addr >> (alen * 8)) & 0xff) || 218 (readw(I2C_BASE + I2SR) & I2SR_RX_NO_AK)) { 219 debug("%s:device address cycle fail(%x)\n", 220 __func__, readw(I2C_BASE + I2SR)); 221 return -1; 222 } 223 return 0; 224 } 225 226 int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len) 227 { 228 int timeout = I2C_MAX_TIMEOUT; 229 int ret; 230 231 debug("%s chip: 0x%02x addr: 0x%04x alen: %d len: %d\n", 232 __func__, chip, addr, alen, len); 233 234 if (i2c_addr(chip, addr, alen)) { 235 printf("i2c_addr failed\n"); 236 return -1; 237 } 238 239 writew(I2CR_IEN | I2CR_MSTA | I2CR_MTX | I2CR_RSTA, I2C_BASE + I2CR); 240 241 if (tx_byte(chip << 1 | 1)) 242 return -1; 243 244 writew(I2CR_IEN | I2CR_MSTA | 245 ((len == 1) ? I2CR_TX_NO_AK : 0), 246 I2C_BASE + I2CR); 247 248 ret = readw(I2C_BASE + I2DR); 249 250 while (len--) { 251 ret = rx_byte(len == 0); 252 if (ret < 0) 253 return -1; 254 *buf++ = ret; 255 if (len <= 1) 256 writew(I2CR_IEN | I2CR_MSTA | 257 I2CR_TX_NO_AK, 258 I2C_BASE + I2CR); 259 } 260 261 writew(I2CR_IEN, I2C_BASE + I2CR); 262 263 while (readw(I2C_BASE + I2SR) & I2SR_IBB && --timeout) 264 udelay(1); 265 266 return 0; 267 } 268 269 int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len) 270 { 271 int timeout = I2C_MAX_TIMEOUT; 272 debug("%s chip: 0x%02x addr: 0x%04x alen: %d len: %d\n", 273 __func__, chip, addr, alen, len); 274 275 if (i2c_addr(chip, addr, alen)) 276 return -1; 277 278 while (len--) 279 if (tx_byte(*buf++)) 280 return -1; 281 282 writew(I2CR_IEN, I2C_BASE + I2CR); 283 284 while (readw(I2C_BASE + I2SR) & I2SR_IBB && --timeout) 285 udelay(1); 286 287 return 0; 288 } 289 290 #endif /* CONFIG_HARD_I2C */ 291