1 /* 2 * i2c driver for Freescale i.MX series 3 * 4 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> 5 * (c) 2011 Marek Vasut <marek.vasut@gmail.com> 6 * 7 * Based on i2c-imx.c from linux kernel: 8 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de> 9 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de> 10 * Copyright (C) 2007 RightHand Technologies, Inc. 11 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt> 12 * 13 * 14 * SPDX-License-Identifier: GPL-2.0+ 15 */ 16 17 #include <common.h> 18 #include <asm/arch/clock.h> 19 #include <asm/arch/imx-regs.h> 20 #include <asm/errno.h> 21 #include <asm/io.h> 22 #include <i2c.h> 23 #include <watchdog.h> 24 25 DECLARE_GLOBAL_DATA_PTR; 26 27 #ifdef I2C_QUIRK_REG 28 struct mxc_i2c_regs { 29 uint8_t iadr; 30 uint8_t ifdr; 31 uint8_t i2cr; 32 uint8_t i2sr; 33 uint8_t i2dr; 34 }; 35 #else 36 struct mxc_i2c_regs { 37 uint32_t iadr; 38 uint32_t ifdr; 39 uint32_t i2cr; 40 uint32_t i2sr; 41 uint32_t i2dr; 42 }; 43 #endif 44 45 #define I2CR_IIEN (1 << 6) 46 #define I2CR_MSTA (1 << 5) 47 #define I2CR_MTX (1 << 4) 48 #define I2CR_TX_NO_AK (1 << 3) 49 #define I2CR_RSTA (1 << 2) 50 51 #define I2SR_ICF (1 << 7) 52 #define I2SR_IBB (1 << 5) 53 #define I2SR_IAL (1 << 4) 54 #define I2SR_IIF (1 << 1) 55 #define I2SR_RX_NO_AK (1 << 0) 56 57 #ifdef I2C_QUIRK_REG 58 #define I2CR_IEN (0 << 7) 59 #define I2CR_IDIS (1 << 7) 60 #define I2SR_IIF_CLEAR (1 << 1) 61 #else 62 #define I2CR_IEN (1 << 7) 63 #define I2CR_IDIS (0 << 7) 64 #define I2SR_IIF_CLEAR (0 << 1) 65 #endif 66 67 #if defined(CONFIG_HARD_I2C) && !defined(CONFIG_SYS_I2C_BASE) 68 #error "define CONFIG_SYS_I2C_BASE to use the mxc_i2c driver" 69 #endif 70 71 #ifdef I2C_QUIRK_REG 72 static u16 i2c_clk_div[60][2] = { 73 { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 }, 74 { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 }, 75 { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D }, 76 { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 }, 77 { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 }, 78 { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 }, 79 { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 }, 80 { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 }, 81 { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 }, 82 { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B }, 83 { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 }, 84 { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 }, 85 { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B }, 86 { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A }, 87 { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E }, 88 }; 89 #else 90 static u16 i2c_clk_div[50][2] = { 91 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 }, 92 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 }, 93 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 }, 94 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B }, 95 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A }, 96 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 }, 97 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 }, 98 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 }, 99 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 }, 100 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B }, 101 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E }, 102 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D }, 103 { 3072, 0x1E }, { 3840, 0x1F } 104 }; 105 #endif 106 107 108 #ifndef CONFIG_SYS_MXC_I2C1_SPEED 109 #define CONFIG_SYS_MXC_I2C1_SPEED 100000 110 #endif 111 #ifndef CONFIG_SYS_MXC_I2C2_SPEED 112 #define CONFIG_SYS_MXC_I2C2_SPEED 100000 113 #endif 114 #ifndef CONFIG_SYS_MXC_I2C3_SPEED 115 #define CONFIG_SYS_MXC_I2C3_SPEED 100000 116 #endif 117 118 #ifndef CONFIG_SYS_MXC_I2C1_SLAVE 119 #define CONFIG_SYS_MXC_I2C1_SLAVE 0 120 #endif 121 #ifndef CONFIG_SYS_MXC_I2C2_SLAVE 122 #define CONFIG_SYS_MXC_I2C2_SLAVE 0 123 #endif 124 #ifndef CONFIG_SYS_MXC_I2C3_SLAVE 125 #define CONFIG_SYS_MXC_I2C3_SLAVE 0 126 #endif 127 128 129 /* 130 * Calculate and set proper clock divider 131 */ 132 static uint8_t i2c_imx_get_clk(unsigned int rate) 133 { 134 unsigned int i2c_clk_rate; 135 unsigned int div; 136 u8 clk_div; 137 138 #if defined(CONFIG_MX31) 139 struct clock_control_regs *sc_regs = 140 (struct clock_control_regs *)CCM_BASE; 141 142 /* start the required I2C clock */ 143 writel(readl(&sc_regs->cgr0) | (3 << CONFIG_SYS_I2C_CLK_OFFSET), 144 &sc_regs->cgr0); 145 #endif 146 147 /* Divider value calculation */ 148 i2c_clk_rate = mxc_get_clock(MXC_I2C_CLK); 149 div = (i2c_clk_rate + rate - 1) / rate; 150 if (div < i2c_clk_div[0][0]) 151 clk_div = 0; 152 else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0]) 153 clk_div = ARRAY_SIZE(i2c_clk_div) - 1; 154 else 155 for (clk_div = 0; i2c_clk_div[clk_div][0] < div; clk_div++) 156 ; 157 158 /* Store divider value */ 159 return clk_div; 160 } 161 162 /* 163 * Set I2C Bus speed 164 */ 165 static int bus_i2c_set_bus_speed(void *base, int speed) 166 { 167 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)base; 168 u8 clk_idx = i2c_imx_get_clk(speed); 169 u8 idx = i2c_clk_div[clk_idx][1]; 170 171 /* Store divider value */ 172 writeb(idx, &i2c_regs->ifdr); 173 174 /* Reset module */ 175 writeb(I2CR_IDIS, &i2c_regs->i2cr); 176 writeb(0, &i2c_regs->i2sr); 177 return 0; 178 } 179 180 #define ST_BUS_IDLE (0 | (I2SR_IBB << 8)) 181 #define ST_BUS_BUSY (I2SR_IBB | (I2SR_IBB << 8)) 182 #define ST_IIF (I2SR_IIF | (I2SR_IIF << 8)) 183 184 static int wait_for_sr_state(struct mxc_i2c_regs *i2c_regs, unsigned state) 185 { 186 unsigned sr; 187 ulong elapsed; 188 ulong start_time = get_timer(0); 189 for (;;) { 190 sr = readb(&i2c_regs->i2sr); 191 if (sr & I2SR_IAL) { 192 #ifdef I2C_QUIRK_REG 193 writeb(sr | I2SR_IAL, &i2c_regs->i2sr); 194 #else 195 writeb(sr & ~I2SR_IAL, &i2c_regs->i2sr); 196 #endif 197 printf("%s: Arbitration lost sr=%x cr=%x state=%x\n", 198 __func__, sr, readb(&i2c_regs->i2cr), state); 199 return -ERESTART; 200 } 201 if ((sr & (state >> 8)) == (unsigned char)state) 202 return sr; 203 WATCHDOG_RESET(); 204 elapsed = get_timer(start_time); 205 if (elapsed > (CONFIG_SYS_HZ / 10)) /* .1 seconds */ 206 break; 207 } 208 printf("%s: failed sr=%x cr=%x state=%x\n", __func__, 209 sr, readb(&i2c_regs->i2cr), state); 210 return -ETIMEDOUT; 211 } 212 213 static int tx_byte(struct mxc_i2c_regs *i2c_regs, u8 byte) 214 { 215 int ret; 216 217 writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr); 218 writeb(byte, &i2c_regs->i2dr); 219 ret = wait_for_sr_state(i2c_regs, ST_IIF); 220 if (ret < 0) 221 return ret; 222 if (ret & I2SR_RX_NO_AK) 223 return -ENODEV; 224 return 0; 225 } 226 227 /* 228 * Stop I2C transaction 229 */ 230 static void i2c_imx_stop(struct mxc_i2c_regs *i2c_regs) 231 { 232 int ret; 233 unsigned int temp = readb(&i2c_regs->i2cr); 234 235 temp &= ~(I2CR_MSTA | I2CR_MTX); 236 writeb(temp, &i2c_regs->i2cr); 237 ret = wait_for_sr_state(i2c_regs, ST_BUS_IDLE); 238 if (ret < 0) 239 printf("%s:trigger stop failed\n", __func__); 240 } 241 242 /* 243 * Send start signal, chip address and 244 * write register address 245 */ 246 static int i2c_init_transfer_(struct mxc_i2c_regs *i2c_regs, 247 uchar chip, uint addr, int alen) 248 { 249 unsigned int temp; 250 int ret; 251 252 /* Enable I2C controller */ 253 #ifdef I2C_QUIRK_REG 254 if (readb(&i2c_regs->i2cr) & I2CR_IDIS) { 255 #else 256 if (!(readb(&i2c_regs->i2cr) & I2CR_IEN)) { 257 #endif 258 writeb(I2CR_IEN, &i2c_regs->i2cr); 259 /* Wait for controller to be stable */ 260 udelay(50); 261 } 262 if (readb(&i2c_regs->iadr) == (chip << 1)) 263 writeb((chip << 1) ^ 2, &i2c_regs->iadr); 264 writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr); 265 ret = wait_for_sr_state(i2c_regs, ST_BUS_IDLE); 266 if (ret < 0) 267 return ret; 268 269 /* Start I2C transaction */ 270 temp = readb(&i2c_regs->i2cr); 271 temp |= I2CR_MSTA; 272 writeb(temp, &i2c_regs->i2cr); 273 274 ret = wait_for_sr_state(i2c_regs, ST_BUS_BUSY); 275 if (ret < 0) 276 return ret; 277 278 temp |= I2CR_MTX | I2CR_TX_NO_AK; 279 writeb(temp, &i2c_regs->i2cr); 280 281 /* write slave address */ 282 ret = tx_byte(i2c_regs, chip << 1); 283 if (ret < 0) 284 return ret; 285 286 while (alen--) { 287 ret = tx_byte(i2c_regs, (addr >> (alen * 8)) & 0xff); 288 if (ret < 0) 289 return ret; 290 } 291 return 0; 292 } 293 294 static int i2c_idle_bus(void *base); 295 296 static int i2c_init_transfer(struct mxc_i2c_regs *i2c_regs, 297 uchar chip, uint addr, int alen) 298 { 299 int retry; 300 int ret; 301 for (retry = 0; retry < 3; retry++) { 302 ret = i2c_init_transfer_(i2c_regs, chip, addr, alen); 303 if (ret >= 0) 304 return 0; 305 i2c_imx_stop(i2c_regs); 306 if (ret == -ENODEV) 307 return ret; 308 309 printf("%s: failed for chip 0x%x retry=%d\n", __func__, chip, 310 retry); 311 if (ret != -ERESTART) 312 /* Disable controller */ 313 writeb(I2CR_IDIS, &i2c_regs->i2cr); 314 udelay(100); 315 if (i2c_idle_bus(i2c_regs) < 0) 316 break; 317 } 318 printf("%s: give up i2c_regs=%p\n", __func__, i2c_regs); 319 return ret; 320 } 321 322 /* 323 * Read data from I2C device 324 */ 325 int bus_i2c_read(void *base, uchar chip, uint addr, int alen, uchar *buf, 326 int len) 327 { 328 int ret; 329 unsigned int temp; 330 int i; 331 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)base; 332 333 ret = i2c_init_transfer(i2c_regs, chip, addr, alen); 334 if (ret < 0) 335 return ret; 336 337 temp = readb(&i2c_regs->i2cr); 338 temp |= I2CR_RSTA; 339 writeb(temp, &i2c_regs->i2cr); 340 341 ret = tx_byte(i2c_regs, (chip << 1) | 1); 342 if (ret < 0) { 343 i2c_imx_stop(i2c_regs); 344 return ret; 345 } 346 347 /* setup bus to read data */ 348 temp = readb(&i2c_regs->i2cr); 349 temp &= ~(I2CR_MTX | I2CR_TX_NO_AK); 350 if (len == 1) 351 temp |= I2CR_TX_NO_AK; 352 writeb(temp, &i2c_regs->i2cr); 353 writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr); 354 readb(&i2c_regs->i2dr); /* dummy read to clear ICF */ 355 356 /* read data */ 357 for (i = 0; i < len; i++) { 358 ret = wait_for_sr_state(i2c_regs, ST_IIF); 359 if (ret < 0) { 360 i2c_imx_stop(i2c_regs); 361 return ret; 362 } 363 364 /* 365 * It must generate STOP before read I2DR to prevent 366 * controller from generating another clock cycle 367 */ 368 if (i == (len - 1)) { 369 i2c_imx_stop(i2c_regs); 370 } else if (i == (len - 2)) { 371 temp = readb(&i2c_regs->i2cr); 372 temp |= I2CR_TX_NO_AK; 373 writeb(temp, &i2c_regs->i2cr); 374 } 375 writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr); 376 buf[i] = readb(&i2c_regs->i2dr); 377 } 378 i2c_imx_stop(i2c_regs); 379 return 0; 380 } 381 382 /* 383 * Write data to I2C device 384 */ 385 int bus_i2c_write(void *base, uchar chip, uint addr, int alen, 386 const uchar *buf, int len) 387 { 388 int ret; 389 int i; 390 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)base; 391 392 ret = i2c_init_transfer(i2c_regs, chip, addr, alen); 393 if (ret < 0) 394 return ret; 395 396 for (i = 0; i < len; i++) { 397 ret = tx_byte(i2c_regs, buf[i]); 398 if (ret < 0) 399 break; 400 } 401 i2c_imx_stop(i2c_regs); 402 return ret; 403 } 404 405 struct i2c_parms { 406 void *base; 407 void *idle_bus_data; 408 int (*idle_bus_fn)(void *p); 409 }; 410 411 struct sram_data { 412 unsigned curr_i2c_bus; 413 struct i2c_parms i2c_data[3]; 414 }; 415 416 static void * const i2c_bases[] = { 417 #if defined(CONFIG_MX25) 418 (void *)IMX_I2C_BASE, 419 (void *)IMX_I2C2_BASE, 420 (void *)IMX_I2C3_BASE 421 #elif defined(CONFIG_MX27) 422 (void *)IMX_I2C1_BASE, 423 (void *)IMX_I2C2_BASE 424 #elif defined(CONFIG_MX31) || defined(CONFIG_MX35) || \ 425 defined(CONFIG_MX51) || defined(CONFIG_MX53) || \ 426 defined(CONFIG_MX6) || defined(CONFIG_LS102XA) 427 (void *)I2C1_BASE_ADDR, 428 (void *)I2C2_BASE_ADDR, 429 (void *)I2C3_BASE_ADDR 430 #elif defined(CONFIG_VF610) 431 (void *)I2C0_BASE_ADDR 432 #elif defined(CONFIG_FSL_LSCH3) 433 (void *)I2C1_BASE_ADDR, 434 (void *)I2C2_BASE_ADDR, 435 (void *)I2C3_BASE_ADDR, 436 (void *)I2C4_BASE_ADDR 437 #else 438 #error "architecture not supported" 439 #endif 440 }; 441 442 void *i2c_get_base(struct i2c_adapter *adap) 443 { 444 return i2c_bases[adap->hwadapnr]; 445 } 446 447 static struct i2c_parms *i2c_get_parms(void *base) 448 { 449 struct sram_data *srdata = (void *)gd->srdata; 450 int i = 0; 451 struct i2c_parms *p = srdata->i2c_data; 452 while (i < ARRAY_SIZE(srdata->i2c_data)) { 453 if (p->base == base) 454 return p; 455 p++; 456 i++; 457 } 458 printf("Invalid I2C base: %p\n", base); 459 return NULL; 460 } 461 462 static int i2c_idle_bus(void *base) 463 { 464 struct i2c_parms *p = i2c_get_parms(base); 465 if (p && p->idle_bus_fn) 466 return p->idle_bus_fn(p->idle_bus_data); 467 return 0; 468 } 469 470 static int mxc_i2c_read(struct i2c_adapter *adap, uint8_t chip, 471 uint addr, int alen, uint8_t *buffer, 472 int len) 473 { 474 return bus_i2c_read(i2c_get_base(adap), chip, addr, alen, buffer, len); 475 } 476 477 static int mxc_i2c_write(struct i2c_adapter *adap, uint8_t chip, 478 uint addr, int alen, uint8_t *buffer, 479 int len) 480 { 481 return bus_i2c_write(i2c_get_base(adap), chip, addr, alen, buffer, len); 482 } 483 484 /* 485 * Test if a chip at a given address responds (probe the chip) 486 */ 487 static int mxc_i2c_probe(struct i2c_adapter *adap, uint8_t chip) 488 { 489 return bus_i2c_write(i2c_get_base(adap), chip, 0, 0, NULL, 0); 490 } 491 492 void bus_i2c_init(void *base, int speed, int unused, 493 int (*idle_bus_fn)(void *p), void *idle_bus_data) 494 { 495 struct sram_data *srdata = (void *)gd->srdata; 496 int i = 0; 497 struct i2c_parms *p = srdata->i2c_data; 498 if (!base) 499 return; 500 for (;;) { 501 if (!p->base || (p->base == base)) { 502 p->base = base; 503 if (idle_bus_fn) { 504 p->idle_bus_fn = idle_bus_fn; 505 p->idle_bus_data = idle_bus_data; 506 } 507 break; 508 } 509 p++; 510 i++; 511 if (i >= ARRAY_SIZE(srdata->i2c_data)) 512 return; 513 } 514 bus_i2c_set_bus_speed(base, speed); 515 } 516 517 /* 518 * Init I2C Bus 519 */ 520 static void mxc_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr) 521 { 522 bus_i2c_init(i2c_get_base(adap), speed, slaveaddr, NULL, NULL); 523 } 524 525 /* 526 * Set I2C Speed 527 */ 528 static uint mxc_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed) 529 { 530 return bus_i2c_set_bus_speed(i2c_get_base(adap), speed); 531 } 532 533 /* 534 * Register mxc i2c adapters 535 */ 536 U_BOOT_I2C_ADAP_COMPLETE(mxc0, mxc_i2c_init, mxc_i2c_probe, 537 mxc_i2c_read, mxc_i2c_write, 538 mxc_i2c_set_bus_speed, 539 CONFIG_SYS_MXC_I2C1_SPEED, 540 CONFIG_SYS_MXC_I2C1_SLAVE, 0) 541 U_BOOT_I2C_ADAP_COMPLETE(mxc1, mxc_i2c_init, mxc_i2c_probe, 542 mxc_i2c_read, mxc_i2c_write, 543 mxc_i2c_set_bus_speed, 544 CONFIG_SYS_MXC_I2C2_SPEED, 545 CONFIG_SYS_MXC_I2C2_SLAVE, 1) 546 #if defined(CONFIG_MX31) || defined(CONFIG_MX35) ||\ 547 defined(CONFIG_MX51) || defined(CONFIG_MX53) ||\ 548 defined(CONFIG_MX6) || defined(CONFIG_LS102XA) 549 U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe, 550 mxc_i2c_read, mxc_i2c_write, 551 mxc_i2c_set_bus_speed, 552 CONFIG_SYS_MXC_I2C3_SPEED, 553 CONFIG_SYS_MXC_I2C3_SLAVE, 2) 554 #endif 555