1 /* 2 * i2c driver for Freescale i.MX series 3 * 4 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> 5 * (c) 2011 Marek Vasut <marek.vasut@gmail.com> 6 * 7 * Based on i2c-imx.c from linux kernel: 8 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de> 9 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de> 10 * Copyright (C) 2007 RightHand Technologies, Inc. 11 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt> 12 * 13 * 14 * See file CREDITS for list of people who contributed to this 15 * project. 16 * 17 * This program is free software; you can redistribute it and/or 18 * modify it under the terms of the GNU General Public License as 19 * published by the Free Software Foundation; either version 2 of 20 * the License, or (at your option) any later version. 21 * 22 * This program is distributed in the hope that it will be useful, 23 * but WITHOUT ANY WARRANTY; without even the implied warranty of 24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 25 * GNU General Public License for more details. 26 * 27 * You should have received a copy of the GNU General Public License 28 * along with this program; if not, write to the Free Software 29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 30 * MA 02111-1307 USA 31 */ 32 33 #include <common.h> 34 #include <asm/io.h> 35 36 #if defined(CONFIG_HARD_I2C) 37 38 #include <asm/arch/clock.h> 39 #include <asm/arch/imx-regs.h> 40 41 struct mxc_i2c_regs { 42 uint32_t iadr; 43 uint32_t ifdr; 44 uint32_t i2cr; 45 uint32_t i2sr; 46 uint32_t i2dr; 47 }; 48 49 #define I2CR_IEN (1 << 7) 50 #define I2CR_IIEN (1 << 6) 51 #define I2CR_MSTA (1 << 5) 52 #define I2CR_MTX (1 << 4) 53 #define I2CR_TX_NO_AK (1 << 3) 54 #define I2CR_RSTA (1 << 2) 55 56 #define I2SR_ICF (1 << 7) 57 #define I2SR_IBB (1 << 5) 58 #define I2SR_IIF (1 << 1) 59 #define I2SR_RX_NO_AK (1 << 0) 60 61 #if defined(CONFIG_SYS_I2C_MX31_PORT1) 62 #define I2C_BASE 0x43f80000 63 #define I2C_CLK_OFFSET 26 64 #elif defined (CONFIG_SYS_I2C_MX31_PORT2) 65 #define I2C_BASE 0x43f98000 66 #define I2C_CLK_OFFSET 28 67 #elif defined (CONFIG_SYS_I2C_MX31_PORT3) 68 #define I2C_BASE 0x43f84000 69 #define I2C_CLK_OFFSET 30 70 #elif defined(CONFIG_SYS_I2C_MX53_PORT1) 71 #define I2C_BASE I2C1_BASE_ADDR 72 #elif defined(CONFIG_SYS_I2C_MX53_PORT2) 73 #define I2C_BASE I2C2_BASE_ADDR 74 #elif defined(CONFIG_SYS_I2C_MX35_PORT1) 75 #define I2C_BASE I2C_BASE_ADDR 76 #else 77 #error "define CONFIG_SYS_I2C_MX<Processor>_PORTx to use the mx I2C driver" 78 #endif 79 80 #define I2C_MAX_TIMEOUT 10000 81 82 static u16 i2c_clk_div[50][2] = { 83 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 }, 84 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 }, 85 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 }, 86 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B }, 87 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A }, 88 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 }, 89 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 }, 90 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 }, 91 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 }, 92 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B }, 93 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E }, 94 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D }, 95 { 3072, 0x1E }, { 3840, 0x1F } 96 }; 97 98 static u8 clk_div; 99 100 /* 101 * Calculate and set proper clock divider 102 */ 103 static void i2c_imx_set_clk(unsigned int rate) 104 { 105 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 106 unsigned int i2c_clk_rate; 107 unsigned int div; 108 109 #if defined(CONFIG_MX31) 110 struct clock_control_regs *sc_regs = 111 (struct clock_control_regs *)CCM_BASE; 112 113 /* start the required I2C clock */ 114 writel(readl(&sc_regs->cgr0) | (3 << I2C_CLK_OFFSET), 115 &sc_regs->cgr0); 116 #endif 117 118 /* Divider value calculation */ 119 i2c_clk_rate = mxc_get_clock(MXC_IPG_PERCLK); 120 div = (i2c_clk_rate + rate - 1) / rate; 121 if (div < i2c_clk_div[0][0]) 122 clk_div = 0; 123 else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0]) 124 clk_div = ARRAY_SIZE(i2c_clk_div) - 1; 125 else 126 for (clk_div = 0; i2c_clk_div[clk_div][0] < div; clk_div++) 127 ; 128 129 /* Store divider value */ 130 writeb(i2c_clk_div[clk_div][1], &i2c_regs->ifdr); 131 } 132 133 /* 134 * Reset I2C Controller 135 */ 136 void i2c_reset(void) 137 { 138 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 139 140 writeb(0, &i2c_regs->i2cr); /* Reset module */ 141 writeb(0, &i2c_regs->i2sr); 142 } 143 144 /* 145 * Init I2C Bus 146 */ 147 void i2c_init(int speed, int unused) 148 { 149 i2c_imx_set_clk(speed); 150 i2c_reset(); 151 } 152 153 /* 154 * Set I2C Speed 155 */ 156 int i2c_set_bus_speed(unsigned int speed) 157 { 158 i2c_init(speed, 0); 159 return 0; 160 } 161 162 /* 163 * Get I2C Speed 164 */ 165 unsigned int i2c_get_bus_speed(void) 166 { 167 return mxc_get_clock(MXC_IPG_PERCLK) / i2c_clk_div[clk_div][0]; 168 } 169 170 /* 171 * Wait for bus to be busy (or free if for_busy = 0) 172 * 173 * for_busy = 1: Wait for IBB to be asserted 174 * for_busy = 0: Wait for IBB to be de-asserted 175 */ 176 int i2c_imx_bus_busy(int for_busy) 177 { 178 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 179 unsigned int temp; 180 181 int timeout = I2C_MAX_TIMEOUT; 182 183 while (timeout--) { 184 temp = readb(&i2c_regs->i2sr); 185 186 if (for_busy && (temp & I2SR_IBB)) 187 return 0; 188 if (!for_busy && !(temp & I2SR_IBB)) 189 return 0; 190 191 udelay(1); 192 } 193 194 return 1; 195 } 196 197 /* 198 * Wait for transaction to complete 199 */ 200 int i2c_imx_trx_complete(void) 201 { 202 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 203 int timeout = I2C_MAX_TIMEOUT; 204 205 while (timeout--) { 206 if (readb(&i2c_regs->i2sr) & I2SR_IIF) { 207 writeb(0, &i2c_regs->i2sr); 208 return 0; 209 } 210 211 udelay(1); 212 } 213 214 return 1; 215 } 216 217 /* 218 * Check if the transaction was ACKed 219 */ 220 int i2c_imx_acked(void) 221 { 222 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 223 224 return readb(&i2c_regs->i2sr) & I2SR_RX_NO_AK; 225 } 226 227 /* 228 * Start the controller 229 */ 230 int i2c_imx_start(void) 231 { 232 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 233 unsigned int temp = 0; 234 int result; 235 236 writeb(i2c_clk_div[clk_div][1], &i2c_regs->ifdr); 237 238 /* Enable I2C controller */ 239 writeb(0, &i2c_regs->i2sr); 240 writeb(I2CR_IEN, &i2c_regs->i2cr); 241 242 /* Wait controller to be stable */ 243 udelay(50); 244 245 /* Start I2C transaction */ 246 temp = readb(&i2c_regs->i2cr); 247 temp |= I2CR_MSTA; 248 writeb(temp, &i2c_regs->i2cr); 249 250 result = i2c_imx_bus_busy(1); 251 if (result) 252 return result; 253 254 temp |= I2CR_MTX | I2CR_TX_NO_AK; 255 writeb(temp, &i2c_regs->i2cr); 256 257 return 0; 258 } 259 260 /* 261 * Stop the controller 262 */ 263 void i2c_imx_stop(void) 264 { 265 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 266 unsigned int temp = 0; 267 268 /* Stop I2C transaction */ 269 temp = readb(&i2c_regs->i2cr); 270 temp |= ~(I2CR_MSTA | I2CR_MTX); 271 writeb(temp, &i2c_regs->i2cr); 272 273 i2c_imx_bus_busy(0); 274 275 /* Disable I2C controller */ 276 writeb(0, &i2c_regs->i2cr); 277 } 278 279 /* 280 * Set chip address and access mode 281 * 282 * read = 1: READ access 283 * read = 0: WRITE access 284 */ 285 int i2c_imx_set_chip_addr(uchar chip, int read) 286 { 287 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 288 int ret; 289 290 writeb((chip << 1) | read, &i2c_regs->i2dr); 291 292 ret = i2c_imx_trx_complete(); 293 if (ret) 294 return ret; 295 296 ret = i2c_imx_acked(); 297 if (ret) 298 return ret; 299 300 return ret; 301 } 302 303 /* 304 * Write register address 305 */ 306 int i2c_imx_set_reg_addr(uint addr, int alen) 307 { 308 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 309 int ret; 310 int i; 311 312 for (i = 0; i < (8 * alen); i += 8) { 313 writeb((addr >> i) & 0xff, &i2c_regs->i2dr); 314 315 ret = i2c_imx_trx_complete(); 316 if (ret) 317 break; 318 319 ret = i2c_imx_acked(); 320 if (ret) 321 break; 322 } 323 324 return ret; 325 } 326 327 /* 328 * Try if a chip add given address responds (probe the chip) 329 */ 330 int i2c_probe(uchar chip) 331 { 332 int ret; 333 334 ret = i2c_imx_start(); 335 if (ret) 336 return ret; 337 338 ret = i2c_imx_set_chip_addr(chip, 0); 339 if (ret) 340 return ret; 341 342 i2c_imx_stop(); 343 344 return ret; 345 } 346 347 /* 348 * Read data from I2C device 349 */ 350 int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len) 351 { 352 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 353 int ret; 354 unsigned int temp; 355 int i; 356 357 ret = i2c_imx_start(); 358 if (ret) 359 return ret; 360 361 /* write slave address */ 362 ret = i2c_imx_set_chip_addr(chip, 0); 363 if (ret) 364 return ret; 365 366 ret = i2c_imx_set_reg_addr(addr, alen); 367 if (ret) 368 return ret; 369 370 temp = readb(&i2c_regs->i2cr); 371 temp |= I2CR_RSTA; 372 writeb(temp, &i2c_regs->i2cr); 373 374 ret = i2c_imx_set_chip_addr(chip, 1); 375 if (ret) 376 return ret; 377 378 /* setup bus to read data */ 379 temp = readb(&i2c_regs->i2cr); 380 temp &= ~(I2CR_MTX | I2CR_TX_NO_AK); 381 if (len == 1) 382 temp |= I2CR_TX_NO_AK; 383 writeb(temp, &i2c_regs->i2cr); 384 readb(&i2c_regs->i2dr); 385 386 /* read data */ 387 for (i = 0; i < len; i++) { 388 ret = i2c_imx_trx_complete(); 389 if (ret) 390 return ret; 391 392 /* 393 * It must generate STOP before read I2DR to prevent 394 * controller from generating another clock cycle 395 */ 396 if (i == (len - 1)) { 397 temp = readb(&i2c_regs->i2cr); 398 temp &= ~(I2CR_MSTA | I2CR_MTX); 399 writeb(temp, &i2c_regs->i2cr); 400 i2c_imx_bus_busy(0); 401 } else if (i == (len - 2)) { 402 temp = readb(&i2c_regs->i2cr); 403 temp |= I2CR_TX_NO_AK; 404 writeb(temp, &i2c_regs->i2cr); 405 } 406 407 buf[i] = readb(&i2c_regs->i2dr); 408 } 409 410 i2c_imx_stop(); 411 412 return ret; 413 } 414 415 /* 416 * Write data to I2C device 417 */ 418 int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len) 419 { 420 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 421 int ret; 422 int i; 423 424 ret = i2c_imx_start(); 425 if (ret) 426 return ret; 427 428 /* write slave address */ 429 ret = i2c_imx_set_chip_addr(chip, 0); 430 if (ret) 431 return ret; 432 433 ret = i2c_imx_set_reg_addr(addr, alen); 434 if (ret) 435 return ret; 436 437 for (i = 0; i < len; i++) { 438 writeb(buf[i], &i2c_regs->i2dr); 439 440 ret = i2c_imx_trx_complete(); 441 if (ret) 442 return ret; 443 444 ret = i2c_imx_acked(); 445 if (ret) 446 return ret; 447 } 448 449 i2c_imx_stop(); 450 451 return ret; 452 } 453 #endif /* CONFIG_HARD_I2C */ 454