1 /* 2 * i2c driver for Freescale i.MX series 3 * 4 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> 5 * (c) 2011 Marek Vasut <marek.vasut@gmail.com> 6 * 7 * Based on i2c-imx.c from linux kernel: 8 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de> 9 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de> 10 * Copyright (C) 2007 RightHand Technologies, Inc. 11 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt> 12 * 13 * 14 * See file CREDITS for list of people who contributed to this 15 * project. 16 * 17 * This program is free software; you can redistribute it and/or 18 * modify it under the terms of the GNU General Public License as 19 * published by the Free Software Foundation; either version 2 of 20 * the License, or (at your option) any later version. 21 * 22 * This program is distributed in the hope that it will be useful, 23 * but WITHOUT ANY WARRANTY; without even the implied warranty of 24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 25 * GNU General Public License for more details. 26 * 27 * You should have received a copy of the GNU General Public License 28 * along with this program; if not, write to the Free Software 29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 30 * MA 02111-1307 USA 31 */ 32 33 #include <common.h> 34 #include <asm/io.h> 35 36 #if defined(CONFIG_HARD_I2C) 37 38 #include <asm/arch/clock.h> 39 #include <asm/arch/imx-regs.h> 40 41 struct mxc_i2c_regs { 42 uint32_t iadr; 43 uint32_t ifdr; 44 uint32_t i2cr; 45 uint32_t i2sr; 46 uint32_t i2dr; 47 }; 48 49 #define I2CR_IEN (1 << 7) 50 #define I2CR_IIEN (1 << 6) 51 #define I2CR_MSTA (1 << 5) 52 #define I2CR_MTX (1 << 4) 53 #define I2CR_TX_NO_AK (1 << 3) 54 #define I2CR_RSTA (1 << 2) 55 56 #define I2SR_ICF (1 << 7) 57 #define I2SR_IBB (1 << 5) 58 #define I2SR_IIF (1 << 1) 59 #define I2SR_RX_NO_AK (1 << 0) 60 61 #if defined(CONFIG_SYS_I2C_MX31_PORT1) 62 #define I2C_BASE 0x43f80000 63 #define I2C_CLK_OFFSET 26 64 #elif defined (CONFIG_SYS_I2C_MX31_PORT2) 65 #define I2C_BASE 0x43f98000 66 #define I2C_CLK_OFFSET 28 67 #elif defined (CONFIG_SYS_I2C_MX31_PORT3) 68 #define I2C_BASE 0x43f84000 69 #define I2C_CLK_OFFSET 30 70 #elif defined(CONFIG_SYS_I2C_MX53_PORT1) 71 #define I2C_BASE I2C1_BASE_ADDR 72 #elif defined(CONFIG_SYS_I2C_MX53_PORT2) 73 #define I2C_BASE I2C2_BASE_ADDR 74 #elif defined(CONFIG_SYS_I2C_MX35_PORT1) 75 #define I2C_BASE I2C_BASE_ADDR 76 #else 77 #error "define CONFIG_SYS_I2C_MX<Processor>_PORTx to use the mx I2C driver" 78 #endif 79 80 #define I2C_MAX_TIMEOUT 10000 81 82 static u16 i2c_clk_div[50][2] = { 83 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 }, 84 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 }, 85 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 }, 86 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B }, 87 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A }, 88 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 }, 89 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 }, 90 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 }, 91 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 }, 92 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B }, 93 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E }, 94 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D }, 95 { 3072, 0x1E }, { 3840, 0x1F } 96 }; 97 98 static u8 clk_idx; 99 100 /* 101 * Calculate and set proper clock divider 102 */ 103 static void i2c_imx_set_clk(unsigned int rate) 104 { 105 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 106 unsigned int i2c_clk_rate; 107 unsigned int div; 108 int i; 109 110 #if defined(CONFIG_MX31) 111 struct clock_control_regs *sc_regs = 112 (struct clock_control_regs *)CCM_BASE; 113 114 /* start the required I2C clock */ 115 writel(readl(&sc_regs->cgr0) | (3 << I2C_CLK_OFFSET), 116 &sc_regs->cgr0); 117 #endif 118 119 /* Divider value calculation */ 120 i2c_clk_rate = mxc_get_clock(MXC_IPG_PERCLK); 121 div = (i2c_clk_rate + rate - 1) / rate; 122 if (div < i2c_clk_div[0][0]) 123 i = 0; 124 else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0]) 125 i = ARRAY_SIZE(i2c_clk_div) - 1; 126 else 127 for (i = 0; i2c_clk_div[i][0] < div; i++) 128 ; 129 130 /* Store divider value */ 131 clk_idx = i2c_clk_div[i][1]; 132 writeb(clk_idx, &i2c_regs->ifdr); 133 } 134 135 /* 136 * Reset I2C Controller 137 */ 138 void i2c_reset(void) 139 { 140 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 141 142 writeb(0, &i2c_regs->i2cr); /* Reset module */ 143 writeb(0, &i2c_regs->i2sr); 144 } 145 146 /* 147 * Init I2C Bus 148 */ 149 void i2c_init(int speed, int unused) 150 { 151 i2c_imx_set_clk(speed); 152 i2c_reset(); 153 } 154 155 /* 156 * Wait for bus to be busy (or free if for_busy = 0) 157 * 158 * for_busy = 1: Wait for IBB to be asserted 159 * for_busy = 0: Wait for IBB to be de-asserted 160 */ 161 int i2c_imx_bus_busy(int for_busy) 162 { 163 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 164 unsigned int temp; 165 166 int timeout = I2C_MAX_TIMEOUT; 167 168 while (timeout--) { 169 temp = readb(&i2c_regs->i2sr); 170 171 if (for_busy && (temp & I2SR_IBB)) 172 return 0; 173 if (!for_busy && !(temp & I2SR_IBB)) 174 return 0; 175 176 udelay(1); 177 } 178 179 return 1; 180 } 181 182 /* 183 * Wait for transaction to complete 184 */ 185 int i2c_imx_trx_complete(void) 186 { 187 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 188 int timeout = I2C_MAX_TIMEOUT; 189 190 while (timeout--) { 191 if (readb(&i2c_regs->i2sr) & I2SR_IIF) { 192 writeb(0, &i2c_regs->i2sr); 193 return 0; 194 } 195 196 udelay(1); 197 } 198 199 return 1; 200 } 201 202 /* 203 * Check if the transaction was ACKed 204 */ 205 int i2c_imx_acked(void) 206 { 207 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 208 209 return readb(&i2c_regs->i2sr) & I2SR_RX_NO_AK; 210 } 211 212 /* 213 * Start the controller 214 */ 215 int i2c_imx_start(void) 216 { 217 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 218 unsigned int temp = 0; 219 int result; 220 221 writeb(clk_idx, &i2c_regs->ifdr); 222 223 /* Enable I2C controller */ 224 writeb(0, &i2c_regs->i2sr); 225 writeb(I2CR_IEN, &i2c_regs->i2cr); 226 227 /* Wait controller to be stable */ 228 udelay(50); 229 230 /* Start I2C transaction */ 231 temp = readb(&i2c_regs->i2cr); 232 temp |= I2CR_MSTA; 233 writeb(temp, &i2c_regs->i2cr); 234 235 result = i2c_imx_bus_busy(1); 236 if (result) 237 return result; 238 239 temp |= I2CR_MTX | I2CR_TX_NO_AK; 240 writeb(temp, &i2c_regs->i2cr); 241 242 return 0; 243 } 244 245 /* 246 * Stop the controller 247 */ 248 void i2c_imx_stop(void) 249 { 250 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 251 unsigned int temp = 0; 252 253 /* Stop I2C transaction */ 254 temp = readb(&i2c_regs->i2cr); 255 temp |= ~(I2CR_MSTA | I2CR_MTX); 256 writeb(temp, &i2c_regs->i2cr); 257 258 i2c_imx_bus_busy(0); 259 260 /* Disable I2C controller */ 261 writeb(0, &i2c_regs->i2cr); 262 } 263 264 /* 265 * Set chip address and access mode 266 * 267 * read = 1: READ access 268 * read = 0: WRITE access 269 */ 270 int i2c_imx_set_chip_addr(uchar chip, int read) 271 { 272 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 273 int ret; 274 275 writeb((chip << 1) | read, &i2c_regs->i2dr); 276 277 ret = i2c_imx_trx_complete(); 278 if (ret) 279 return ret; 280 281 ret = i2c_imx_acked(); 282 if (ret) 283 return ret; 284 285 return ret; 286 } 287 288 /* 289 * Write register address 290 */ 291 int i2c_imx_set_reg_addr(uint addr, int alen) 292 { 293 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 294 int ret; 295 int i; 296 297 for (i = 0; i < (8 * alen); i += 8) { 298 writeb((addr >> i) & 0xff, &i2c_regs->i2dr); 299 300 ret = i2c_imx_trx_complete(); 301 if (ret) 302 break; 303 304 ret = i2c_imx_acked(); 305 if (ret) 306 break; 307 } 308 309 return ret; 310 } 311 312 /* 313 * Try if a chip add given address responds (probe the chip) 314 */ 315 int i2c_probe(uchar chip) 316 { 317 int ret; 318 319 ret = i2c_imx_start(); 320 if (ret) 321 return ret; 322 323 ret = i2c_imx_set_chip_addr(chip, 0); 324 if (ret) 325 return ret; 326 327 i2c_imx_stop(); 328 329 return ret; 330 } 331 332 /* 333 * Read data from I2C device 334 */ 335 int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len) 336 { 337 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 338 int ret; 339 unsigned int temp; 340 int i; 341 342 ret = i2c_imx_start(); 343 if (ret) 344 return ret; 345 346 /* write slave address */ 347 ret = i2c_imx_set_chip_addr(chip, 0); 348 if (ret) 349 return ret; 350 351 ret = i2c_imx_set_reg_addr(addr, alen); 352 if (ret) 353 return ret; 354 355 temp = readb(&i2c_regs->i2cr); 356 temp |= I2CR_RSTA; 357 writeb(temp, &i2c_regs->i2cr); 358 359 ret = i2c_imx_set_chip_addr(chip, 1); 360 if (ret) 361 return ret; 362 363 /* setup bus to read data */ 364 temp = readb(&i2c_regs->i2cr); 365 temp &= ~(I2CR_MTX | I2CR_TX_NO_AK); 366 if (len == 1) 367 temp |= I2CR_TX_NO_AK; 368 writeb(temp, &i2c_regs->i2cr); 369 readb(&i2c_regs->i2dr); 370 371 /* read data */ 372 for (i = 0; i < len; i++) { 373 ret = i2c_imx_trx_complete(); 374 if (ret) 375 return ret; 376 377 /* 378 * It must generate STOP before read I2DR to prevent 379 * controller from generating another clock cycle 380 */ 381 if (i == (len - 1)) { 382 temp = readb(&i2c_regs->i2cr); 383 temp &= ~(I2CR_MSTA | I2CR_MTX); 384 writeb(temp, &i2c_regs->i2cr); 385 i2c_imx_bus_busy(0); 386 } else if (i == (len - 2)) { 387 temp = readb(&i2c_regs->i2cr); 388 temp |= I2CR_TX_NO_AK; 389 writeb(temp, &i2c_regs->i2cr); 390 } 391 392 buf[i] = readb(&i2c_regs->i2dr); 393 } 394 395 i2c_imx_stop(); 396 397 return ret; 398 } 399 400 /* 401 * Write data to I2C device 402 */ 403 int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len) 404 { 405 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 406 int ret; 407 int i; 408 409 ret = i2c_imx_start(); 410 if (ret) 411 return ret; 412 413 /* write slave address */ 414 ret = i2c_imx_set_chip_addr(chip, 0); 415 if (ret) 416 return ret; 417 418 ret = i2c_imx_set_reg_addr(addr, alen); 419 if (ret) 420 return ret; 421 422 for (i = 0; i < len; i++) { 423 writeb(buf[i], &i2c_regs->i2dr); 424 425 ret = i2c_imx_trx_complete(); 426 if (ret) 427 return ret; 428 429 ret = i2c_imx_acked(); 430 if (ret) 431 return ret; 432 } 433 434 i2c_imx_stop(); 435 436 return ret; 437 } 438 #endif /* CONFIG_HARD_I2C */ 439