1 /* 2 * i2c driver for Freescale i.MX series 3 * 4 * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> 5 * (c) 2011 Marek Vasut <marek.vasut@gmail.com> 6 * 7 * Based on i2c-imx.c from linux kernel: 8 * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de> 9 * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de> 10 * Copyright (C) 2007 RightHand Technologies, Inc. 11 * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt> 12 * 13 * 14 * See file CREDITS for list of people who contributed to this 15 * project. 16 * 17 * This program is free software; you can redistribute it and/or 18 * modify it under the terms of the GNU General Public License as 19 * published by the Free Software Foundation; either version 2 of 20 * the License, or (at your option) any later version. 21 * 22 * This program is distributed in the hope that it will be useful, 23 * but WITHOUT ANY WARRANTY; without even the implied warranty of 24 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 25 * GNU General Public License for more details. 26 * 27 * You should have received a copy of the GNU General Public License 28 * along with this program; if not, write to the Free Software 29 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 30 * MA 02111-1307 USA 31 */ 32 33 #include <common.h> 34 #include <asm/io.h> 35 36 #if defined(CONFIG_HARD_I2C) 37 38 #include <asm/arch/clock.h> 39 #include <asm/arch/imx-regs.h> 40 #include <i2c.h> 41 42 struct mxc_i2c_regs { 43 uint32_t iadr; 44 uint32_t ifdr; 45 uint32_t i2cr; 46 uint32_t i2sr; 47 uint32_t i2dr; 48 }; 49 50 #define I2CR_IEN (1 << 7) 51 #define I2CR_IIEN (1 << 6) 52 #define I2CR_MSTA (1 << 5) 53 #define I2CR_MTX (1 << 4) 54 #define I2CR_TX_NO_AK (1 << 3) 55 #define I2CR_RSTA (1 << 2) 56 57 #define I2SR_ICF (1 << 7) 58 #define I2SR_IBB (1 << 5) 59 #define I2SR_IIF (1 << 1) 60 #define I2SR_RX_NO_AK (1 << 0) 61 62 #ifdef CONFIG_SYS_I2C_BASE 63 #define I2C_BASE CONFIG_SYS_I2C_BASE 64 #else 65 #error "define CONFIG_SYS_I2C_BASE to use the mxc_i2c driver" 66 #endif 67 68 #define I2C_MAX_TIMEOUT 10000 69 70 static u16 i2c_clk_div[50][2] = { 71 { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 }, 72 { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 }, 73 { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 }, 74 { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B }, 75 { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A }, 76 { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 }, 77 { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 }, 78 { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 }, 79 { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 }, 80 { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B }, 81 { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E }, 82 { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D }, 83 { 3072, 0x1E }, { 3840, 0x1F } 84 }; 85 86 /* 87 * Calculate and set proper clock divider 88 */ 89 static uint8_t i2c_imx_get_clk(unsigned int rate) 90 { 91 unsigned int i2c_clk_rate; 92 unsigned int div; 93 u8 clk_div; 94 95 #if defined(CONFIG_MX31) 96 struct clock_control_regs *sc_regs = 97 (struct clock_control_regs *)CCM_BASE; 98 99 /* start the required I2C clock */ 100 writel(readl(&sc_regs->cgr0) | (3 << CONFIG_SYS_I2C_CLK_OFFSET), 101 &sc_regs->cgr0); 102 #endif 103 104 /* Divider value calculation */ 105 i2c_clk_rate = mxc_get_clock(MXC_IPG_PERCLK); 106 div = (i2c_clk_rate + rate - 1) / rate; 107 if (div < i2c_clk_div[0][0]) 108 clk_div = 0; 109 else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0]) 110 clk_div = ARRAY_SIZE(i2c_clk_div) - 1; 111 else 112 for (clk_div = 0; i2c_clk_div[clk_div][0] < div; clk_div++) 113 ; 114 115 /* Store divider value */ 116 return clk_div; 117 } 118 119 /* 120 * Reset I2C Controller 121 */ 122 void i2c_reset(void) 123 { 124 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 125 126 writeb(0, &i2c_regs->i2cr); /* Reset module */ 127 writeb(0, &i2c_regs->i2sr); 128 } 129 130 /* 131 * Init I2C Bus 132 */ 133 void i2c_init(int speed, int unused) 134 { 135 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 136 u8 clk_idx = i2c_imx_get_clk(speed); 137 u8 idx = i2c_clk_div[clk_idx][1]; 138 139 /* Store divider value */ 140 writeb(idx, &i2c_regs->ifdr); 141 142 i2c_reset(); 143 } 144 145 /* 146 * Set I2C Speed 147 */ 148 int i2c_set_bus_speed(unsigned int speed) 149 { 150 i2c_init(speed, 0); 151 return 0; 152 } 153 154 /* 155 * Get I2C Speed 156 */ 157 unsigned int i2c_get_bus_speed(void) 158 { 159 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 160 u8 clk_idx = readb(&i2c_regs->ifdr); 161 u8 clk_div; 162 163 for (clk_div = 0; i2c_clk_div[clk_div][1] != clk_idx; clk_div++) 164 ; 165 166 return mxc_get_clock(MXC_IPG_PERCLK) / i2c_clk_div[clk_div][0]; 167 } 168 169 /* 170 * Wait for bus to be busy (or free if for_busy = 0) 171 * 172 * for_busy = 1: Wait for IBB to be asserted 173 * for_busy = 0: Wait for IBB to be de-asserted 174 */ 175 int i2c_imx_bus_busy(int for_busy) 176 { 177 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 178 unsigned int temp; 179 180 int timeout = I2C_MAX_TIMEOUT; 181 182 while (timeout--) { 183 temp = readb(&i2c_regs->i2sr); 184 185 if (for_busy && (temp & I2SR_IBB)) 186 return 0; 187 if (!for_busy && !(temp & I2SR_IBB)) 188 return 0; 189 190 udelay(1); 191 } 192 193 return 1; 194 } 195 196 /* 197 * Wait for transaction to complete 198 */ 199 int i2c_imx_trx_complete(void) 200 { 201 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 202 int timeout = I2C_MAX_TIMEOUT; 203 204 while (timeout--) { 205 if (readb(&i2c_regs->i2sr) & I2SR_IIF) { 206 writeb(0, &i2c_regs->i2sr); 207 return 0; 208 } 209 210 udelay(1); 211 } 212 213 return 1; 214 } 215 216 /* 217 * Check if the transaction was ACKed 218 */ 219 int i2c_imx_acked(void) 220 { 221 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 222 223 return readb(&i2c_regs->i2sr) & I2SR_RX_NO_AK; 224 } 225 226 /* 227 * Start the controller 228 */ 229 int i2c_imx_start(void) 230 { 231 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 232 unsigned int temp = 0; 233 int result; 234 235 /* Enable I2C controller */ 236 writeb(0, &i2c_regs->i2sr); 237 writeb(I2CR_IEN, &i2c_regs->i2cr); 238 239 /* Wait controller to be stable */ 240 udelay(50); 241 242 /* Start I2C transaction */ 243 temp = readb(&i2c_regs->i2cr); 244 temp |= I2CR_MSTA; 245 writeb(temp, &i2c_regs->i2cr); 246 247 result = i2c_imx_bus_busy(1); 248 if (result) 249 return result; 250 251 temp |= I2CR_MTX | I2CR_TX_NO_AK; 252 writeb(temp, &i2c_regs->i2cr); 253 254 return 0; 255 } 256 257 /* 258 * Stop the controller 259 */ 260 void i2c_imx_stop(void) 261 { 262 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 263 unsigned int temp = 0; 264 265 /* Stop I2C transaction */ 266 temp = readb(&i2c_regs->i2cr); 267 temp |= ~(I2CR_MSTA | I2CR_MTX); 268 writeb(temp, &i2c_regs->i2cr); 269 270 i2c_imx_bus_busy(0); 271 272 /* Disable I2C controller */ 273 writeb(0, &i2c_regs->i2cr); 274 } 275 276 /* 277 * Set chip address and access mode 278 * 279 * read = 1: READ access 280 * read = 0: WRITE access 281 */ 282 int i2c_imx_set_chip_addr(uchar chip, int read) 283 { 284 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 285 int ret; 286 287 writeb((chip << 1) | read, &i2c_regs->i2dr); 288 289 ret = i2c_imx_trx_complete(); 290 if (ret) 291 return ret; 292 293 ret = i2c_imx_acked(); 294 if (ret) 295 return ret; 296 297 return ret; 298 } 299 300 /* 301 * Write register address 302 */ 303 int i2c_imx_set_reg_addr(uint addr, int alen) 304 { 305 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 306 int ret = 0; 307 308 while (alen--) { 309 writeb((addr >> (alen * 8)) & 0xff, &i2c_regs->i2dr); 310 311 ret = i2c_imx_trx_complete(); 312 if (ret) 313 break; 314 315 ret = i2c_imx_acked(); 316 if (ret) 317 break; 318 } 319 320 return ret; 321 } 322 323 /* 324 * Try if a chip add given address responds (probe the chip) 325 */ 326 int i2c_probe(uchar chip) 327 { 328 int ret; 329 330 ret = i2c_imx_start(); 331 if (ret) 332 return ret; 333 334 ret = i2c_imx_set_chip_addr(chip, 0); 335 if (ret) 336 return ret; 337 338 i2c_imx_stop(); 339 340 return ret; 341 } 342 343 /* 344 * Read data from I2C device 345 */ 346 int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len) 347 { 348 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 349 int ret; 350 unsigned int temp; 351 int i; 352 353 ret = i2c_imx_start(); 354 if (ret) 355 return ret; 356 357 /* write slave address */ 358 ret = i2c_imx_set_chip_addr(chip, 0); 359 if (ret) 360 return ret; 361 362 ret = i2c_imx_set_reg_addr(addr, alen); 363 if (ret) 364 return ret; 365 366 temp = readb(&i2c_regs->i2cr); 367 temp |= I2CR_RSTA; 368 writeb(temp, &i2c_regs->i2cr); 369 370 ret = i2c_imx_set_chip_addr(chip, 1); 371 if (ret) 372 return ret; 373 374 /* setup bus to read data */ 375 temp = readb(&i2c_regs->i2cr); 376 temp &= ~(I2CR_MTX | I2CR_TX_NO_AK); 377 if (len == 1) 378 temp |= I2CR_TX_NO_AK; 379 writeb(temp, &i2c_regs->i2cr); 380 readb(&i2c_regs->i2dr); 381 382 /* read data */ 383 for (i = 0; i < len; i++) { 384 ret = i2c_imx_trx_complete(); 385 if (ret) 386 return ret; 387 388 /* 389 * It must generate STOP before read I2DR to prevent 390 * controller from generating another clock cycle 391 */ 392 if (i == (len - 1)) { 393 temp = readb(&i2c_regs->i2cr); 394 temp &= ~(I2CR_MSTA | I2CR_MTX); 395 writeb(temp, &i2c_regs->i2cr); 396 i2c_imx_bus_busy(0); 397 } else if (i == (len - 2)) { 398 temp = readb(&i2c_regs->i2cr); 399 temp |= I2CR_TX_NO_AK; 400 writeb(temp, &i2c_regs->i2cr); 401 } 402 403 buf[i] = readb(&i2c_regs->i2dr); 404 } 405 406 i2c_imx_stop(); 407 408 return ret; 409 } 410 411 /* 412 * Write data to I2C device 413 */ 414 int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len) 415 { 416 struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 417 int ret; 418 int i; 419 420 ret = i2c_imx_start(); 421 if (ret) 422 return ret; 423 424 /* write slave address */ 425 ret = i2c_imx_set_chip_addr(chip, 0); 426 if (ret) 427 return ret; 428 429 ret = i2c_imx_set_reg_addr(addr, alen); 430 if (ret) 431 return ret; 432 433 for (i = 0; i < len; i++) { 434 writeb(buf[i], &i2c_regs->i2dr); 435 436 ret = i2c_imx_trx_complete(); 437 if (ret) 438 return ret; 439 440 ret = i2c_imx_acked(); 441 if (ret) 442 return ret; 443 } 444 445 i2c_imx_stop(); 446 447 return ret; 448 } 449 #endif /* CONFIG_HARD_I2C */ 450