1cdace066SSascha Hauer /* 2db84140bSMarek Vasut * i2c driver for Freescale i.MX series 3cdace066SSascha Hauer * 4cdace066SSascha Hauer * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> 5db84140bSMarek Vasut * (c) 2011 Marek Vasut <marek.vasut@gmail.com> 6db84140bSMarek Vasut * 7db84140bSMarek Vasut * Based on i2c-imx.c from linux kernel: 8db84140bSMarek Vasut * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de> 9db84140bSMarek Vasut * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de> 10db84140bSMarek Vasut * Copyright (C) 2007 RightHand Technologies, Inc. 11db84140bSMarek Vasut * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt> 12db84140bSMarek Vasut * 13cdace066SSascha Hauer * 141a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 15cdace066SSascha Hauer */ 16cdace066SSascha Hauer 17cdace066SSascha Hauer #include <common.h> 18127cec18SLiu Hui-R64343 #include <asm/arch/clock.h> 1986271115SStefano Babic #include <asm/arch/imx-regs.h> 20cea60b0cSTroy Kisky #include <asm/errno.h> 2124cd738bSTroy Kisky #include <asm/io.h> 22bf0783dfSMarek Vasut #include <i2c.h> 237aa57a01STroy Kisky #include <watchdog.h> 24cdace066SSascha Hauer 2530ea41a4SAlison Wang #ifdef I2C_QUIRK_REG 2630ea41a4SAlison Wang struct mxc_i2c_regs { 2730ea41a4SAlison Wang uint8_t iadr; 2830ea41a4SAlison Wang uint8_t ifdr; 2930ea41a4SAlison Wang uint8_t i2cr; 3030ea41a4SAlison Wang uint8_t i2sr; 3130ea41a4SAlison Wang uint8_t i2dr; 3230ea41a4SAlison Wang }; 3330ea41a4SAlison Wang #else 34db84140bSMarek Vasut struct mxc_i2c_regs { 35db84140bSMarek Vasut uint32_t iadr; 36db84140bSMarek Vasut uint32_t ifdr; 37db84140bSMarek Vasut uint32_t i2cr; 38db84140bSMarek Vasut uint32_t i2sr; 39db84140bSMarek Vasut uint32_t i2dr; 40db84140bSMarek Vasut }; 4130ea41a4SAlison Wang #endif 42cdace066SSascha Hauer 43cdace066SSascha Hauer #define I2CR_IIEN (1 << 6) 44cdace066SSascha Hauer #define I2CR_MSTA (1 << 5) 45cdace066SSascha Hauer #define I2CR_MTX (1 << 4) 46cdace066SSascha Hauer #define I2CR_TX_NO_AK (1 << 3) 47cdace066SSascha Hauer #define I2CR_RSTA (1 << 2) 48cdace066SSascha Hauer 49cdace066SSascha Hauer #define I2SR_ICF (1 << 7) 50cdace066SSascha Hauer #define I2SR_IBB (1 << 5) 51d5383a63STroy Kisky #define I2SR_IAL (1 << 4) 52cdace066SSascha Hauer #define I2SR_IIF (1 << 1) 53cdace066SSascha Hauer #define I2SR_RX_NO_AK (1 << 0) 54cdace066SSascha Hauer 5530ea41a4SAlison Wang #ifdef I2C_QUIRK_REG 5630ea41a4SAlison Wang #define I2CR_IEN (0 << 7) 5730ea41a4SAlison Wang #define I2CR_IDIS (1 << 7) 5830ea41a4SAlison Wang #define I2SR_IIF_CLEAR (1 << 1) 5930ea41a4SAlison Wang #else 6030ea41a4SAlison Wang #define I2CR_IEN (1 << 7) 6130ea41a4SAlison Wang #define I2CR_IDIS (0 << 7) 6230ea41a4SAlison Wang #define I2SR_IIF_CLEAR (0 << 1) 6330ea41a4SAlison Wang #endif 6430ea41a4SAlison Wang 65e4ff525fSTroy Kisky #if defined(CONFIG_HARD_I2C) && !defined(CONFIG_SYS_I2C_BASE) 66de6f604dSTroy Kisky #error "define CONFIG_SYS_I2C_BASE to use the mxc_i2c driver" 67cdace066SSascha Hauer #endif 68cdace066SSascha Hauer 6930ea41a4SAlison Wang #ifdef I2C_QUIRK_REG 7030ea41a4SAlison Wang static u16 i2c_clk_div[60][2] = { 7130ea41a4SAlison Wang { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 }, 7230ea41a4SAlison Wang { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 }, 7330ea41a4SAlison Wang { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D }, 7430ea41a4SAlison Wang { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 }, 7530ea41a4SAlison Wang { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 }, 7630ea41a4SAlison Wang { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 }, 7730ea41a4SAlison Wang { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 }, 7830ea41a4SAlison Wang { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 }, 7930ea41a4SAlison Wang { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 }, 8030ea41a4SAlison Wang { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B }, 8130ea41a4SAlison Wang { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 }, 8230ea41a4SAlison Wang { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 }, 8330ea41a4SAlison Wang { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B }, 8430ea41a4SAlison Wang { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A }, 8530ea41a4SAlison Wang { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E }, 8630ea41a4SAlison Wang }; 8730ea41a4SAlison Wang #else 88db84140bSMarek Vasut static u16 i2c_clk_div[50][2] = { 89db84140bSMarek Vasut { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 }, 90db84140bSMarek Vasut { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 }, 91db84140bSMarek Vasut { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 }, 92db84140bSMarek Vasut { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B }, 93db84140bSMarek Vasut { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A }, 94db84140bSMarek Vasut { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 }, 95db84140bSMarek Vasut { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 }, 96db84140bSMarek Vasut { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 }, 97db84140bSMarek Vasut { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 }, 98db84140bSMarek Vasut { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B }, 99db84140bSMarek Vasut { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E }, 100db84140bSMarek Vasut { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D }, 101db84140bSMarek Vasut { 3072, 0x1E }, { 3840, 0x1F } 102db84140bSMarek Vasut }; 10330ea41a4SAlison Wang #endif 104cdace066SSascha Hauer 105*fac96408Strem 106*fac96408Strem #ifndef CONFIG_SYS_MXC_I2C1_SPEED 107*fac96408Strem #define CONFIG_SYS_MXC_I2C1_SPEED 100000 108*fac96408Strem #endif 109*fac96408Strem #ifndef CONFIG_SYS_MXC_I2C2_SPEED 110*fac96408Strem #define CONFIG_SYS_MXC_I2C2_SPEED 100000 111*fac96408Strem #endif 112*fac96408Strem #ifndef CONFIG_SYS_MXC_I2C3_SPEED 113*fac96408Strem #define CONFIG_SYS_MXC_I2C3_SPEED 100000 114*fac96408Strem #endif 115*fac96408Strem 116*fac96408Strem #ifndef CONFIG_SYS_MXC_I2C1_SLAVE 117*fac96408Strem #define CONFIG_SYS_MXC_I2C1_SLAVE 0 118*fac96408Strem #endif 119*fac96408Strem #ifndef CONFIG_SYS_MXC_I2C2_SLAVE 120*fac96408Strem #define CONFIG_SYS_MXC_I2C2_SLAVE 0 121*fac96408Strem #endif 122*fac96408Strem #ifndef CONFIG_SYS_MXC_I2C3_SLAVE 123*fac96408Strem #define CONFIG_SYS_MXC_I2C3_SLAVE 0 124*fac96408Strem #endif 125*fac96408Strem 126*fac96408Strem 127db84140bSMarek Vasut /* 128db84140bSMarek Vasut * Calculate and set proper clock divider 129db84140bSMarek Vasut */ 130bf0783dfSMarek Vasut static uint8_t i2c_imx_get_clk(unsigned int rate) 1311d549adeSStefano Babic { 132db84140bSMarek Vasut unsigned int i2c_clk_rate; 133db84140bSMarek Vasut unsigned int div; 134bf0783dfSMarek Vasut u8 clk_div; 135cdace066SSascha Hauer 136127cec18SLiu Hui-R64343 #if defined(CONFIG_MX31) 1371d549adeSStefano Babic struct clock_control_regs *sc_regs = 1381d549adeSStefano Babic (struct clock_control_regs *)CCM_BASE; 139db84140bSMarek Vasut 140e7de18afSGuennadi Liakhovetski /* start the required I2C clock */ 141de6f604dSTroy Kisky writel(readl(&sc_regs->cgr0) | (3 << CONFIG_SYS_I2C_CLK_OFFSET), 1421d549adeSStefano Babic &sc_regs->cgr0); 143127cec18SLiu Hui-R64343 #endif 144e7de18afSGuennadi Liakhovetski 145db84140bSMarek Vasut /* Divider value calculation */ 146e7bed5c2SMatthias Weisser i2c_clk_rate = mxc_get_clock(MXC_I2C_CLK); 147db84140bSMarek Vasut div = (i2c_clk_rate + rate - 1) / rate; 148db84140bSMarek Vasut if (div < i2c_clk_div[0][0]) 149b567b8ffSMarek Vasut clk_div = 0; 150db84140bSMarek Vasut else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0]) 151b567b8ffSMarek Vasut clk_div = ARRAY_SIZE(i2c_clk_div) - 1; 152db84140bSMarek Vasut else 153b567b8ffSMarek Vasut for (clk_div = 0; i2c_clk_div[clk_div][0] < div; clk_div++) 154db84140bSMarek Vasut ; 155cdace066SSascha Hauer 156db84140bSMarek Vasut /* Store divider value */ 157bf0783dfSMarek Vasut return clk_div; 158db84140bSMarek Vasut } 159cdace066SSascha Hauer 160db84140bSMarek Vasut /* 161e4ff525fSTroy Kisky * Set I2C Bus speed 162db84140bSMarek Vasut */ 1637f86bd57SMarek Vasut static int bus_i2c_set_bus_speed(void *base, int speed) 164db84140bSMarek Vasut { 165e4ff525fSTroy Kisky struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)base; 166bf0783dfSMarek Vasut u8 clk_idx = i2c_imx_get_clk(speed); 167bf0783dfSMarek Vasut u8 idx = i2c_clk_div[clk_idx][1]; 168bf0783dfSMarek Vasut 169bf0783dfSMarek Vasut /* Store divider value */ 170bf0783dfSMarek Vasut writeb(idx, &i2c_regs->ifdr); 171bf0783dfSMarek Vasut 17283a1a190STroy Kisky /* Reset module */ 17330ea41a4SAlison Wang writeb(I2CR_IDIS, &i2c_regs->i2cr); 17483a1a190STroy Kisky writeb(0, &i2c_regs->i2sr); 175b567b8ffSMarek Vasut return 0; 176b567b8ffSMarek Vasut } 177b567b8ffSMarek Vasut 1787aa57a01STroy Kisky #define ST_BUS_IDLE (0 | (I2SR_IBB << 8)) 1797aa57a01STroy Kisky #define ST_BUS_BUSY (I2SR_IBB | (I2SR_IBB << 8)) 1807aa57a01STroy Kisky #define ST_IIF (I2SR_IIF | (I2SR_IIF << 8)) 1817aa57a01STroy Kisky 1827aa57a01STroy Kisky static int wait_for_sr_state(struct mxc_i2c_regs *i2c_regs, unsigned state) 18381687212SStefano Babic { 1847aa57a01STroy Kisky unsigned sr; 1857aa57a01STroy Kisky ulong elapsed; 1867aa57a01STroy Kisky ulong start_time = get_timer(0); 1877aa57a01STroy Kisky for (;;) { 1887aa57a01STroy Kisky sr = readb(&i2c_regs->i2sr); 189d5383a63STroy Kisky if (sr & I2SR_IAL) { 19030ea41a4SAlison Wang #ifdef I2C_QUIRK_REG 19130ea41a4SAlison Wang writeb(sr | I2SR_IAL, &i2c_regs->i2sr); 19230ea41a4SAlison Wang #else 193d5383a63STroy Kisky writeb(sr & ~I2SR_IAL, &i2c_regs->i2sr); 19430ea41a4SAlison Wang #endif 195d5383a63STroy Kisky printf("%s: Arbitration lost sr=%x cr=%x state=%x\n", 196d5383a63STroy Kisky __func__, sr, readb(&i2c_regs->i2cr), state); 197d5383a63STroy Kisky return -ERESTART; 198d5383a63STroy Kisky } 1997aa57a01STroy Kisky if ((sr & (state >> 8)) == (unsigned char)state) 2007aa57a01STroy Kisky return sr; 2017aa57a01STroy Kisky WATCHDOG_RESET(); 2027aa57a01STroy Kisky elapsed = get_timer(start_time); 2037aa57a01STroy Kisky if (elapsed > (CONFIG_SYS_HZ / 10)) /* .1 seconds */ 2047aa57a01STroy Kisky break; 20581687212SStefano Babic } 2067aa57a01STroy Kisky printf("%s: failed sr=%x cr=%x state=%x\n", __func__, 2077aa57a01STroy Kisky sr, readb(&i2c_regs->i2cr), state); 208cea60b0cSTroy Kisky return -ETIMEDOUT; 209db84140bSMarek Vasut } 210db84140bSMarek Vasut 211cea60b0cSTroy Kisky static int tx_byte(struct mxc_i2c_regs *i2c_regs, u8 byte) 212cdace066SSascha Hauer { 213cea60b0cSTroy Kisky int ret; 214db84140bSMarek Vasut 21530ea41a4SAlison Wang writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr); 216cea60b0cSTroy Kisky writeb(byte, &i2c_regs->i2dr); 2177aa57a01STroy Kisky ret = wait_for_sr_state(i2c_regs, ST_IIF); 218cea60b0cSTroy Kisky if (ret < 0) 219cea60b0cSTroy Kisky return ret; 220cea60b0cSTroy Kisky if (ret & I2SR_RX_NO_AK) 221cea60b0cSTroy Kisky return -ENODEV; 222cea60b0cSTroy Kisky return 0; 223db84140bSMarek Vasut } 224db84140bSMarek Vasut 225db84140bSMarek Vasut /* 22690a5b70fSTroy Kisky * Stop I2C transaction 227db84140bSMarek Vasut */ 22827a5da02STroy Kisky static void i2c_imx_stop(struct mxc_i2c_regs *i2c_regs) 229db84140bSMarek Vasut { 2307aa57a01STroy Kisky int ret; 23190a5b70fSTroy Kisky unsigned int temp = readb(&i2c_regs->i2cr); 232db84140bSMarek Vasut 2331c076dbaSTroy Kisky temp &= ~(I2CR_MSTA | I2CR_MTX); 234db84140bSMarek Vasut writeb(temp, &i2c_regs->i2cr); 2357aa57a01STroy Kisky ret = wait_for_sr_state(i2c_regs, ST_BUS_IDLE); 2367aa57a01STroy Kisky if (ret < 0) 2377aa57a01STroy Kisky printf("%s:trigger stop failed\n", __func__); 238db84140bSMarek Vasut } 239db84140bSMarek Vasut 240db84140bSMarek Vasut /* 241b230ddc2STroy Kisky * Send start signal, chip address and 242b230ddc2STroy Kisky * write register address 243db84140bSMarek Vasut */ 244a7f1a005STroy Kisky static int i2c_init_transfer_(struct mxc_i2c_regs *i2c_regs, 245b230ddc2STroy Kisky uchar chip, uint addr, int alen) 246cdace066SSascha Hauer { 24771e9f3cbSTroy Kisky unsigned int temp; 24871e9f3cbSTroy Kisky int ret; 24971e9f3cbSTroy Kisky 25071e9f3cbSTroy Kisky /* Enable I2C controller */ 25130ea41a4SAlison Wang #ifdef I2C_QUIRK_REG 25230ea41a4SAlison Wang if (readb(&i2c_regs->i2cr) & I2CR_IDIS) { 25330ea41a4SAlison Wang #else 25490a5b70fSTroy Kisky if (!(readb(&i2c_regs->i2cr) & I2CR_IEN)) { 25530ea41a4SAlison Wang #endif 25671e9f3cbSTroy Kisky writeb(I2CR_IEN, &i2c_regs->i2cr); 25771e9f3cbSTroy Kisky /* Wait for controller to be stable */ 25871e9f3cbSTroy Kisky udelay(50); 25990a5b70fSTroy Kisky } 260ca741da1STroy Kisky if (readb(&i2c_regs->iadr) == (chip << 1)) 261ca741da1STroy Kisky writeb((chip << 1) ^ 2, &i2c_regs->iadr); 26230ea41a4SAlison Wang writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr); 26390a5b70fSTroy Kisky ret = wait_for_sr_state(i2c_regs, ST_BUS_IDLE); 26490a5b70fSTroy Kisky if (ret < 0) 265a7f1a005STroy Kisky return ret; 26671e9f3cbSTroy Kisky 26771e9f3cbSTroy Kisky /* Start I2C transaction */ 26871e9f3cbSTroy Kisky temp = readb(&i2c_regs->i2cr); 26971e9f3cbSTroy Kisky temp |= I2CR_MSTA; 27071e9f3cbSTroy Kisky writeb(temp, &i2c_regs->i2cr); 27171e9f3cbSTroy Kisky 27271e9f3cbSTroy Kisky ret = wait_for_sr_state(i2c_regs, ST_BUS_BUSY); 27371e9f3cbSTroy Kisky if (ret < 0) 274a7f1a005STroy Kisky return ret; 275b230ddc2STroy Kisky 27671e9f3cbSTroy Kisky temp |= I2CR_MTX | I2CR_TX_NO_AK; 27771e9f3cbSTroy Kisky writeb(temp, &i2c_regs->i2cr); 27871e9f3cbSTroy Kisky 279b230ddc2STroy Kisky /* write slave address */ 280b230ddc2STroy Kisky ret = tx_byte(i2c_regs, chip << 1); 281b230ddc2STroy Kisky if (ret < 0) 282a7f1a005STroy Kisky return ret; 283db84140bSMarek Vasut 284bf0783dfSMarek Vasut while (alen--) { 285cea60b0cSTroy Kisky ret = tx_byte(i2c_regs, (addr >> (alen * 8)) & 0xff); 286cea60b0cSTroy Kisky if (ret < 0) 287a7f1a005STroy Kisky return ret; 28881687212SStefano Babic } 289b230ddc2STroy Kisky return 0; 290a7f1a005STroy Kisky } 291a7f1a005STroy Kisky 29296c19bd3STroy Kisky static int i2c_idle_bus(void *base); 29396c19bd3STroy Kisky 294a7f1a005STroy Kisky static int i2c_init_transfer(struct mxc_i2c_regs *i2c_regs, 295a7f1a005STroy Kisky uchar chip, uint addr, int alen) 296a7f1a005STroy Kisky { 297a7f1a005STroy Kisky int retry; 298a7f1a005STroy Kisky int ret; 299a7f1a005STroy Kisky for (retry = 0; retry < 3; retry++) { 300a7f1a005STroy Kisky ret = i2c_init_transfer_(i2c_regs, chip, addr, alen); 301a7f1a005STroy Kisky if (ret >= 0) 302a7f1a005STroy Kisky return 0; 30327a5da02STroy Kisky i2c_imx_stop(i2c_regs); 304a7f1a005STroy Kisky if (ret == -ENODEV) 305a7f1a005STroy Kisky return ret; 306a7f1a005STroy Kisky 307a7f1a005STroy Kisky printf("%s: failed for chip 0x%x retry=%d\n", __func__, chip, 308a7f1a005STroy Kisky retry); 309a7f1a005STroy Kisky if (ret != -ERESTART) 31030ea41a4SAlison Wang /* Disable controller */ 31130ea41a4SAlison Wang writeb(I2CR_IDIS, &i2c_regs->i2cr); 312a7f1a005STroy Kisky udelay(100); 31396c19bd3STroy Kisky if (i2c_idle_bus(i2c_regs) < 0) 31496c19bd3STroy Kisky break; 315a7f1a005STroy Kisky } 316a7f1a005STroy Kisky printf("%s: give up i2c_regs=%p\n", __func__, i2c_regs); 317db84140bSMarek Vasut return ret; 318cdace066SSascha Hauer } 319cdace066SSascha Hauer 320db84140bSMarek Vasut /* 321db84140bSMarek Vasut * Read data from I2C device 322db84140bSMarek Vasut */ 323e4ff525fSTroy Kisky int bus_i2c_read(void *base, uchar chip, uint addr, int alen, uchar *buf, 324e4ff525fSTroy Kisky int len) 325db84140bSMarek Vasut { 326db84140bSMarek Vasut int ret; 327db84140bSMarek Vasut unsigned int temp; 328db84140bSMarek Vasut int i; 329e4ff525fSTroy Kisky struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)base; 330cdace066SSascha Hauer 331b230ddc2STroy Kisky ret = i2c_init_transfer(i2c_regs, chip, addr, alen); 332cea60b0cSTroy Kisky if (ret < 0) 333db84140bSMarek Vasut return ret; 334cdace066SSascha Hauer 335db84140bSMarek Vasut temp = readb(&i2c_regs->i2cr); 336db84140bSMarek Vasut temp |= I2CR_RSTA; 337db84140bSMarek Vasut writeb(temp, &i2c_regs->i2cr); 338db84140bSMarek Vasut 339cea60b0cSTroy Kisky ret = tx_byte(i2c_regs, (chip << 1) | 1); 340c4330d28STroy Kisky if (ret < 0) { 34127a5da02STroy Kisky i2c_imx_stop(i2c_regs); 342db84140bSMarek Vasut return ret; 343c4330d28STroy Kisky } 344db84140bSMarek Vasut 345db84140bSMarek Vasut /* setup bus to read data */ 346db84140bSMarek Vasut temp = readb(&i2c_regs->i2cr); 347db84140bSMarek Vasut temp &= ~(I2CR_MTX | I2CR_TX_NO_AK); 348db84140bSMarek Vasut if (len == 1) 349db84140bSMarek Vasut temp |= I2CR_TX_NO_AK; 350db84140bSMarek Vasut writeb(temp, &i2c_regs->i2cr); 35130ea41a4SAlison Wang writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr); 352ea572d85STroy Kisky readb(&i2c_regs->i2dr); /* dummy read to clear ICF */ 353db84140bSMarek Vasut 354db84140bSMarek Vasut /* read data */ 355db84140bSMarek Vasut for (i = 0; i < len; i++) { 3567aa57a01STroy Kisky ret = wait_for_sr_state(i2c_regs, ST_IIF); 3577aa57a01STroy Kisky if (ret < 0) { 35827a5da02STroy Kisky i2c_imx_stop(i2c_regs); 359db84140bSMarek Vasut return ret; 360c4330d28STroy Kisky } 361db84140bSMarek Vasut 362db84140bSMarek Vasut /* 363db84140bSMarek Vasut * It must generate STOP before read I2DR to prevent 364db84140bSMarek Vasut * controller from generating another clock cycle 365db84140bSMarek Vasut */ 366db84140bSMarek Vasut if (i == (len - 1)) { 36727a5da02STroy Kisky i2c_imx_stop(i2c_regs); 368db84140bSMarek Vasut } else if (i == (len - 2)) { 369db84140bSMarek Vasut temp = readb(&i2c_regs->i2cr); 370db84140bSMarek Vasut temp |= I2CR_TX_NO_AK; 371db84140bSMarek Vasut writeb(temp, &i2c_regs->i2cr); 372cdace066SSascha Hauer } 37330ea41a4SAlison Wang writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr); 374db84140bSMarek Vasut buf[i] = readb(&i2c_regs->i2dr); 375cdace066SSascha Hauer } 37627a5da02STroy Kisky i2c_imx_stop(i2c_regs); 3777aa57a01STroy Kisky return 0; 378db84140bSMarek Vasut } 379db84140bSMarek Vasut 380db84140bSMarek Vasut /* 381db84140bSMarek Vasut * Write data to I2C device 382db84140bSMarek Vasut */ 383e4ff525fSTroy Kisky int bus_i2c_write(void *base, uchar chip, uint addr, int alen, 384e4ff525fSTroy Kisky const uchar *buf, int len) 385cdace066SSascha Hauer { 386db84140bSMarek Vasut int ret; 387db84140bSMarek Vasut int i; 388e4ff525fSTroy Kisky struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)base; 389cdace066SSascha Hauer 390b230ddc2STroy Kisky ret = i2c_init_transfer(i2c_regs, chip, addr, alen); 391cea60b0cSTroy Kisky if (ret < 0) 392db84140bSMarek Vasut return ret; 393cdace066SSascha Hauer 394db84140bSMarek Vasut for (i = 0; i < len; i++) { 395cea60b0cSTroy Kisky ret = tx_byte(i2c_regs, buf[i]); 396cea60b0cSTroy Kisky if (ret < 0) 397c4330d28STroy Kisky break; 398cdace066SSascha Hauer } 39927a5da02STroy Kisky i2c_imx_stop(i2c_regs); 400db84140bSMarek Vasut return ret; 401db84140bSMarek Vasut } 402cfbb88d3STroy Kisky 403e4ff525fSTroy Kisky struct i2c_parms { 404e4ff525fSTroy Kisky void *base; 405e4ff525fSTroy Kisky void *idle_bus_data; 406e4ff525fSTroy Kisky int (*idle_bus_fn)(void *p); 407e4ff525fSTroy Kisky }; 408e4ff525fSTroy Kisky 409e4ff525fSTroy Kisky struct sram_data { 410e4ff525fSTroy Kisky unsigned curr_i2c_bus; 411e4ff525fSTroy Kisky struct i2c_parms i2c_data[3]; 412e4ff525fSTroy Kisky }; 413e4ff525fSTroy Kisky 414e4ff525fSTroy Kisky /* 415e4ff525fSTroy Kisky * For SPL boot some boards need i2c before SDRAM is initialized so force 416e4ff525fSTroy Kisky * variables to live in SRAM 417e4ff525fSTroy Kisky */ 418e4ff525fSTroy Kisky static struct sram_data __attribute__((section(".data"))) srdata; 419e4ff525fSTroy Kisky 420*fac96408Strem static void * const i2c_bases[] = { 421*fac96408Strem #if defined(CONFIG_MX25) 422*fac96408Strem (void *)IMX_I2C_BASE, 423*fac96408Strem (void *)IMX_I2C2_BASE, 424*fac96408Strem (void *)IMX_I2C3_BASE 425*fac96408Strem #elif defined(CONFIG_MX27) 426*fac96408Strem (void *)IMX_I2C1_BASE, 427*fac96408Strem (void *)IMX_I2C2_BASE 428*fac96408Strem #elif defined(CONFIG_MX31) || defined(CONFIG_MX35) || \ 429*fac96408Strem defined(CONFIG_MX51) || defined(CONFIG_MX53) || \ 430*fac96408Strem defined(CONFIG_MX6) 431*fac96408Strem (void *)I2C1_BASE_ADDR, 432*fac96408Strem (void *)I2C2_BASE_ADDR, 433*fac96408Strem (void *)I2C3_BASE_ADDR 434*fac96408Strem #elif defined(CONFIG_VF610) 435*fac96408Strem (void *)I2C0_BASE_ADDR 436e4ff525fSTroy Kisky #else 437*fac96408Strem #error "architecture not supported" 438e4ff525fSTroy Kisky #endif 439*fac96408Strem }; 440*fac96408Strem 441*fac96408Strem void *i2c_get_base(struct i2c_adapter *adap) 442*fac96408Strem { 443*fac96408Strem return i2c_bases[adap->hwadapnr]; 444e4ff525fSTroy Kisky } 445e4ff525fSTroy Kisky 44696c19bd3STroy Kisky static struct i2c_parms *i2c_get_parms(void *base) 44796c19bd3STroy Kisky { 44896c19bd3STroy Kisky int i = 0; 44996c19bd3STroy Kisky struct i2c_parms *p = srdata.i2c_data; 45096c19bd3STroy Kisky while (i < ARRAY_SIZE(srdata.i2c_data)) { 45196c19bd3STroy Kisky if (p->base == base) 45296c19bd3STroy Kisky return p; 45396c19bd3STroy Kisky p++; 45496c19bd3STroy Kisky i++; 45596c19bd3STroy Kisky } 45696c19bd3STroy Kisky printf("Invalid I2C base: %p\n", base); 45796c19bd3STroy Kisky return NULL; 45896c19bd3STroy Kisky } 45996c19bd3STroy Kisky 46096c19bd3STroy Kisky static int i2c_idle_bus(void *base) 46196c19bd3STroy Kisky { 46296c19bd3STroy Kisky struct i2c_parms *p = i2c_get_parms(base); 46396c19bd3STroy Kisky if (p && p->idle_bus_fn) 46496c19bd3STroy Kisky return p->idle_bus_fn(p->idle_bus_data); 46596c19bd3STroy Kisky return 0; 46696c19bd3STroy Kisky } 46796c19bd3STroy Kisky 468*fac96408Strem static int mxc_i2c_read(struct i2c_adapter *adap, uint8_t chip, 469*fac96408Strem uint addr, int alen, uint8_t *buffer, 470*fac96408Strem int len) 4719815326dSTroy Kisky { 472*fac96408Strem return bus_i2c_read(i2c_get_base(adap), chip, addr, alen, buffer, len); 4739815326dSTroy Kisky } 4749815326dSTroy Kisky 475*fac96408Strem static int mxc_i2c_write(struct i2c_adapter *adap, uint8_t chip, 476*fac96408Strem uint addr, int alen, uint8_t *buffer, 477*fac96408Strem int len) 4789815326dSTroy Kisky { 479*fac96408Strem return bus_i2c_write(i2c_get_base(adap), chip, addr, alen, buffer, len); 480e4ff525fSTroy Kisky } 481e4ff525fSTroy Kisky 482cfbb88d3STroy Kisky /* 483cfbb88d3STroy Kisky * Test if a chip at a given address responds (probe the chip) 484cfbb88d3STroy Kisky */ 485*fac96408Strem static int mxc_i2c_probe(struct i2c_adapter *adap, uint8_t chip) 486cfbb88d3STroy Kisky { 487*fac96408Strem return bus_i2c_write(i2c_get_base(adap), chip, 0, 0, NULL, 0); 488e4ff525fSTroy Kisky } 489e4ff525fSTroy Kisky 490e4ff525fSTroy Kisky void bus_i2c_init(void *base, int speed, int unused, 491e4ff525fSTroy Kisky int (*idle_bus_fn)(void *p), void *idle_bus_data) 492e4ff525fSTroy Kisky { 493e4ff525fSTroy Kisky int i = 0; 494e4ff525fSTroy Kisky struct i2c_parms *p = srdata.i2c_data; 495e4ff525fSTroy Kisky if (!base) 496e4ff525fSTroy Kisky return; 497e4ff525fSTroy Kisky for (;;) { 498e4ff525fSTroy Kisky if (!p->base || (p->base == base)) { 499e4ff525fSTroy Kisky p->base = base; 500e4ff525fSTroy Kisky if (idle_bus_fn) { 501e4ff525fSTroy Kisky p->idle_bus_fn = idle_bus_fn; 502e4ff525fSTroy Kisky p->idle_bus_data = idle_bus_data; 503e4ff525fSTroy Kisky } 504e4ff525fSTroy Kisky break; 505e4ff525fSTroy Kisky } 506e4ff525fSTroy Kisky p++; 507e4ff525fSTroy Kisky i++; 508e4ff525fSTroy Kisky if (i >= ARRAY_SIZE(srdata.i2c_data)) 509e4ff525fSTroy Kisky return; 510e4ff525fSTroy Kisky } 511e4ff525fSTroy Kisky bus_i2c_set_bus_speed(base, speed); 512e4ff525fSTroy Kisky } 513e4ff525fSTroy Kisky 514e4ff525fSTroy Kisky /* 515e4ff525fSTroy Kisky * Init I2C Bus 516e4ff525fSTroy Kisky */ 517*fac96408Strem static void mxc_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr) 518e4ff525fSTroy Kisky { 519*fac96408Strem bus_i2c_init(i2c_get_base(adap), speed, slaveaddr, NULL, NULL); 520e4ff525fSTroy Kisky } 521e4ff525fSTroy Kisky 522e4ff525fSTroy Kisky /* 523e4ff525fSTroy Kisky * Set I2C Speed 524e4ff525fSTroy Kisky */ 525*fac96408Strem static uint mxc_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed) 526e4ff525fSTroy Kisky { 527*fac96408Strem return bus_i2c_set_bus_speed(i2c_get_base(adap), speed); 528e4ff525fSTroy Kisky } 529e4ff525fSTroy Kisky 530e4ff525fSTroy Kisky /* 531*fac96408Strem * Register mxc i2c adapters 532e4ff525fSTroy Kisky */ 533*fac96408Strem U_BOOT_I2C_ADAP_COMPLETE(mxc0, mxc_i2c_init, mxc_i2c_probe, 534*fac96408Strem mxc_i2c_read, mxc_i2c_write, 535*fac96408Strem mxc_i2c_set_bus_speed, 536*fac96408Strem CONFIG_SYS_MXC_I2C1_SPEED, 537*fac96408Strem CONFIG_SYS_MXC_I2C1_SLAVE, 0) 538*fac96408Strem U_BOOT_I2C_ADAP_COMPLETE(mxc1, mxc_i2c_init, mxc_i2c_probe, 539*fac96408Strem mxc_i2c_read, mxc_i2c_write, 540*fac96408Strem mxc_i2c_set_bus_speed, 541*fac96408Strem CONFIG_SYS_MXC_I2C2_SPEED, 542*fac96408Strem CONFIG_SYS_MXC_I2C2_SLAVE, 1) 543*fac96408Strem #if defined(CONFIG_MX31) || defined(CONFIG_MX35) ||\ 544*fac96408Strem defined(CONFIG_MX51) || defined(CONFIG_MX53) ||\ 545*fac96408Strem defined(CONFIG_MX6) 546*fac96408Strem U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe, 547*fac96408Strem mxc_i2c_read, mxc_i2c_write, 548*fac96408Strem mxc_i2c_set_bus_speed, 549*fac96408Strem CONFIG_SYS_MXC_I2C3_SPEED, 550*fac96408Strem CONFIG_SYS_MXC_I2C3_SLAVE, 2) 551*fac96408Strem #endif 552