1cdace066SSascha Hauer /* 2db84140bSMarek Vasut * i2c driver for Freescale i.MX series 3cdace066SSascha Hauer * 4cdace066SSascha Hauer * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> 5db84140bSMarek Vasut * (c) 2011 Marek Vasut <marek.vasut@gmail.com> 6db84140bSMarek Vasut * 7db84140bSMarek Vasut * Based on i2c-imx.c from linux kernel: 8db84140bSMarek Vasut * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de> 9db84140bSMarek Vasut * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de> 10db84140bSMarek Vasut * Copyright (C) 2007 RightHand Technologies, Inc. 11db84140bSMarek Vasut * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt> 12db84140bSMarek Vasut * 13cdace066SSascha Hauer * 14cdace066SSascha Hauer * See file CREDITS for list of people who contributed to this 15cdace066SSascha Hauer * project. 16cdace066SSascha Hauer * 17cdace066SSascha Hauer * This program is free software; you can redistribute it and/or 18cdace066SSascha Hauer * modify it under the terms of the GNU General Public License as 19cdace066SSascha Hauer * published by the Free Software Foundation; either version 2 of 20cdace066SSascha Hauer * the License, or (at your option) any later version. 21cdace066SSascha Hauer * 22cdace066SSascha Hauer * This program is distributed in the hope that it will be useful, 23cdace066SSascha Hauer * but WITHOUT ANY WARRANTY; without even the implied warranty of 24cdace066SSascha Hauer * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the 25cdace066SSascha Hauer * GNU General Public License for more details. 26cdace066SSascha Hauer * 27cdace066SSascha Hauer * You should have received a copy of the GNU General Public License 28cdace066SSascha Hauer * along with this program; if not, write to the Free Software 29cdace066SSascha Hauer * Foundation, Inc., 59 Temple Place, Suite 330, Boston, 30cdace066SSascha Hauer * MA 02111-1307 USA 31cdace066SSascha Hauer */ 32cdace066SSascha Hauer 33cdace066SSascha Hauer #include <common.h> 34127cec18SLiu Hui-R64343 #include <asm/arch/clock.h> 3586271115SStefano Babic #include <asm/arch/imx-regs.h> 36cea60b0cSTroy Kisky #include <asm/errno.h> 3724cd738bSTroy Kisky #include <asm/io.h> 38bf0783dfSMarek Vasut #include <i2c.h> 39cdace066SSascha Hauer 40db84140bSMarek Vasut struct mxc_i2c_regs { 41db84140bSMarek Vasut uint32_t iadr; 42db84140bSMarek Vasut uint32_t ifdr; 43db84140bSMarek Vasut uint32_t i2cr; 44db84140bSMarek Vasut uint32_t i2sr; 45db84140bSMarek Vasut uint32_t i2dr; 46db84140bSMarek Vasut }; 47cdace066SSascha Hauer 48cdace066SSascha Hauer #define I2CR_IEN (1 << 7) 49cdace066SSascha Hauer #define I2CR_IIEN (1 << 6) 50cdace066SSascha Hauer #define I2CR_MSTA (1 << 5) 51cdace066SSascha Hauer #define I2CR_MTX (1 << 4) 52cdace066SSascha Hauer #define I2CR_TX_NO_AK (1 << 3) 53cdace066SSascha Hauer #define I2CR_RSTA (1 << 2) 54cdace066SSascha Hauer 55cdace066SSascha Hauer #define I2SR_ICF (1 << 7) 56cdace066SSascha Hauer #define I2SR_IBB (1 << 5) 57cdace066SSascha Hauer #define I2SR_IIF (1 << 1) 58cdace066SSascha Hauer #define I2SR_RX_NO_AK (1 << 0) 59cdace066SSascha Hauer 60de6f604dSTroy Kisky #ifdef CONFIG_SYS_I2C_BASE 61de6f604dSTroy Kisky #define I2C_BASE CONFIG_SYS_I2C_BASE 62cdace066SSascha Hauer #else 63de6f604dSTroy Kisky #error "define CONFIG_SYS_I2C_BASE to use the mxc_i2c driver" 64cdace066SSascha Hauer #endif 65cdace066SSascha Hauer 6681687212SStefano Babic #define I2C_MAX_TIMEOUT 10000 67cdace066SSascha Hauer 68db84140bSMarek Vasut static u16 i2c_clk_div[50][2] = { 69db84140bSMarek Vasut { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 }, 70db84140bSMarek Vasut { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 }, 71db84140bSMarek Vasut { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 }, 72db84140bSMarek Vasut { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B }, 73db84140bSMarek Vasut { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A }, 74db84140bSMarek Vasut { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 }, 75db84140bSMarek Vasut { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 }, 76db84140bSMarek Vasut { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 }, 77db84140bSMarek Vasut { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 }, 78db84140bSMarek Vasut { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B }, 79db84140bSMarek Vasut { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E }, 80db84140bSMarek Vasut { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D }, 81db84140bSMarek Vasut { 3072, 0x1E }, { 3840, 0x1F } 82db84140bSMarek Vasut }; 83cdace066SSascha Hauer 84db84140bSMarek Vasut /* 85db84140bSMarek Vasut * Calculate and set proper clock divider 86db84140bSMarek Vasut */ 87bf0783dfSMarek Vasut static uint8_t i2c_imx_get_clk(unsigned int rate) 881d549adeSStefano Babic { 89db84140bSMarek Vasut unsigned int i2c_clk_rate; 90db84140bSMarek Vasut unsigned int div; 91bf0783dfSMarek Vasut u8 clk_div; 92cdace066SSascha Hauer 93127cec18SLiu Hui-R64343 #if defined(CONFIG_MX31) 941d549adeSStefano Babic struct clock_control_regs *sc_regs = 951d549adeSStefano Babic (struct clock_control_regs *)CCM_BASE; 96db84140bSMarek Vasut 97e7de18afSGuennadi Liakhovetski /* start the required I2C clock */ 98de6f604dSTroy Kisky writel(readl(&sc_regs->cgr0) | (3 << CONFIG_SYS_I2C_CLK_OFFSET), 991d549adeSStefano Babic &sc_regs->cgr0); 100127cec18SLiu Hui-R64343 #endif 101e7de18afSGuennadi Liakhovetski 102db84140bSMarek Vasut /* Divider value calculation */ 103db84140bSMarek Vasut i2c_clk_rate = mxc_get_clock(MXC_IPG_PERCLK); 104db84140bSMarek Vasut div = (i2c_clk_rate + rate - 1) / rate; 105db84140bSMarek Vasut if (div < i2c_clk_div[0][0]) 106b567b8ffSMarek Vasut clk_div = 0; 107db84140bSMarek Vasut else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0]) 108b567b8ffSMarek Vasut clk_div = ARRAY_SIZE(i2c_clk_div) - 1; 109db84140bSMarek Vasut else 110b567b8ffSMarek Vasut for (clk_div = 0; i2c_clk_div[clk_div][0] < div; clk_div++) 111db84140bSMarek Vasut ; 112cdace066SSascha Hauer 113db84140bSMarek Vasut /* Store divider value */ 114bf0783dfSMarek Vasut return clk_div; 115db84140bSMarek Vasut } 116cdace066SSascha Hauer 117db84140bSMarek Vasut /* 118db84140bSMarek Vasut * Reset I2C Controller 119db84140bSMarek Vasut */ 120db84140bSMarek Vasut void i2c_reset(void) 121db84140bSMarek Vasut { 122db84140bSMarek Vasut struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 123db84140bSMarek Vasut 124db84140bSMarek Vasut writeb(0, &i2c_regs->i2cr); /* Reset module */ 125db84140bSMarek Vasut writeb(0, &i2c_regs->i2sr); 126db84140bSMarek Vasut } 127db84140bSMarek Vasut 128db84140bSMarek Vasut /* 129db84140bSMarek Vasut * Init I2C Bus 130db84140bSMarek Vasut */ 131db84140bSMarek Vasut void i2c_init(int speed, int unused) 132db84140bSMarek Vasut { 133bf0783dfSMarek Vasut struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 134bf0783dfSMarek Vasut u8 clk_idx = i2c_imx_get_clk(speed); 135bf0783dfSMarek Vasut u8 idx = i2c_clk_div[clk_idx][1]; 136bf0783dfSMarek Vasut 137bf0783dfSMarek Vasut /* Store divider value */ 138bf0783dfSMarek Vasut writeb(idx, &i2c_regs->ifdr); 139bf0783dfSMarek Vasut 1401d549adeSStefano Babic i2c_reset(); 141cdace066SSascha Hauer } 142cdace066SSascha Hauer 143db84140bSMarek Vasut /* 144b567b8ffSMarek Vasut * Set I2C Speed 145b567b8ffSMarek Vasut */ 146b567b8ffSMarek Vasut int i2c_set_bus_speed(unsigned int speed) 147b567b8ffSMarek Vasut { 148b567b8ffSMarek Vasut i2c_init(speed, 0); 149b567b8ffSMarek Vasut return 0; 150b567b8ffSMarek Vasut } 151b567b8ffSMarek Vasut 152b567b8ffSMarek Vasut /* 153b567b8ffSMarek Vasut * Get I2C Speed 154b567b8ffSMarek Vasut */ 155b567b8ffSMarek Vasut unsigned int i2c_get_bus_speed(void) 156b567b8ffSMarek Vasut { 157bf0783dfSMarek Vasut struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 158bf0783dfSMarek Vasut u8 clk_idx = readb(&i2c_regs->ifdr); 159bf0783dfSMarek Vasut u8 clk_div; 160bf0783dfSMarek Vasut 161bf0783dfSMarek Vasut for (clk_div = 0; i2c_clk_div[clk_div][1] != clk_idx; clk_div++) 162bf0783dfSMarek Vasut ; 163bf0783dfSMarek Vasut 164b567b8ffSMarek Vasut return mxc_get_clock(MXC_IPG_PERCLK) / i2c_clk_div[clk_div][0]; 165b567b8ffSMarek Vasut } 166b567b8ffSMarek Vasut 167b567b8ffSMarek Vasut /* 168db84140bSMarek Vasut * Wait for bus to be busy (or free if for_busy = 0) 169db84140bSMarek Vasut * 170db84140bSMarek Vasut * for_busy = 1: Wait for IBB to be asserted 171db84140bSMarek Vasut * for_busy = 0: Wait for IBB to be de-asserted 172db84140bSMarek Vasut */ 173db84140bSMarek Vasut int i2c_imx_bus_busy(int for_busy) 17481687212SStefano Babic { 175db84140bSMarek Vasut struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 176db84140bSMarek Vasut unsigned int temp; 177db84140bSMarek Vasut 17881687212SStefano Babic int timeout = I2C_MAX_TIMEOUT; 17981687212SStefano Babic 180db84140bSMarek Vasut while (timeout--) { 181db84140bSMarek Vasut temp = readb(&i2c_regs->i2sr); 182db84140bSMarek Vasut 183db84140bSMarek Vasut if (for_busy && (temp & I2SR_IBB)) 184db84140bSMarek Vasut return 0; 185db84140bSMarek Vasut if (!for_busy && !(temp & I2SR_IBB)) 186db84140bSMarek Vasut return 0; 187db84140bSMarek Vasut 18881687212SStefano Babic udelay(1); 18981687212SStefano Babic } 190db84140bSMarek Vasut 191db84140bSMarek Vasut return 1; 19281687212SStefano Babic } 19381687212SStefano Babic 194db84140bSMarek Vasut /* 195db84140bSMarek Vasut * Wait for transaction to complete 196db84140bSMarek Vasut */ 197db84140bSMarek Vasut int i2c_imx_trx_complete(void) 198cdace066SSascha Hauer { 199db84140bSMarek Vasut struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 20081687212SStefano Babic int timeout = I2C_MAX_TIMEOUT; 201cdace066SSascha Hauer 202db84140bSMarek Vasut while (timeout--) { 203*ea572d85STroy Kisky if (readb(&i2c_regs->i2sr) & I2SR_IIF) 204cdace066SSascha Hauer return 0; 205cdace066SSascha Hauer 206db84140bSMarek Vasut udelay(1); 207cdace066SSascha Hauer } 208cdace066SSascha Hauer 209cea60b0cSTroy Kisky return -ETIMEDOUT; 210db84140bSMarek Vasut } 211db84140bSMarek Vasut 212cea60b0cSTroy Kisky static int tx_byte(struct mxc_i2c_regs *i2c_regs, u8 byte) 213cdace066SSascha Hauer { 214cea60b0cSTroy Kisky int ret; 215db84140bSMarek Vasut 216*ea572d85STroy Kisky writeb(0, &i2c_regs->i2sr); 217cea60b0cSTroy Kisky writeb(byte, &i2c_regs->i2dr); 218cea60b0cSTroy Kisky ret = i2c_imx_trx_complete(); 219cea60b0cSTroy Kisky if (ret < 0) 220cea60b0cSTroy Kisky return ret; 221cea60b0cSTroy Kisky ret = readb(&i2c_regs->i2sr); 222cea60b0cSTroy Kisky if (ret & I2SR_RX_NO_AK) 223cea60b0cSTroy Kisky return -ENODEV; 224cea60b0cSTroy Kisky return 0; 225db84140bSMarek Vasut } 226db84140bSMarek Vasut 227db84140bSMarek Vasut /* 228db84140bSMarek Vasut * Start the controller 229db84140bSMarek Vasut */ 230db84140bSMarek Vasut int i2c_imx_start(void) 231db84140bSMarek Vasut { 232db84140bSMarek Vasut struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 233db84140bSMarek Vasut unsigned int temp = 0; 234db84140bSMarek Vasut int result; 235db84140bSMarek Vasut 236db84140bSMarek Vasut /* Enable I2C controller */ 237db84140bSMarek Vasut writeb(0, &i2c_regs->i2sr); 238db84140bSMarek Vasut writeb(I2CR_IEN, &i2c_regs->i2cr); 239db84140bSMarek Vasut 240db84140bSMarek Vasut /* Wait controller to be stable */ 241db84140bSMarek Vasut udelay(50); 242db84140bSMarek Vasut 243db84140bSMarek Vasut /* Start I2C transaction */ 244db84140bSMarek Vasut temp = readb(&i2c_regs->i2cr); 245db84140bSMarek Vasut temp |= I2CR_MSTA; 246db84140bSMarek Vasut writeb(temp, &i2c_regs->i2cr); 247db84140bSMarek Vasut 248db84140bSMarek Vasut result = i2c_imx_bus_busy(1); 249db84140bSMarek Vasut if (result) 250db84140bSMarek Vasut return result; 251db84140bSMarek Vasut 252db84140bSMarek Vasut temp |= I2CR_MTX | I2CR_TX_NO_AK; 253db84140bSMarek Vasut writeb(temp, &i2c_regs->i2cr); 254db84140bSMarek Vasut 255db84140bSMarek Vasut return 0; 256db84140bSMarek Vasut } 257db84140bSMarek Vasut 258db84140bSMarek Vasut /* 259db84140bSMarek Vasut * Stop the controller 260db84140bSMarek Vasut */ 261db84140bSMarek Vasut void i2c_imx_stop(void) 262db84140bSMarek Vasut { 263db84140bSMarek Vasut struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 264db84140bSMarek Vasut unsigned int temp = 0; 265db84140bSMarek Vasut 266db84140bSMarek Vasut /* Stop I2C transaction */ 267db84140bSMarek Vasut temp = readb(&i2c_regs->i2cr); 2681c076dbaSTroy Kisky temp &= ~(I2CR_MSTA | I2CR_MTX); 269db84140bSMarek Vasut writeb(temp, &i2c_regs->i2cr); 270db84140bSMarek Vasut 271db84140bSMarek Vasut i2c_imx_bus_busy(0); 272db84140bSMarek Vasut 273db84140bSMarek Vasut /* Disable I2C controller */ 274db84140bSMarek Vasut writeb(0, &i2c_regs->i2cr); 275db84140bSMarek Vasut } 276db84140bSMarek Vasut 277db84140bSMarek Vasut /* 278db84140bSMarek Vasut * Write register address 279db84140bSMarek Vasut */ 280db84140bSMarek Vasut int i2c_imx_set_reg_addr(uint addr, int alen) 281cdace066SSascha Hauer { 282db84140bSMarek Vasut struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 283bf0783dfSMarek Vasut int ret = 0; 284db84140bSMarek Vasut 285bf0783dfSMarek Vasut while (alen--) { 286cea60b0cSTroy Kisky ret = tx_byte(i2c_regs, (addr >> (alen * 8)) & 0xff); 287cea60b0cSTroy Kisky if (ret < 0) 288db84140bSMarek Vasut break; 28981687212SStefano Babic } 290cdace066SSascha Hauer 291db84140bSMarek Vasut return ret; 292cdace066SSascha Hauer } 293cdace066SSascha Hauer 294db84140bSMarek Vasut /* 295db84140bSMarek Vasut * Try if a chip add given address responds (probe the chip) 296db84140bSMarek Vasut */ 297db84140bSMarek Vasut int i2c_probe(uchar chip) 298cdace066SSascha Hauer { 299cea60b0cSTroy Kisky struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 300cdace066SSascha Hauer int ret; 301cdace066SSascha Hauer 302db84140bSMarek Vasut ret = i2c_imx_start(); 303db84140bSMarek Vasut if (ret) 304db84140bSMarek Vasut return ret; 305cdace066SSascha Hauer 306cea60b0cSTroy Kisky ret = tx_byte(i2c_regs, chip << 1); 307db84140bSMarek Vasut i2c_imx_stop(); 308db84140bSMarek Vasut return ret; 309cdace066SSascha Hauer } 310cdace066SSascha Hauer 311db84140bSMarek Vasut /* 312db84140bSMarek Vasut * Read data from I2C device 313db84140bSMarek Vasut */ 314db84140bSMarek Vasut int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len) 315db84140bSMarek Vasut { 316db84140bSMarek Vasut struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 317db84140bSMarek Vasut int ret; 318db84140bSMarek Vasut unsigned int temp; 319db84140bSMarek Vasut int i; 320cdace066SSascha Hauer 321db84140bSMarek Vasut ret = i2c_imx_start(); 322db84140bSMarek Vasut if (ret) 323db84140bSMarek Vasut return ret; 324cdace066SSascha Hauer 325db84140bSMarek Vasut /* write slave address */ 326cea60b0cSTroy Kisky ret = tx_byte(i2c_regs, chip << 1); 327cea60b0cSTroy Kisky if (ret < 0) 328db84140bSMarek Vasut return ret; 329cdace066SSascha Hauer 330db84140bSMarek Vasut ret = i2c_imx_set_reg_addr(addr, alen); 331db84140bSMarek Vasut if (ret) 332db84140bSMarek Vasut return ret; 333cdace066SSascha Hauer 334db84140bSMarek Vasut temp = readb(&i2c_regs->i2cr); 335db84140bSMarek Vasut temp |= I2CR_RSTA; 336db84140bSMarek Vasut writeb(temp, &i2c_regs->i2cr); 337db84140bSMarek Vasut 338cea60b0cSTroy Kisky ret = tx_byte(i2c_regs, (chip << 1) | 1); 339cea60b0cSTroy Kisky if (ret < 0) 340db84140bSMarek Vasut return ret; 341db84140bSMarek Vasut 342db84140bSMarek Vasut /* setup bus to read data */ 343db84140bSMarek Vasut temp = readb(&i2c_regs->i2cr); 344db84140bSMarek Vasut temp &= ~(I2CR_MTX | I2CR_TX_NO_AK); 345db84140bSMarek Vasut if (len == 1) 346db84140bSMarek Vasut temp |= I2CR_TX_NO_AK; 347db84140bSMarek Vasut writeb(temp, &i2c_regs->i2cr); 348*ea572d85STroy Kisky writeb(0, &i2c_regs->i2sr); 349*ea572d85STroy Kisky readb(&i2c_regs->i2dr); /* dummy read to clear ICF */ 350db84140bSMarek Vasut 351db84140bSMarek Vasut /* read data */ 352db84140bSMarek Vasut for (i = 0; i < len; i++) { 353db84140bSMarek Vasut ret = i2c_imx_trx_complete(); 354db84140bSMarek Vasut if (ret) 355db84140bSMarek Vasut return ret; 356db84140bSMarek Vasut 357db84140bSMarek Vasut /* 358db84140bSMarek Vasut * It must generate STOP before read I2DR to prevent 359db84140bSMarek Vasut * controller from generating another clock cycle 360db84140bSMarek Vasut */ 361db84140bSMarek Vasut if (i == (len - 1)) { 362db84140bSMarek Vasut temp = readb(&i2c_regs->i2cr); 363db84140bSMarek Vasut temp &= ~(I2CR_MSTA | I2CR_MTX); 364db84140bSMarek Vasut writeb(temp, &i2c_regs->i2cr); 365db84140bSMarek Vasut i2c_imx_bus_busy(0); 366db84140bSMarek Vasut } else if (i == (len - 2)) { 367db84140bSMarek Vasut temp = readb(&i2c_regs->i2cr); 368db84140bSMarek Vasut temp |= I2CR_TX_NO_AK; 369db84140bSMarek Vasut writeb(temp, &i2c_regs->i2cr); 370cdace066SSascha Hauer } 371cdace066SSascha Hauer 372*ea572d85STroy Kisky writeb(0, &i2c_regs->i2sr); 373db84140bSMarek Vasut buf[i] = readb(&i2c_regs->i2dr); 374cdace066SSascha Hauer } 375cdace066SSascha Hauer 376db84140bSMarek Vasut i2c_imx_stop(); 377db84140bSMarek Vasut 378db84140bSMarek Vasut return ret; 379db84140bSMarek Vasut } 380db84140bSMarek Vasut 381db84140bSMarek Vasut /* 382db84140bSMarek Vasut * Write data to I2C device 383db84140bSMarek Vasut */ 384cdace066SSascha Hauer int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len) 385cdace066SSascha Hauer { 386db84140bSMarek Vasut struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)I2C_BASE; 387db84140bSMarek Vasut int ret; 388db84140bSMarek Vasut int i; 389cdace066SSascha Hauer 390db84140bSMarek Vasut ret = i2c_imx_start(); 391db84140bSMarek Vasut if (ret) 392db84140bSMarek Vasut return ret; 393cdace066SSascha Hauer 394db84140bSMarek Vasut /* write slave address */ 395cea60b0cSTroy Kisky ret = tx_byte(i2c_regs, chip << 1); 396cea60b0cSTroy Kisky if (ret < 0) 397db84140bSMarek Vasut return ret; 398cdace066SSascha Hauer 399db84140bSMarek Vasut ret = i2c_imx_set_reg_addr(addr, alen); 400db84140bSMarek Vasut if (ret) 401db84140bSMarek Vasut return ret; 402cdace066SSascha Hauer 403db84140bSMarek Vasut for (i = 0; i < len; i++) { 404cea60b0cSTroy Kisky ret = tx_byte(i2c_regs, buf[i]); 405cea60b0cSTroy Kisky if (ret < 0) 406db84140bSMarek Vasut return ret; 407cdace066SSascha Hauer } 408cdace066SSascha Hauer 409db84140bSMarek Vasut i2c_imx_stop(); 410db84140bSMarek Vasut 411db84140bSMarek Vasut return ret; 412db84140bSMarek Vasut } 413