1cdace066SSascha Hauer /* 2db84140bSMarek Vasut * i2c driver for Freescale i.MX series 3cdace066SSascha Hauer * 4cdace066SSascha Hauer * (c) 2007 Pengutronix, Sascha Hauer <s.hauer@pengutronix.de> 5db84140bSMarek Vasut * (c) 2011 Marek Vasut <marek.vasut@gmail.com> 6db84140bSMarek Vasut * 7db84140bSMarek Vasut * Based on i2c-imx.c from linux kernel: 8db84140bSMarek Vasut * Copyright (C) 2005 Torsten Koschorrek <koschorrek at synertronixx.de> 9db84140bSMarek Vasut * Copyright (C) 2005 Matthias Blaschke <blaschke at synertronixx.de> 10db84140bSMarek Vasut * Copyright (C) 2007 RightHand Technologies, Inc. 11db84140bSMarek Vasut * Copyright (C) 2008 Darius Augulis <darius.augulis at teltonika.lt> 12db84140bSMarek Vasut * 13cdace066SSascha Hauer * 141a459660SWolfgang Denk * SPDX-License-Identifier: GPL-2.0+ 15cdace066SSascha Hauer */ 16cdace066SSascha Hauer 17cdace066SSascha Hauer #include <common.h> 18127cec18SLiu Hui-R64343 #include <asm/arch/clock.h> 1986271115SStefano Babic #include <asm/arch/imx-regs.h> 20cea60b0cSTroy Kisky #include <asm/errno.h> 2124cd738bSTroy Kisky #include <asm/io.h> 22bf0783dfSMarek Vasut #include <i2c.h> 237aa57a01STroy Kisky #include <watchdog.h> 24cdace066SSascha Hauer 25dec1861bSYork Sun DECLARE_GLOBAL_DATA_PTR; 26dec1861bSYork Sun 2730ea41a4SAlison Wang #ifdef I2C_QUIRK_REG 2830ea41a4SAlison Wang struct mxc_i2c_regs { 2930ea41a4SAlison Wang uint8_t iadr; 3030ea41a4SAlison Wang uint8_t ifdr; 3130ea41a4SAlison Wang uint8_t i2cr; 3230ea41a4SAlison Wang uint8_t i2sr; 3330ea41a4SAlison Wang uint8_t i2dr; 3430ea41a4SAlison Wang }; 3530ea41a4SAlison Wang #else 36db84140bSMarek Vasut struct mxc_i2c_regs { 37db84140bSMarek Vasut uint32_t iadr; 38db84140bSMarek Vasut uint32_t ifdr; 39db84140bSMarek Vasut uint32_t i2cr; 40db84140bSMarek Vasut uint32_t i2sr; 41db84140bSMarek Vasut uint32_t i2dr; 42db84140bSMarek Vasut }; 4330ea41a4SAlison Wang #endif 44cdace066SSascha Hauer 45cdace066SSascha Hauer #define I2CR_IIEN (1 << 6) 46cdace066SSascha Hauer #define I2CR_MSTA (1 << 5) 47cdace066SSascha Hauer #define I2CR_MTX (1 << 4) 48cdace066SSascha Hauer #define I2CR_TX_NO_AK (1 << 3) 49cdace066SSascha Hauer #define I2CR_RSTA (1 << 2) 50cdace066SSascha Hauer 51cdace066SSascha Hauer #define I2SR_ICF (1 << 7) 52cdace066SSascha Hauer #define I2SR_IBB (1 << 5) 53d5383a63STroy Kisky #define I2SR_IAL (1 << 4) 54cdace066SSascha Hauer #define I2SR_IIF (1 << 1) 55cdace066SSascha Hauer #define I2SR_RX_NO_AK (1 << 0) 56cdace066SSascha Hauer 5730ea41a4SAlison Wang #ifdef I2C_QUIRK_REG 5830ea41a4SAlison Wang #define I2CR_IEN (0 << 7) 5930ea41a4SAlison Wang #define I2CR_IDIS (1 << 7) 6030ea41a4SAlison Wang #define I2SR_IIF_CLEAR (1 << 1) 6130ea41a4SAlison Wang #else 6230ea41a4SAlison Wang #define I2CR_IEN (1 << 7) 6330ea41a4SAlison Wang #define I2CR_IDIS (0 << 7) 6430ea41a4SAlison Wang #define I2SR_IIF_CLEAR (0 << 1) 6530ea41a4SAlison Wang #endif 6630ea41a4SAlison Wang 67e4ff525fSTroy Kisky #if defined(CONFIG_HARD_I2C) && !defined(CONFIG_SYS_I2C_BASE) 68de6f604dSTroy Kisky #error "define CONFIG_SYS_I2C_BASE to use the mxc_i2c driver" 69cdace066SSascha Hauer #endif 70cdace066SSascha Hauer 7130ea41a4SAlison Wang #ifdef I2C_QUIRK_REG 7230ea41a4SAlison Wang static u16 i2c_clk_div[60][2] = { 7330ea41a4SAlison Wang { 20, 0x00 }, { 22, 0x01 }, { 24, 0x02 }, { 26, 0x03 }, 7430ea41a4SAlison Wang { 28, 0x04 }, { 30, 0x05 }, { 32, 0x09 }, { 34, 0x06 }, 7530ea41a4SAlison Wang { 36, 0x0A }, { 40, 0x07 }, { 44, 0x0C }, { 48, 0x0D }, 7630ea41a4SAlison Wang { 52, 0x43 }, { 56, 0x0E }, { 60, 0x45 }, { 64, 0x12 }, 7730ea41a4SAlison Wang { 68, 0x0F }, { 72, 0x13 }, { 80, 0x14 }, { 88, 0x15 }, 7830ea41a4SAlison Wang { 96, 0x19 }, { 104, 0x16 }, { 112, 0x1A }, { 128, 0x17 }, 7930ea41a4SAlison Wang { 136, 0x4F }, { 144, 0x1C }, { 160, 0x1D }, { 176, 0x55 }, 8030ea41a4SAlison Wang { 192, 0x1E }, { 208, 0x56 }, { 224, 0x22 }, { 228, 0x24 }, 8130ea41a4SAlison Wang { 240, 0x1F }, { 256, 0x23 }, { 288, 0x5C }, { 320, 0x25 }, 8230ea41a4SAlison Wang { 384, 0x26 }, { 448, 0x2A }, { 480, 0x27 }, { 512, 0x2B }, 8330ea41a4SAlison Wang { 576, 0x2C }, { 640, 0x2D }, { 768, 0x31 }, { 896, 0x32 }, 8430ea41a4SAlison Wang { 960, 0x2F }, { 1024, 0x33 }, { 1152, 0x34 }, { 1280, 0x35 }, 8530ea41a4SAlison Wang { 1536, 0x36 }, { 1792, 0x3A }, { 1920, 0x37 }, { 2048, 0x3B }, 8630ea41a4SAlison Wang { 2304, 0x3C }, { 2560, 0x3D }, { 3072, 0x3E }, { 3584, 0x7A }, 8730ea41a4SAlison Wang { 3840, 0x3F }, { 4096, 0x7B }, { 5120, 0x7D }, { 6144, 0x7E }, 8830ea41a4SAlison Wang }; 8930ea41a4SAlison Wang #else 90db84140bSMarek Vasut static u16 i2c_clk_div[50][2] = { 91db84140bSMarek Vasut { 22, 0x20 }, { 24, 0x21 }, { 26, 0x22 }, { 28, 0x23 }, 92db84140bSMarek Vasut { 30, 0x00 }, { 32, 0x24 }, { 36, 0x25 }, { 40, 0x26 }, 93db84140bSMarek Vasut { 42, 0x03 }, { 44, 0x27 }, { 48, 0x28 }, { 52, 0x05 }, 94db84140bSMarek Vasut { 56, 0x29 }, { 60, 0x06 }, { 64, 0x2A }, { 72, 0x2B }, 95db84140bSMarek Vasut { 80, 0x2C }, { 88, 0x09 }, { 96, 0x2D }, { 104, 0x0A }, 96db84140bSMarek Vasut { 112, 0x2E }, { 128, 0x2F }, { 144, 0x0C }, { 160, 0x30 }, 97db84140bSMarek Vasut { 192, 0x31 }, { 224, 0x32 }, { 240, 0x0F }, { 256, 0x33 }, 98db84140bSMarek Vasut { 288, 0x10 }, { 320, 0x34 }, { 384, 0x35 }, { 448, 0x36 }, 99db84140bSMarek Vasut { 480, 0x13 }, { 512, 0x37 }, { 576, 0x14 }, { 640, 0x38 }, 100db84140bSMarek Vasut { 768, 0x39 }, { 896, 0x3A }, { 960, 0x17 }, { 1024, 0x3B }, 101db84140bSMarek Vasut { 1152, 0x18 }, { 1280, 0x3C }, { 1536, 0x3D }, { 1792, 0x3E }, 102db84140bSMarek Vasut { 1920, 0x1B }, { 2048, 0x3F }, { 2304, 0x1C }, { 2560, 0x1D }, 103db84140bSMarek Vasut { 3072, 0x1E }, { 3840, 0x1F } 104db84140bSMarek Vasut }; 10530ea41a4SAlison Wang #endif 106cdace066SSascha Hauer 107fac96408Strem 108fac96408Strem #ifndef CONFIG_SYS_MXC_I2C1_SPEED 109fac96408Strem #define CONFIG_SYS_MXC_I2C1_SPEED 100000 110fac96408Strem #endif 111fac96408Strem #ifndef CONFIG_SYS_MXC_I2C2_SPEED 112fac96408Strem #define CONFIG_SYS_MXC_I2C2_SPEED 100000 113fac96408Strem #endif 114fac96408Strem #ifndef CONFIG_SYS_MXC_I2C3_SPEED 115fac96408Strem #define CONFIG_SYS_MXC_I2C3_SPEED 100000 116fac96408Strem #endif 117fac96408Strem 118fac96408Strem #ifndef CONFIG_SYS_MXC_I2C1_SLAVE 119fac96408Strem #define CONFIG_SYS_MXC_I2C1_SLAVE 0 120fac96408Strem #endif 121fac96408Strem #ifndef CONFIG_SYS_MXC_I2C2_SLAVE 122fac96408Strem #define CONFIG_SYS_MXC_I2C2_SLAVE 0 123fac96408Strem #endif 124fac96408Strem #ifndef CONFIG_SYS_MXC_I2C3_SLAVE 125fac96408Strem #define CONFIG_SYS_MXC_I2C3_SLAVE 0 126fac96408Strem #endif 127fac96408Strem 128fac96408Strem 129db84140bSMarek Vasut /* 130db84140bSMarek Vasut * Calculate and set proper clock divider 131db84140bSMarek Vasut */ 132bf0783dfSMarek Vasut static uint8_t i2c_imx_get_clk(unsigned int rate) 1331d549adeSStefano Babic { 134db84140bSMarek Vasut unsigned int i2c_clk_rate; 135db84140bSMarek Vasut unsigned int div; 136bf0783dfSMarek Vasut u8 clk_div; 137cdace066SSascha Hauer 138127cec18SLiu Hui-R64343 #if defined(CONFIG_MX31) 1391d549adeSStefano Babic struct clock_control_regs *sc_regs = 1401d549adeSStefano Babic (struct clock_control_regs *)CCM_BASE; 141db84140bSMarek Vasut 142e7de18afSGuennadi Liakhovetski /* start the required I2C clock */ 143de6f604dSTroy Kisky writel(readl(&sc_regs->cgr0) | (3 << CONFIG_SYS_I2C_CLK_OFFSET), 1441d549adeSStefano Babic &sc_regs->cgr0); 145127cec18SLiu Hui-R64343 #endif 146e7de18afSGuennadi Liakhovetski 147db84140bSMarek Vasut /* Divider value calculation */ 148e7bed5c2SMatthias Weisser i2c_clk_rate = mxc_get_clock(MXC_I2C_CLK); 149db84140bSMarek Vasut div = (i2c_clk_rate + rate - 1) / rate; 150db84140bSMarek Vasut if (div < i2c_clk_div[0][0]) 151b567b8ffSMarek Vasut clk_div = 0; 152db84140bSMarek Vasut else if (div > i2c_clk_div[ARRAY_SIZE(i2c_clk_div) - 1][0]) 153b567b8ffSMarek Vasut clk_div = ARRAY_SIZE(i2c_clk_div) - 1; 154db84140bSMarek Vasut else 155b567b8ffSMarek Vasut for (clk_div = 0; i2c_clk_div[clk_div][0] < div; clk_div++) 156db84140bSMarek Vasut ; 157cdace066SSascha Hauer 158db84140bSMarek Vasut /* Store divider value */ 159bf0783dfSMarek Vasut return clk_div; 160db84140bSMarek Vasut } 161cdace066SSascha Hauer 162db84140bSMarek Vasut /* 163e4ff525fSTroy Kisky * Set I2C Bus speed 164db84140bSMarek Vasut */ 1657f86bd57SMarek Vasut static int bus_i2c_set_bus_speed(void *base, int speed) 166db84140bSMarek Vasut { 167e4ff525fSTroy Kisky struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)base; 168bf0783dfSMarek Vasut u8 clk_idx = i2c_imx_get_clk(speed); 169bf0783dfSMarek Vasut u8 idx = i2c_clk_div[clk_idx][1]; 170bf0783dfSMarek Vasut 171bf0783dfSMarek Vasut /* Store divider value */ 172bf0783dfSMarek Vasut writeb(idx, &i2c_regs->ifdr); 173bf0783dfSMarek Vasut 17483a1a190STroy Kisky /* Reset module */ 17530ea41a4SAlison Wang writeb(I2CR_IDIS, &i2c_regs->i2cr); 17683a1a190STroy Kisky writeb(0, &i2c_regs->i2sr); 177b567b8ffSMarek Vasut return 0; 178b567b8ffSMarek Vasut } 179b567b8ffSMarek Vasut 1807aa57a01STroy Kisky #define ST_BUS_IDLE (0 | (I2SR_IBB << 8)) 1817aa57a01STroy Kisky #define ST_BUS_BUSY (I2SR_IBB | (I2SR_IBB << 8)) 1827aa57a01STroy Kisky #define ST_IIF (I2SR_IIF | (I2SR_IIF << 8)) 1837aa57a01STroy Kisky 1847aa57a01STroy Kisky static int wait_for_sr_state(struct mxc_i2c_regs *i2c_regs, unsigned state) 18581687212SStefano Babic { 1867aa57a01STroy Kisky unsigned sr; 1877aa57a01STroy Kisky ulong elapsed; 1887aa57a01STroy Kisky ulong start_time = get_timer(0); 1897aa57a01STroy Kisky for (;;) { 1907aa57a01STroy Kisky sr = readb(&i2c_regs->i2sr); 191d5383a63STroy Kisky if (sr & I2SR_IAL) { 19230ea41a4SAlison Wang #ifdef I2C_QUIRK_REG 19330ea41a4SAlison Wang writeb(sr | I2SR_IAL, &i2c_regs->i2sr); 19430ea41a4SAlison Wang #else 195d5383a63STroy Kisky writeb(sr & ~I2SR_IAL, &i2c_regs->i2sr); 19630ea41a4SAlison Wang #endif 197d5383a63STroy Kisky printf("%s: Arbitration lost sr=%x cr=%x state=%x\n", 198d5383a63STroy Kisky __func__, sr, readb(&i2c_regs->i2cr), state); 199d5383a63STroy Kisky return -ERESTART; 200d5383a63STroy Kisky } 2017aa57a01STroy Kisky if ((sr & (state >> 8)) == (unsigned char)state) 2027aa57a01STroy Kisky return sr; 2037aa57a01STroy Kisky WATCHDOG_RESET(); 2047aa57a01STroy Kisky elapsed = get_timer(start_time); 2057aa57a01STroy Kisky if (elapsed > (CONFIG_SYS_HZ / 10)) /* .1 seconds */ 2067aa57a01STroy Kisky break; 20781687212SStefano Babic } 2087aa57a01STroy Kisky printf("%s: failed sr=%x cr=%x state=%x\n", __func__, 2097aa57a01STroy Kisky sr, readb(&i2c_regs->i2cr), state); 210cea60b0cSTroy Kisky return -ETIMEDOUT; 211db84140bSMarek Vasut } 212db84140bSMarek Vasut 213cea60b0cSTroy Kisky static int tx_byte(struct mxc_i2c_regs *i2c_regs, u8 byte) 214cdace066SSascha Hauer { 215cea60b0cSTroy Kisky int ret; 216db84140bSMarek Vasut 21730ea41a4SAlison Wang writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr); 218cea60b0cSTroy Kisky writeb(byte, &i2c_regs->i2dr); 2197aa57a01STroy Kisky ret = wait_for_sr_state(i2c_regs, ST_IIF); 220cea60b0cSTroy Kisky if (ret < 0) 221cea60b0cSTroy Kisky return ret; 222cea60b0cSTroy Kisky if (ret & I2SR_RX_NO_AK) 223cea60b0cSTroy Kisky return -ENODEV; 224cea60b0cSTroy Kisky return 0; 225db84140bSMarek Vasut } 226db84140bSMarek Vasut 227db84140bSMarek Vasut /* 22890a5b70fSTroy Kisky * Stop I2C transaction 229db84140bSMarek Vasut */ 23027a5da02STroy Kisky static void i2c_imx_stop(struct mxc_i2c_regs *i2c_regs) 231db84140bSMarek Vasut { 2327aa57a01STroy Kisky int ret; 23390a5b70fSTroy Kisky unsigned int temp = readb(&i2c_regs->i2cr); 234db84140bSMarek Vasut 2351c076dbaSTroy Kisky temp &= ~(I2CR_MSTA | I2CR_MTX); 236db84140bSMarek Vasut writeb(temp, &i2c_regs->i2cr); 2377aa57a01STroy Kisky ret = wait_for_sr_state(i2c_regs, ST_BUS_IDLE); 2387aa57a01STroy Kisky if (ret < 0) 2397aa57a01STroy Kisky printf("%s:trigger stop failed\n", __func__); 240db84140bSMarek Vasut } 241db84140bSMarek Vasut 242db84140bSMarek Vasut /* 243b230ddc2STroy Kisky * Send start signal, chip address and 244b230ddc2STroy Kisky * write register address 245db84140bSMarek Vasut */ 246a7f1a005STroy Kisky static int i2c_init_transfer_(struct mxc_i2c_regs *i2c_regs, 247b230ddc2STroy Kisky uchar chip, uint addr, int alen) 248cdace066SSascha Hauer { 24971e9f3cbSTroy Kisky unsigned int temp; 25071e9f3cbSTroy Kisky int ret; 25171e9f3cbSTroy Kisky 25271e9f3cbSTroy Kisky /* Enable I2C controller */ 25330ea41a4SAlison Wang #ifdef I2C_QUIRK_REG 25430ea41a4SAlison Wang if (readb(&i2c_regs->i2cr) & I2CR_IDIS) { 25530ea41a4SAlison Wang #else 25690a5b70fSTroy Kisky if (!(readb(&i2c_regs->i2cr) & I2CR_IEN)) { 25730ea41a4SAlison Wang #endif 25871e9f3cbSTroy Kisky writeb(I2CR_IEN, &i2c_regs->i2cr); 25971e9f3cbSTroy Kisky /* Wait for controller to be stable */ 26071e9f3cbSTroy Kisky udelay(50); 26190a5b70fSTroy Kisky } 262ca741da1STroy Kisky if (readb(&i2c_regs->iadr) == (chip << 1)) 263ca741da1STroy Kisky writeb((chip << 1) ^ 2, &i2c_regs->iadr); 26430ea41a4SAlison Wang writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr); 26590a5b70fSTroy Kisky ret = wait_for_sr_state(i2c_regs, ST_BUS_IDLE); 26690a5b70fSTroy Kisky if (ret < 0) 267a7f1a005STroy Kisky return ret; 26871e9f3cbSTroy Kisky 26971e9f3cbSTroy Kisky /* Start I2C transaction */ 27071e9f3cbSTroy Kisky temp = readb(&i2c_regs->i2cr); 27171e9f3cbSTroy Kisky temp |= I2CR_MSTA; 27271e9f3cbSTroy Kisky writeb(temp, &i2c_regs->i2cr); 27371e9f3cbSTroy Kisky 27471e9f3cbSTroy Kisky ret = wait_for_sr_state(i2c_regs, ST_BUS_BUSY); 27571e9f3cbSTroy Kisky if (ret < 0) 276a7f1a005STroy Kisky return ret; 277b230ddc2STroy Kisky 27871e9f3cbSTroy Kisky temp |= I2CR_MTX | I2CR_TX_NO_AK; 27971e9f3cbSTroy Kisky writeb(temp, &i2c_regs->i2cr); 28071e9f3cbSTroy Kisky 281b230ddc2STroy Kisky /* write slave address */ 282b230ddc2STroy Kisky ret = tx_byte(i2c_regs, chip << 1); 283b230ddc2STroy Kisky if (ret < 0) 284a7f1a005STroy Kisky return ret; 285db84140bSMarek Vasut 286bf0783dfSMarek Vasut while (alen--) { 287cea60b0cSTroy Kisky ret = tx_byte(i2c_regs, (addr >> (alen * 8)) & 0xff); 288cea60b0cSTroy Kisky if (ret < 0) 289a7f1a005STroy Kisky return ret; 29081687212SStefano Babic } 291b230ddc2STroy Kisky return 0; 292a7f1a005STroy Kisky } 293a7f1a005STroy Kisky 29496c19bd3STroy Kisky static int i2c_idle_bus(void *base); 29596c19bd3STroy Kisky 296a7f1a005STroy Kisky static int i2c_init_transfer(struct mxc_i2c_regs *i2c_regs, 297a7f1a005STroy Kisky uchar chip, uint addr, int alen) 298a7f1a005STroy Kisky { 299a7f1a005STroy Kisky int retry; 300a7f1a005STroy Kisky int ret; 301a7f1a005STroy Kisky for (retry = 0; retry < 3; retry++) { 302a7f1a005STroy Kisky ret = i2c_init_transfer_(i2c_regs, chip, addr, alen); 303a7f1a005STroy Kisky if (ret >= 0) 304a7f1a005STroy Kisky return 0; 30527a5da02STroy Kisky i2c_imx_stop(i2c_regs); 306a7f1a005STroy Kisky if (ret == -ENODEV) 307a7f1a005STroy Kisky return ret; 308a7f1a005STroy Kisky 309a7f1a005STroy Kisky printf("%s: failed for chip 0x%x retry=%d\n", __func__, chip, 310a7f1a005STroy Kisky retry); 311a7f1a005STroy Kisky if (ret != -ERESTART) 31230ea41a4SAlison Wang /* Disable controller */ 31330ea41a4SAlison Wang writeb(I2CR_IDIS, &i2c_regs->i2cr); 314a7f1a005STroy Kisky udelay(100); 31596c19bd3STroy Kisky if (i2c_idle_bus(i2c_regs) < 0) 31696c19bd3STroy Kisky break; 317a7f1a005STroy Kisky } 318a7f1a005STroy Kisky printf("%s: give up i2c_regs=%p\n", __func__, i2c_regs); 319db84140bSMarek Vasut return ret; 320cdace066SSascha Hauer } 321cdace066SSascha Hauer 322db84140bSMarek Vasut /* 323db84140bSMarek Vasut * Read data from I2C device 324db84140bSMarek Vasut */ 325e4ff525fSTroy Kisky int bus_i2c_read(void *base, uchar chip, uint addr, int alen, uchar *buf, 326e4ff525fSTroy Kisky int len) 327db84140bSMarek Vasut { 328db84140bSMarek Vasut int ret; 329db84140bSMarek Vasut unsigned int temp; 330db84140bSMarek Vasut int i; 331e4ff525fSTroy Kisky struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)base; 332cdace066SSascha Hauer 333b230ddc2STroy Kisky ret = i2c_init_transfer(i2c_regs, chip, addr, alen); 334cea60b0cSTroy Kisky if (ret < 0) 335db84140bSMarek Vasut return ret; 336cdace066SSascha Hauer 337db84140bSMarek Vasut temp = readb(&i2c_regs->i2cr); 338db84140bSMarek Vasut temp |= I2CR_RSTA; 339db84140bSMarek Vasut writeb(temp, &i2c_regs->i2cr); 340db84140bSMarek Vasut 341cea60b0cSTroy Kisky ret = tx_byte(i2c_regs, (chip << 1) | 1); 342c4330d28STroy Kisky if (ret < 0) { 34327a5da02STroy Kisky i2c_imx_stop(i2c_regs); 344db84140bSMarek Vasut return ret; 345c4330d28STroy Kisky } 346db84140bSMarek Vasut 347db84140bSMarek Vasut /* setup bus to read data */ 348db84140bSMarek Vasut temp = readb(&i2c_regs->i2cr); 349db84140bSMarek Vasut temp &= ~(I2CR_MTX | I2CR_TX_NO_AK); 350db84140bSMarek Vasut if (len == 1) 351db84140bSMarek Vasut temp |= I2CR_TX_NO_AK; 352db84140bSMarek Vasut writeb(temp, &i2c_regs->i2cr); 35330ea41a4SAlison Wang writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr); 354ea572d85STroy Kisky readb(&i2c_regs->i2dr); /* dummy read to clear ICF */ 355db84140bSMarek Vasut 356db84140bSMarek Vasut /* read data */ 357db84140bSMarek Vasut for (i = 0; i < len; i++) { 3587aa57a01STroy Kisky ret = wait_for_sr_state(i2c_regs, ST_IIF); 3597aa57a01STroy Kisky if (ret < 0) { 36027a5da02STroy Kisky i2c_imx_stop(i2c_regs); 361db84140bSMarek Vasut return ret; 362c4330d28STroy Kisky } 363db84140bSMarek Vasut 364db84140bSMarek Vasut /* 365db84140bSMarek Vasut * It must generate STOP before read I2DR to prevent 366db84140bSMarek Vasut * controller from generating another clock cycle 367db84140bSMarek Vasut */ 368db84140bSMarek Vasut if (i == (len - 1)) { 36927a5da02STroy Kisky i2c_imx_stop(i2c_regs); 370db84140bSMarek Vasut } else if (i == (len - 2)) { 371db84140bSMarek Vasut temp = readb(&i2c_regs->i2cr); 372db84140bSMarek Vasut temp |= I2CR_TX_NO_AK; 373db84140bSMarek Vasut writeb(temp, &i2c_regs->i2cr); 374cdace066SSascha Hauer } 37530ea41a4SAlison Wang writeb(I2SR_IIF_CLEAR, &i2c_regs->i2sr); 376db84140bSMarek Vasut buf[i] = readb(&i2c_regs->i2dr); 377cdace066SSascha Hauer } 37827a5da02STroy Kisky i2c_imx_stop(i2c_regs); 3797aa57a01STroy Kisky return 0; 380db84140bSMarek Vasut } 381db84140bSMarek Vasut 382db84140bSMarek Vasut /* 383db84140bSMarek Vasut * Write data to I2C device 384db84140bSMarek Vasut */ 385e4ff525fSTroy Kisky int bus_i2c_write(void *base, uchar chip, uint addr, int alen, 386e4ff525fSTroy Kisky const uchar *buf, int len) 387cdace066SSascha Hauer { 388db84140bSMarek Vasut int ret; 389db84140bSMarek Vasut int i; 390e4ff525fSTroy Kisky struct mxc_i2c_regs *i2c_regs = (struct mxc_i2c_regs *)base; 391cdace066SSascha Hauer 392b230ddc2STroy Kisky ret = i2c_init_transfer(i2c_regs, chip, addr, alen); 393cea60b0cSTroy Kisky if (ret < 0) 394db84140bSMarek Vasut return ret; 395cdace066SSascha Hauer 396db84140bSMarek Vasut for (i = 0; i < len; i++) { 397cea60b0cSTroy Kisky ret = tx_byte(i2c_regs, buf[i]); 398cea60b0cSTroy Kisky if (ret < 0) 399c4330d28STroy Kisky break; 400cdace066SSascha Hauer } 40127a5da02STroy Kisky i2c_imx_stop(i2c_regs); 402db84140bSMarek Vasut return ret; 403db84140bSMarek Vasut } 404cfbb88d3STroy Kisky 405e4ff525fSTroy Kisky struct i2c_parms { 406e4ff525fSTroy Kisky void *base; 407e4ff525fSTroy Kisky void *idle_bus_data; 408e4ff525fSTroy Kisky int (*idle_bus_fn)(void *p); 409e4ff525fSTroy Kisky }; 410e4ff525fSTroy Kisky 411e4ff525fSTroy Kisky struct sram_data { 412e4ff525fSTroy Kisky unsigned curr_i2c_bus; 413e4ff525fSTroy Kisky struct i2c_parms i2c_data[3]; 414e4ff525fSTroy Kisky }; 415e4ff525fSTroy Kisky 416fac96408Strem static void * const i2c_bases[] = { 417fac96408Strem #if defined(CONFIG_MX25) 418fac96408Strem (void *)IMX_I2C_BASE, 419fac96408Strem (void *)IMX_I2C2_BASE, 420fac96408Strem (void *)IMX_I2C3_BASE 421fac96408Strem #elif defined(CONFIG_MX27) 422fac96408Strem (void *)IMX_I2C1_BASE, 423fac96408Strem (void *)IMX_I2C2_BASE 424fac96408Strem #elif defined(CONFIG_MX31) || defined(CONFIG_MX35) || \ 425fac96408Strem defined(CONFIG_MX51) || defined(CONFIG_MX53) || \ 426fac96408Strem defined(CONFIG_MX6) 427fac96408Strem (void *)I2C1_BASE_ADDR, 428fac96408Strem (void *)I2C2_BASE_ADDR, 429fac96408Strem (void *)I2C3_BASE_ADDR 430fac96408Strem #elif defined(CONFIG_VF610) 431fac96408Strem (void *)I2C0_BASE_ADDR 432*2f78eae5SYork Sun #elif defined(CONFIG_FSL_LSCH3) 433*2f78eae5SYork Sun (void *)I2C1_BASE_ADDR, 434*2f78eae5SYork Sun (void *)I2C2_BASE_ADDR, 435*2f78eae5SYork Sun (void *)I2C3_BASE_ADDR, 436*2f78eae5SYork Sun (void *)I2C4_BASE_ADDR 437e4ff525fSTroy Kisky #else 438fac96408Strem #error "architecture not supported" 439e4ff525fSTroy Kisky #endif 440fac96408Strem }; 441fac96408Strem 442fac96408Strem void *i2c_get_base(struct i2c_adapter *adap) 443fac96408Strem { 444fac96408Strem return i2c_bases[adap->hwadapnr]; 445e4ff525fSTroy Kisky } 446e4ff525fSTroy Kisky 44796c19bd3STroy Kisky static struct i2c_parms *i2c_get_parms(void *base) 44896c19bd3STroy Kisky { 449dec1861bSYork Sun struct sram_data *srdata = (void *)gd->srdata; 45096c19bd3STroy Kisky int i = 0; 451dec1861bSYork Sun struct i2c_parms *p = srdata->i2c_data; 452dec1861bSYork Sun while (i < ARRAY_SIZE(srdata->i2c_data)) { 45396c19bd3STroy Kisky if (p->base == base) 45496c19bd3STroy Kisky return p; 45596c19bd3STroy Kisky p++; 45696c19bd3STroy Kisky i++; 45796c19bd3STroy Kisky } 45896c19bd3STroy Kisky printf("Invalid I2C base: %p\n", base); 45996c19bd3STroy Kisky return NULL; 46096c19bd3STroy Kisky } 46196c19bd3STroy Kisky 46296c19bd3STroy Kisky static int i2c_idle_bus(void *base) 46396c19bd3STroy Kisky { 46496c19bd3STroy Kisky struct i2c_parms *p = i2c_get_parms(base); 46596c19bd3STroy Kisky if (p && p->idle_bus_fn) 46696c19bd3STroy Kisky return p->idle_bus_fn(p->idle_bus_data); 46796c19bd3STroy Kisky return 0; 46896c19bd3STroy Kisky } 46996c19bd3STroy Kisky 470fac96408Strem static int mxc_i2c_read(struct i2c_adapter *adap, uint8_t chip, 471fac96408Strem uint addr, int alen, uint8_t *buffer, 472fac96408Strem int len) 4739815326dSTroy Kisky { 474fac96408Strem return bus_i2c_read(i2c_get_base(adap), chip, addr, alen, buffer, len); 4759815326dSTroy Kisky } 4769815326dSTroy Kisky 477fac96408Strem static int mxc_i2c_write(struct i2c_adapter *adap, uint8_t chip, 478fac96408Strem uint addr, int alen, uint8_t *buffer, 479fac96408Strem int len) 4809815326dSTroy Kisky { 481fac96408Strem return bus_i2c_write(i2c_get_base(adap), chip, addr, alen, buffer, len); 482e4ff525fSTroy Kisky } 483e4ff525fSTroy Kisky 484cfbb88d3STroy Kisky /* 485cfbb88d3STroy Kisky * Test if a chip at a given address responds (probe the chip) 486cfbb88d3STroy Kisky */ 487fac96408Strem static int mxc_i2c_probe(struct i2c_adapter *adap, uint8_t chip) 488cfbb88d3STroy Kisky { 489fac96408Strem return bus_i2c_write(i2c_get_base(adap), chip, 0, 0, NULL, 0); 490e4ff525fSTroy Kisky } 491e4ff525fSTroy Kisky 492e4ff525fSTroy Kisky void bus_i2c_init(void *base, int speed, int unused, 493e4ff525fSTroy Kisky int (*idle_bus_fn)(void *p), void *idle_bus_data) 494e4ff525fSTroy Kisky { 495dec1861bSYork Sun struct sram_data *srdata = (void *)gd->srdata; 496e4ff525fSTroy Kisky int i = 0; 497dec1861bSYork Sun struct i2c_parms *p = srdata->i2c_data; 498e4ff525fSTroy Kisky if (!base) 499e4ff525fSTroy Kisky return; 500e4ff525fSTroy Kisky for (;;) { 501e4ff525fSTroy Kisky if (!p->base || (p->base == base)) { 502e4ff525fSTroy Kisky p->base = base; 503e4ff525fSTroy Kisky if (idle_bus_fn) { 504e4ff525fSTroy Kisky p->idle_bus_fn = idle_bus_fn; 505e4ff525fSTroy Kisky p->idle_bus_data = idle_bus_data; 506e4ff525fSTroy Kisky } 507e4ff525fSTroy Kisky break; 508e4ff525fSTroy Kisky } 509e4ff525fSTroy Kisky p++; 510e4ff525fSTroy Kisky i++; 511dec1861bSYork Sun if (i >= ARRAY_SIZE(srdata->i2c_data)) 512e4ff525fSTroy Kisky return; 513e4ff525fSTroy Kisky } 514e4ff525fSTroy Kisky bus_i2c_set_bus_speed(base, speed); 515e4ff525fSTroy Kisky } 516e4ff525fSTroy Kisky 517e4ff525fSTroy Kisky /* 518e4ff525fSTroy Kisky * Init I2C Bus 519e4ff525fSTroy Kisky */ 520fac96408Strem static void mxc_i2c_init(struct i2c_adapter *adap, int speed, int slaveaddr) 521e4ff525fSTroy Kisky { 522fac96408Strem bus_i2c_init(i2c_get_base(adap), speed, slaveaddr, NULL, NULL); 523e4ff525fSTroy Kisky } 524e4ff525fSTroy Kisky 525e4ff525fSTroy Kisky /* 526e4ff525fSTroy Kisky * Set I2C Speed 527e4ff525fSTroy Kisky */ 528fac96408Strem static uint mxc_i2c_set_bus_speed(struct i2c_adapter *adap, uint speed) 529e4ff525fSTroy Kisky { 530fac96408Strem return bus_i2c_set_bus_speed(i2c_get_base(adap), speed); 531e4ff525fSTroy Kisky } 532e4ff525fSTroy Kisky 533e4ff525fSTroy Kisky /* 534fac96408Strem * Register mxc i2c adapters 535e4ff525fSTroy Kisky */ 536fac96408Strem U_BOOT_I2C_ADAP_COMPLETE(mxc0, mxc_i2c_init, mxc_i2c_probe, 537fac96408Strem mxc_i2c_read, mxc_i2c_write, 538fac96408Strem mxc_i2c_set_bus_speed, 539fac96408Strem CONFIG_SYS_MXC_I2C1_SPEED, 540fac96408Strem CONFIG_SYS_MXC_I2C1_SLAVE, 0) 541fac96408Strem U_BOOT_I2C_ADAP_COMPLETE(mxc1, mxc_i2c_init, mxc_i2c_probe, 542fac96408Strem mxc_i2c_read, mxc_i2c_write, 543fac96408Strem mxc_i2c_set_bus_speed, 544fac96408Strem CONFIG_SYS_MXC_I2C2_SPEED, 545fac96408Strem CONFIG_SYS_MXC_I2C2_SLAVE, 1) 546fac96408Strem #if defined(CONFIG_MX31) || defined(CONFIG_MX35) ||\ 547fac96408Strem defined(CONFIG_MX51) || defined(CONFIG_MX53) ||\ 548fac96408Strem defined(CONFIG_MX6) 549fac96408Strem U_BOOT_I2C_ADAP_COMPLETE(mxc2, mxc_i2c_init, mxc_i2c_probe, 550fac96408Strem mxc_i2c_read, mxc_i2c_write, 551fac96408Strem mxc_i2c_set_bus_speed, 552fac96408Strem CONFIG_SYS_MXC_I2C3_SPEED, 553fac96408Strem CONFIG_SYS_MXC_I2C3_SLAVE, 2) 554fac96408Strem #endif 555